Chip and electronic device

Abstract

The application discloses a chip and an electronic device, and relates to the technical field of chips; the chip comprises a chip body and a plurality of pad structures, a plurality of solder mask window structures are arranged on the chip body, and the plurality of pad structures are one-to-one welded with the solder mask window structures, wherein the area of the orthographic projection of the pad structure on the chip body is greater than or equal to the area of the orthographic projection of the solder mask window structure on the chip body; the above design improves the welding firmness.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more particularly to a chip and an electronic device. Background Technology

[0002] In SSD manufacturing, red ink verification is a commonly used method for inspecting solder joint quality. It is used to assess whether there are cracks or incomplete soldering issues. If the red dye penetrates the interface between the solder ball and the pad, it indicates that there is a crack or insufficient solder strength, and the verification fails.

[0003] The main reason for incomplete soldering is the "weak adhesion zone" caused by the size mismatch between the pad structure and the solder mask opening structure. In existing chips, the size of the pad structure is smaller than the size of the solder mask opening structure. This results in an exposed substrate area between the edges of the pad structure and the solder mask opening structure. During soldering, the solder paste cannot form a strong bond with the exposed chip body. This area becomes a natural mechanical weak point; when subjected to stress, cracks can easily initiate and propagate from here, providing a channel for red ink penetration. Utility Model Content

[0004] The purpose of this application is to provide a chip and electronic device that improves solder joint strength.

[0005] This application discloses a chip, including a chip body and multiple pad structures. The chip body has multiple solder mask opening structures, and the multiple pad structures are soldered one-to-one with the solder mask opening structures. The area of ​​the orthographic projection of the pad structure on the chip body is greater than or equal to the area of ​​the orthographic projection of the solder mask opening structure on the chip body.

[0006] Optionally, the plurality of solder mask opening structures include a plurality of central solder mask openings and a plurality of edge solder mask openings. The plurality of central solder mask openings are disposed in the central region of the chip body, and the plurality of edge solder mask openings are disposed around the perimeter of the chip body. The plurality of pad structures include a plurality of central pads and a plurality of edge pads. The plurality of central pads are disposed in a one-to-one correspondence with the plurality of central solder mask openings, and the plurality of edge pads are welded in a one-to-one correspondence with the plurality of edge solder mask openings to form an edge pad structure. The area of ​​the orthographic projection of the central solder mask opening on the chip body is greater than the area of ​​the orthographic projection of the central pad on the chip body; the area of ​​the orthographic projection of the edge pad on the chip body is greater than or equal to the area of ​​the orthographic projection of the edge solder mask opening on the chip body.

[0007] Optionally, the area of ​​the edge pad projected onto the chip body is larger than the area of ​​the edge solder mask opening projected onto the chip body.

[0008] Optionally, the size of the edge pad is 18mil to 20mil, and the size of the edge solder resist opening is 16mil to 18mil.

[0009] Optionally, the chip further comprises a bump structure, the bump structure is arranged in the edge solder resist opening; wherein the bump structure is a cross-shaped structure.

[0010] Optionally, the chip further comprises a plurality of edge traces, two adjacent edge pad structures are connected through the edge trace, and the edge trace is a non-signal trace.

[0011] Optionally, every two adjacent edge pad structures are correspondingly connected through one edge trace to form a square-shaped structure; or every two edge pad structures are cross-connected through one edge trace to form an X-shaped structure.

[0012] Optionally, the width of each edge trace is 3mil-5mil.

[0013] Optionally, the plurality of edge traces comprises a plurality of sub-edge traces, two adjacent edge pad structures are connected through a plurality of the sub-edge traces, the plurality of sub-edge traces between two adjacent edge pad structures are arranged to form a connection region, and the width of the connection region is 3mil-5mil.

[0014] The present application further discloses an electronic device, comprising the chip as described above.

[0015] Compared with the solution where the size of the pad structure is smaller than the size of the solder resist layer opening structure, during soldering, the solder paste cannot form a firm bond with the exposed chip body, so that when the region is subjected to stress, cracks are very easy to initiate and propagate from this position, the chip of the present application includes a chip body and a plurality of pad structures, the chip body is provided with a plurality of solder resist opening structures, the plurality of pad structures are soldered in one-to-one correspondence with the solder resist opening structures, wherein the area of the orthographic projection of the pad structure on the chip body is greater than or equal to the area of the orthographic projection of the solder resist opening structure on the chip body, that is, the soldering area between the pad structure and the solder resist opening structure is at least equal, so that during soldering, the pad structure at least covers the solder resist opening structure, no exposed region exists between the edge of the solder resist opening structure and the edge of the pad structure, and the soldering solder paste fills the soldering area, which enhances the overall mechanical stress resistance of the soldering area, makes it difficult to generate cracks at this position, and thus can improve the overall mechanical stability of the chip. Brief Description of the Drawings

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a schematic diagram of the chip structure provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of some edge pads provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of edge pads and edge traces provided in an embodiment of this application; Figure 4 This is a schematic diagram of another edge pad structure and edge trace matching provided in the embodiments of this application; Figure 5 This is a block diagram of the electronic device provided in the embodiments of this application.

[0017] Among them: 10, electronic equipment; 100, chip; 110, chip body; 120, pad structure; 121, center pad; 122, edge pad; 130, solder mask opening structure; 131, center solder mask opening; 132, edge solder mask opening; 140, protrusion structure; 150, edge trace; 151, sub-edge trace; 160, edge pad structure; 170, connection area. Detailed Implementation

[0018] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0019] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of indicated technical features. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean a non-exclusive inclusion, which may include or add one or more other features, integers, steps, operations, units, components, and / or combinations thereof. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0020] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] Figure 1 This is a schematic diagram of the chip structure provided in the embodiments of this application, such as... Figure 1 As shown, this application discloses a chip 100, including a chip body 110 and a plurality of pad structures 120. The chip body 110 is provided with a plurality of solder resist opening structures 130. The plurality of pad structures 120 are soldered one-to-one with the solder resist opening structures 130. The area of ​​the orthographic projection of the pad structure 120 on the chip body 110 is at least equal to the area of ​​the orthographic projection of the solder resist opening structure 130 on the chip body 110.

[0022] Compared to solutions where the size of the pad structure 120 is smaller than the size of the solder mask window structure, resulting in solder paste failing to form a firm bond with the exposed chip body 110 during soldering, thus making it prone to crack initiation and propagation under stress, the chip 100 of this application includes a chip body 110 and multiple pad structures 120. Multiple solder mask window structures 130 are provided on the chip body 110, and the multiple pad structures 120 are soldered one-to-one with the solder mask window structures 130. The area of ​​the orthographic projection of the pad structure 120 onto the chip body 110 is greater than or equal to... The area of ​​the solder mask window structure 130 projected onto the chip body 110, that is, the area where the solder pad structure 120 and the solder mask window structure 130 are soldered, is at least equal. Thus, during soldering, the solder pad structure 120 at least covers the solder mask window structure 130, and there is no exposed area between the edge of the solder mask window structure 130 and the edge of the solder pad structure 120. The solder paste fills the soldering area, which enhances the overall mechanical stress resistance of the soldering area and makes it less likely to crack in that area, thereby improving the overall mechanical stability of the chip 100.

[0023] The chip body 110 is a PCB substrate. Figure 2 This is a schematic diagram of the structure of some edge pads provided in an embodiment of this application, as shown below. Figure 2 As shown, combined with Figure 1The plurality of solder mask window structures 130 include a plurality of central solder mask windows 131 and a plurality of edge solder mask windows 132. The plurality of central solder mask windows 131 are disposed in the central region of the chip body 110, and the plurality of edge solder mask windows 132 are disposed around the chip body 110. The plurality of pad structures 120 include a plurality of central pads 121 and a plurality of edge pads 122. The central pads 121 are functional pads used for the telecommunication connection between the chip 100 and the electronic device 10, while the edge pads 122 are non-functional pads, mainly located at the edge of the chip body 110. The edge pads 122 only serve a mechanical fixing function and have no electrical signal connection. However, their soldering failure will directly affect the overall mechanical stability of the chip 100. In thermal cycling or vibration, they will become crack initiation points. Through the crack initiation point, the crack will further expand towards the central region, which will further affect the overall mechanical stability of the chip 100.

[0024] Multiple central pads 121 are correspondingly arranged with multiple central solder mask openings 131, and multiple edge pads 122 are correspondingly soldered with multiple edge solder mask openings 132 to form an edge pad structure 160. The area of ​​the orthogonal projection of the central solder mask opening 131 onto the chip body 110 can be set to be the same as that of the existing chip 100, and larger than the area of ​​the orthogonal projection of the central pads 121 onto the chip body 110; while the area of ​​the orthogonal projection of the edge pads 122 onto the chip body 110 is larger than the area of ​​the orthogonal projection of the central pads 121 onto the chip body 110. The area of ​​the edge solder mask opening 132 projected onto the chip body 110 is such that by increasing the size of the edge pad 122 and decreasing the size of the edge solder mask opening 132, the pad structure 120 completely covers the solder mask opening structure 130. This ensures that the soldering interface between the pad structure 120 and the solder ball is completely located within the solder mask window structure of the solder mask layer, thereby maximizing the interface of the copper foil-solder mask layer-solder ball with the strongest adhesion, completely avoiding direct contact between the solder ball and the low-adhesion material of the PCB substrate, and eliminating the source of crack initiation from the microstructure.

[0025] The edge pad 122 has a size of 18mil to 20mil, and the edge solder mask opening 132 has a size of 16mil to 18mil. This ensures the welding area between the edge solder mask opening 132 and the edge pad 122, thereby enhancing the welding bond. On the other hand, it avoids the edge pad 122 being too large and creating a strong contrast with the center pad 121, which would affect the overall appearance of the chip 100 and ensure the overall visual effect.

[0026] like Figure 2As shown, the chip 100 also includes a protrusion structure 140 whose upper surface protrudes from the chip body 110. The protrusion structure 140 is disposed within the edge solder mask opening 132. The protrusion structure 140 can be a cross-shaped structure, and the width of the protrusion structure 140 is equal to the diameter of the edge solder mask opening 132. In this way, the protrusion structure 140 can increase the contact area of ​​solder paste within the edge solder mask opening 132 during soldering, and the protrusion structure 140 plays a further role in stabilizing the soldering. The protrusion structure 140 can be made of fine copper wire.

[0027] The chip 100 also includes multiple edge traces 150. Adjacent edge pad structures 160 are connected via these edge traces 150. These edge traces 150 are non-signal traces; tiny copper traces are designed to connect the non-functional pads at the four corners, forming a small local network. Although these edge traces 150 do not transmit electrical signals, their mechanical function is crucial. They "bind" the isolated edge pads 122 together, greatly increasing the overall adhesion between the edge pad 122 area and the chip body 110. Simultaneously, they help disperse stress at the corners, reducing stress concentration. Therefore, this application, through adjusting the size of the edge pads 122 and connecting them via edge traces 150, jointly constructs a robust barrier to prevent crack initiation and propagation.

[0028] Figure 3 This is a schematic diagram of the structure of an edge pad structure and an edge trace provided in an embodiment of this application, as shown below. Figure 3 As shown, each pair of adjacent edge pad structures 160 are connected by an edge trace 150 to form a "U" shaped structure, that is, the two edge pads 122 are connected in one direction to form a separate connection network, which will not affect the center pad 121. Figure 4 This is a schematic diagram of another edge pad structure and edge trace matching provided in the embodiments of this application, as shown below. Figure 4 As shown, it is also possible for every two edge pad structures 160 to be cross-connected by an edge trace 150 to form an "X" shape. Of course, other shapes can also be formed by designing the connection, as long as they can enhance adhesion and disperse stress concentration, which is not limited here.

[0029] The multiple edge traces 150 include multiple sub-edge traces 151. Two adjacent edge pad structures 160 are connected by the multiple sub-edge traces 151. The multiple sub-edge traces 151 between two adjacent edge pad structures 160 are arranged to form a connection area. In this way, even if one of the sub-edge traces 151 falls off, the two edge pads 122 can still be connected and fixed by the other sub-edge traces 151, reducing the risk of connection failure at that location.

[0030] like Figure 3 As shown, the width d of the connection area is 3mil-5mil, which will not occupy space and will not affect the arrangement of the connection traces of the center pad 121.

[0031] Of course, it is also possible to use a width of 3mil-5mil for each edge trace 150, so that an edge trace 150 can be directly connected, which is simpler to operate.

[0032] Figure 5 This is a block diagram of the electronic device provided in the embodiments of this application, such as... Figure 5 As shown, this application also discloses an electronic device 10, which employs the chip 100 described above.

[0033] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0034] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A chip, comprising a chip body and a plurality of pad structures, wherein a plurality of solder mask opening structures are arranged on the chip body, the plurality of pad structures are welded in one-to-one correspondence with the solder mask opening structures, characterized in that, the area of the orthographic projection of the pad structure on the chip body is greater than or equal to the area of the orthographic projection of the solder mask opening structure on the chip body.

2. The chip according to claim 1, characterized in that, The plurality of solder mask opening structures comprise a plurality of central solder mask openings and a plurality of edge solder mask openings, the plurality of central solder mask openings are arranged in the central area of the chip body, and the plurality of edge solder mask openings are arranged on the periphery of the chip body; The plurality of pad structures comprise a plurality of central pads and a plurality of edge pads, the plurality of central pads are arranged in one-to-one correspondence with the plurality of central solder mask openings, and the plurality of edge pads are welded in one-to-one correspondence with the plurality of edge solder mask openings to form edge pad structures; wherein the area of the orthographic projection of the central solder mask opening on the chip body is greater than the area of the orthographic projection of the central pad on the chip body; the area of the orthographic projection of the edge pad on the chip body is greater than or equal to the area of the orthographic projection of the edge solder mask opening on the chip body.

3. The chip according to claim 2, characterized in that, The area of the orthographic projection of the edge pad on the chip body is greater than the area of the orthographic projection of the edge solder mask opening on the chip body.

4. The chip according to claim 3, characterized in that, The dimension of the edge pad is 18 mil to 20 mil, and the dimension of the edge solder mask opening is 16 mil to 18 mil.

5. The chip according to claim 3, characterized in that, The chip further comprises a bump structure, and the bump structure is arranged in the edge solder mask opening; wherein the bump structure is a cross-shaped structure.

6. The chip according to claim 3, characterized in that, The chip further comprises a plurality of edge traces, two adjacent edge pad structures are connected through the edge trace, and the edge trace is a non-signal trace.

7. The chip according to claim 6, characterized in that, Every two adjacent edge pad structures are correspondingly connected through one edge trace to form a square-shaped structure; or Every two edge pad structures are cross-connected through one edge trace to form an X-shaped structure.

8. The chip according to claim 7, characterized in that, The width of each edge trace is 3mil-5mil.

9. The chip according to claim 7, characterized in that, The plurality of edge traces comprise a plurality of sub-edge traces, two adjacent edge pad structures are connected through the plurality of sub-edge traces, the plurality of sub-edge traces between two adjacent edge pad structures are arranged to form a connection region, and the width of the connection region is 3mil-5mil.

10. An electronic device, characterized in that, A circuit board component, comprising the chip according to any one of claims 1 to 9.

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