A multi-level stepped chip integrated package structure

Abstract

The utility model discloses a multistage step type chip integrated packaging structure concretely relates to chip packaging technical field, including the substrate, the periphery of substrate is provided with the pin, and the outside of board is provided with the limit slot, the step groove is established in the middle place of substrate, the step groove includes from bottom to top bottom step groove, middle step groove and upper step groove, the chip is pasted in bottom step groove through the glue, and the electrode pad of chip is electrically connected through the lead with pin, this application embeds bottom step groove, middle step groove and upper step groove through the inside embedding of substrate, can install chip embeddedly in the inside of substrate, can effectively reduce the volume after the whole chip packaging, through the cavity ring frame, can wrap the board and the cover plate simultaneously and limit, and then improve the stability after chip packaging, through the sealing groove, sealing plate and the jack, plug rod, can further improve the stability of cover plate on the board.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging, specifically to a multi-level stepped chip integrated packaging structure. Background Technology

[0002] Stepped cavity packaging is a special form of chip packaging. It encapsulates the chip by forming a stepped cavity structure on the substrate. The stepped cavity packaging structure typically includes a bottom plate and several upper plates. The upper plates are arranged circumferentially around the bottom plate, and from top to bottom, the inner sidewalls of the upper plates gradually approach the middle part of the bottom plate to form a step shape. Metal circuits are laid on the bottom plate and upper plates to realize signal transmission. The chip is electrically connected to the substrate solder points through solder points and fixed in the stepped cavity.

[0003] Currently, when chips are packaged using stepped cavity packaging, the top of the chip is directly encapsulated. Although direct encapsulation can dissipate heat and provide insulation, the connection surface between the encapsulator and the substrate is small, making it prone to damage. There is still room for improvement. Utility Model Content

[0004] The purpose of this invention is to provide a multi-level stepped chip integrated packaging structure to address the aforementioned shortcomings in the technology.

[0005] To achieve the above objectives, this utility model provides the following technical solution: a multi-level stepped chip integrated packaging structure, comprising: A substrate, wherein pins are provided around the perimeter of the substrate, and a limiting groove is formed on the outer side of the substrate; A stepped groove is formed in the middle of the substrate, and the stepped groove includes a bottom stepped groove, a middle stepped groove and an upper stepped groove from bottom to top; The chip is glued to the bottom stepped groove, and the electrode pads and pins of the chip are electrically connected by leads. Kovar ring frame, the Kovar ring frame being welded to the outside of the limiting groove; A cover plate, located inside the Kovar ring frame, is a molding compound used to seal the upper side of the chip.

[0006] Preferably, half of the pins are located in the bottom step groove and the other half are located in the middle step groove inside the substrate.

[0007] Preferably, the lead wire is made of aluminum wire.

[0008] Preferably, the lead wire is made of gold wire.

[0009] Preferably, the height of the Kovar ring frame is equal to the sum of the height of the limiting groove and the height of the cover plate.

[0010] Preferably, a sealing groove is provided inside the substrate at the top of the upper step groove, and a sealing plate matching the sealing groove is provided at the bottom of the cover plate.

[0011] Preferably, the top of the substrate is provided with insertion holes near its four corners, and the bottom of the cover plate is provided with insertion rods that match the insertion holes.

[0012] The technical effects and advantages provided by this utility model in the above technical solution are as follows: This application embeds bottom step grooves, middle step grooves and top step grooves inside the substrate, which can embed the chip inside the substrate, effectively reducing the overall size of the chip after packaging. At the same time, due to the reduction in thickness, the heat dissipation effect of the chip is further improved. The Kovar ring frame can simultaneously wrap and limit the substrate and cover plate, thereby improving the stability of the chip after packaging. The sealing groove, sealing plate, and insertion holes and rods can further improve the stability of the cover plate on the substrate. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings.

[0014] Figure 1 This is an appearance drawing of the present utility model; Figure 2 This is a schematic diagram of the limiting groove of this utility model; Figure 3 This is a schematic diagram of the structure of the present invention after the cover plate is removed; Figure 4 This is a schematic diagram showing the chip position of this utility model; Figure 5 This is a schematic diagram of the structure of the chip after it has been removed. Figure 6 This is a schematic diagram of the structure of the cover plate of this utility model.

[0015] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Pin; 3. Kovar ring frame; 4. Cover plate; 5. Limiting groove; 6. Chip; 7. Bottom step groove; 8. Middle step groove; 9. Upper step groove; 10. Sealing groove; 11. Hole; 12. Sealing plate; 13. Insert rod. Detailed Implementation

[0016] To enable those skilled in the art to better understand the technical solution of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings.

[0017] This utility model provides, for example Figures 1-6 The multi-stage stepped chip integrated packaging structure shown includes: The substrate 1 has pins 2 around its perimeter, and a limiting groove 5 is formed on the outer side of the substrate 1. The stepped groove is formed in the middle of the substrate 1. The stepped groove includes a bottom stepped groove 7, a middle stepped groove 8 and an upper stepped groove 9 from bottom to top. Chip 6 is glued to the bottom step groove 7. The electrode pads of chip 6 are electrically connected to pins 2 via leads. The glue used to bond the substrate 1 and chip 6 is a die adhesive. Kovar ring frame 3 is welded to the outside of the limiting groove 5; Cover plate 4 is located inside Kovar ring frame 3. Cover plate 4 is a molding compound that seals the upper side of chip 6.

[0018] Furthermore, the portion of pin 2 inside substrate 1, half of which is located on bottom step groove 7 and the other half of which is located on middle step groove 8.

[0019] Furthermore, aluminum wire is used for the leads.

[0020] Specifically, the lead wire is made of gold.

[0021] Specifically, the height of the Kovar ring frame 3 is equal to the sum of the height of the limiting groove 5 and the height of the cover plate 4.

[0022] Specifically, a sealing groove 10 is provided inside the substrate 1 at the top of the upper step groove 9, and a sealing plate 12 matching the sealing groove 10 is provided at the bottom of the cover plate 4.

[0023] Specifically, the top of the substrate 1 is provided with insertion holes 11 near its four corners, and the bottom of the cover plate 4 is provided with insertion rods 13 that match the insertion holes 11.

[0024] Through the above technical solution: This application embeds a bottom step groove 7, a middle step groove 8, and an upper step groove 9 inside the substrate 1, which can embed the chip 4 inside the substrate 1, effectively reducing the overall size of the packaged chip 4. At the same time, due to the reduced thickness, the heat dissipation effect of the chip 4 is further improved. The Kovar ring 3 can simultaneously wrap and limit the substrate 1 and the cover plate 4, thereby improving the stability of the chip 4 after packaging. The sealing groove 10, sealing plate 12, and insertion hole 11 and insertion rod 13 can further improve the stability of the cover plate 4 on the substrate 1.

[0025] The foregoing description only illustrates certain exemplary embodiments of the present invention. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A multi-stage stepped chip integrated packaging structure, characterized in that, include: The substrate (1) has pins (2) around its perimeter and a limiting groove (5) is formed on the outer side of the substrate (1). The stepped groove is formed in the middle of the substrate (1), and the stepped groove includes a bottom stepped groove (7), a middle stepped groove (8) and an upper stepped groove (9) from bottom to top. Chip (6), the chip (6) is glued to the bottom step groove (7), and the electrode pads of the chip (6) are electrically connected to the pins (2) by leads; Kovar ring frame (3), said Kovar ring frame (3) is welded to the outside of the limiting groove (5); Cover plate (4), which is located inside Kovar ring frame (3), and is a molding compound that seals the upper side of chip (6).

2. The multi-stage stepped chip integrated packaging structure according to claim 1, characterized in that: The portion of the pin (2) inside the substrate (1) is such that half of it is located on the bottom step groove (7) and the other half is located on the middle step groove (8).

3. The multi-stage stepped chip integrated packaging structure according to claim 2, characterized in that: The lead wire is made of aluminum wire.

4. The multi-stage stepped chip integrated packaging structure according to claim 2, characterized in that: The lead wire is made of gold.

5. The multi-stage stepped chip integrated packaging structure according to claim 1, characterized in that: The height of the Kovar ring frame (3) is equal to the sum of the height of the limiting groove (5) and the height of the cover plate (4).

6. The multi-stage stepped chip integrated packaging structure according to claim 1, characterized in that: The substrate (1) has a sealing groove (10) at the top of the upper step groove (9) inside, and the bottom of the cover plate (4) is provided with a sealing plate (12) that matches the sealing groove (10).

7. The multi-stage stepped chip integrated packaging structure according to claim 1, characterized in that: The top of the substrate (1) is provided with insertion holes (11) near its four corners, and the bottom of the cover plate (4) is provided with insertion rods (13) that match the insertion holes (11).

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