A semiconductor component, semiconductor structure and electronic device

Abstract

This application discloses a semiconductor component, a semiconductor structure, and an electronic device. The semiconductor component includes bonded first and second semiconductor structures. The first semiconductor structure includes a first wafer, a first electrical connection portion, a first dielectric layer, and a first conductive pillar. Each first electrical connection portion is correspondingly connected to at least one first conductive pillar. The first conductive pillar penetrates the first dielectric layer, and its surface facing away from the first wafer is flush with the surface of the first dielectric layer. The second semiconductor structure includes a second wafer, a second dielectric layer, a second conductive pillar, and bonding pads. Each second electrical connection portion is connected to a bonding pad through a second conductive pillar. The surface of each bonding pad facing away from the second wafer is flush with the surface of the second dielectric layer. Each first conductive pillar is correspondingly bonded to a bonding pad, and the orthographic projection of each first conductive pillar onto the surface of the corresponding bonding pad facing away from the second wafer falls into the corresponding bonding pad, and the projected area is smaller than the area of ​​the surface of the corresponding bonding pad facing away from the second wafer.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor component, semiconductor structure and electronic device. Background Technology

[0002] With the continuous advancement of semiconductor manufacturing processes, traditional two-dimensional chip scaling methods are beginning to encounter physical limits, such as the reduction in transistor size and the increase in the resistance and capacitance of interconnects, leading to a slowdown in the miniaturization progress of Moore's Law. Meanwhile, power consumption and heat dissipation have become key factors restricting further improvements in chip performance. Traditional two-dimensional packaging methods are insufficient to meet the demands of high-density, high-performance chips.

[0003] To maintain the growth trend in computing performance and storage density, the industry has begun to explore new technological paths. 3D integrated circuit (3D IC) design and packaging technology has emerged, achieving higher integration and faster data transmission speeds by vertically stacking chips or wafers with different functions.

[0004] Hybrid bonding technology emerged in this context. Also known as direct bond interconnect (DBI), it is an innovative technology that has emerged in the semiconductor packaging field in recent years. It combines dielectric-to-dielectric bonding and metal-to-metal bonding, using direct copper-to-copper (Cu-Cu) connections to replace traditional bump or solder ball interconnects, achieving high-density, high-performance interconnects between chips.

[0005] Hybrid bonding technology offers numerous advantages, such as higher integration, faster data transfer speeds, lower power consumption, and higher reliability. However, in related technologies, the copper-to-copper pad interconnection method used in hybrid bonding suffers from varying degrees of misalignment between copper pads in different areas due to alignment errors during bonding, leading to differences in contact resistance. Furthermore, these varying pad offsets result in different bonding areas between dielectric layers, causing inconsistent bond strength and reduced bonding consistency. This ultimately impacts bonding yield. Utility Model Content

[0006] This application discloses a semiconductor component, the semiconductor component comprising: A first semiconductor structure includes a first wafer, a plurality of first electrical connections, a first dielectric layer, and a plurality of first conductive pillars; wherein, the first wafer has a front side; the plurality of first electrical connections are spaced apart on the front side of the first wafer for electrically leading out the first wafer; the first dielectric layer is disposed on the front side of the first wafer and covers the plurality of first electrical connections; each first electrical connection is correspondingly connected to at least one first conductive pillar; each first conductive pillar penetrates the first dielectric layer, and the surface of each first conductive pillar facing away from the first wafer is flush with the surface of the first dielectric layer facing away from the first wafer; A second semiconductor structure includes a second wafer, a plurality of second electrical connections, a second dielectric layer, a plurality of second conductive pillars, and bonding pads; wherein, the second wafer has a front side, and the plurality of second electrical connections are spaced apart on the front side of the second wafer for electrical lead-out of the second wafer; the second dielectric layer is disposed on the front side of the second wafer and covers the plurality of second electrical connections; each second electrical connection corresponds to a bonding pad and is connected through a corresponding second conductive pillar; the surface of each bonding pad facing away from the second wafer is flush with the surface of the second dielectric layer facing away from the second wafer; In the first semiconductor structure, the front side of the first wafer is bonded to the front side of the second wafer in the second semiconductor structure; wherein, each first electrical connection is connected to a first conductive post and is correspondingly bonded to a bonding pad, and the orthographic projection of each first conductive post on the surface of the corresponding bonding pad away from the second wafer falls into the corresponding bonding pad, and the projected area is smaller than the area of ​​the surface of the corresponding bonding pad away from the second wafer.

[0007] In some embodiments, the orthographic projection of each of the first conductive pillars on the front side of the first wafer is located within the orthographic projection range of the corresponding first electrical connection portion on the front side of the first wafer, and the projected area of ​​the first conductive pillar is smaller than the projected area of ​​the first electrical connection portion.

[0008] In some embodiments, the distance between the sidewall of each first conductive post and the side edge of the connected first electrical connection is greater than or equal to 300 nm.

[0009] In some embodiments, each of the first electrical connection portions is connected to a corresponding first conductive post; or... Each of the first electrical connection portions is connected to two corresponding first conductive posts.

[0010] In some embodiments, the first conductive post extends from the front side of the first wafer toward the front side away from the first wafer, and the cross-sectional dimensions of the first conductive post perpendicular to the extension direction of the first conductive post are the same.

[0011] In some embodiments, the orthographic projection of each second conductive post on the front side of the second wafer is located within the orthographic projection range of the corresponding bonding pad on the front side of the second wafer, and the projected area of ​​each second conductive post is smaller than the projected area of ​​the corresponding bonding pad. The orthographic projection of each of the second conductive pillars on the front side of the second wafer is located within the orthographic projection range of the corresponding second electrical connection portion on the front side of the second wafer, and the projected area of ​​each of the second conductive pillars is smaller than the projected area of ​​the corresponding second electrical connection portion.

[0012] In some embodiments, the first wafer has a plurality of first through holes, and each first conductive post fills one of the first through holes; The second wafer has multiple second through holes, and each second conductive post fills one of the second through holes.

[0013] In some embodiments, both the first conductive post and the second conductive post are copper posts; The bonding pads are copper pads.

[0014] This application also discloses a semiconductor structure comprising: The first wafer has a front side; Multiple first electrical connection portions are spaced apart on the front side of the first wafer for electrically leading out the first wafer; A first dielectric layer is disposed on the front side of the first wafer and covers a plurality of the first electrical connection portions; A plurality of first conductive pillars are provided, and each first electrical connection is connected to at least one first conductive pillar. Each first conductive pillar penetrates the first dielectric layer, and the surface of each first conductive pillar facing away from the first wafer is flush with the surface of the first dielectric layer facing away from the first wafer. The orthographic projection of each first conductive pillar on the front side of the first wafer is located within the orthographic projection range of the corresponding first electrical connection on the front side of the first wafer, and the projected area of ​​the first conductive pillar is smaller than the projected area of ​​the first electrical connection.

[0015] In some embodiments, the distance between the sidewall of each first conductive post and the side edge of the connected first electrical connection is greater than or equal to 300 nm.

[0016] Embodiments of this disclosure also provide an electronic device that includes the semiconductor components described above or includes the semiconductor structure described above.

[0017] Compared with related technologies, the semiconductor components and semiconductor structures provided in this application, in the first semiconductor structure and the second semiconductor structure bonded together, the structure used for conductive bonding in the first semiconductor structure adopts a first conductive post with a size smaller than the first electrical connection portion and smaller than the bonding pad. The first conductive post is bonded to the bonding pad of the second semiconductor structure. Compared with bonding between two bonding pads, this is beneficial to reduce the contact resistance difference caused by the large offset between the bonding pads, and to reduce the problem of different bonding strength loss between the first dielectric layer and the second dielectric layer, thus ensuring the yield of electrical bonding between the first semiconductor structure and the second semiconductor structure.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0020] Figure 1 This is a cross-sectional view of a partial structure of a semiconductor component according to an embodiment of this application.

[0021] Figure 2 This is a cross-sectional view of a portion of the structure of a first semiconductor structure according to an embodiment of this application.

[0022] Figure 3 This is a cross-sectional view of a portion of the structure of a first semiconductor structure according to an embodiment of this application.

[0023] Figure 4 This is a cross-sectional view of a partial structure of another semiconductor component according to an embodiment of this application.

[0024] Figure 5 This is a cross-sectional view of a partial structure of another first semiconductor structure in one embodiment of this application. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0026] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance. Connections in this application can refer to mechanical connections, electrical connections, or signal connections, etc.

[0027] This application discloses a semiconductor component, a semiconductor structure, and an electronic device. The semiconductor component includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first wafer, a plurality of first electrical connections, a first dielectric layer, and a plurality of first conductive pillars; wherein, the first wafer has a front side; the plurality of first electrical connections are spaced apart on the front side of the first wafer for electrically leading out the first wafer; the first dielectric layer is disposed on the front side of the first wafer and covers the plurality of first electrical connections; each first electrical connection is correspondingly connected to at least one first conductive pillar; each first conductive pillar penetrates the first dielectric layer, and the surface of each first conductive pillar facing away from the first wafer is flush with the surface of the first dielectric layer facing away from the first wafer. The second semiconductor structure includes a second wafer, a plurality of second electrical connections, a second dielectric layer, a plurality of second conductive pillars, and bonding pads; wherein, the second wafer has a front side, and the plurality of second electrical connections are spaced apart on the front side of the second wafer for electrical lead-out of the second wafer; the second dielectric layer is disposed on the front side of the second wafer and covers the plurality of second electrical connections; each second electrical connection corresponds to a bonding pad and is connected through a corresponding second conductive pillar; the surface of each bonding pad facing away from the second wafer is flush with the surface of the second dielectric layer facing away from the second wafer; In the first semiconductor structure, the front side of the first wafer is bonded to the front side of the second wafer in the second semiconductor structure; wherein, each first electrical connection is connected to a first conductive post and is correspondingly bonded to a bonding pad, and the orthographic projection of each first conductive post on the surface of the corresponding bonding pad away from the second wafer falls into the corresponding bonding pad, and the projected area is smaller than the area of ​​the surface of the corresponding bonding pad away from the second wafer.

[0028] In the aforementioned semiconductor component, in the first semiconductor structure and the second semiconductor structure that are bonded together, the structure used for conductive bonding in the first semiconductor structure adopts a first conductive post with a size smaller than the first electrical connection portion and smaller than the bonding pad. The first conductive post is bonded to the bonding pad of the second semiconductor structure. Compared with bonding between two bonding pads, this helps to reduce the contact resistance difference caused by the large offset between the bonding pads, and also reduces the problem of different bonding strength loss between the first dielectric layer and the second dielectric layer, thus ensuring the yield of electrical bonding between the first semiconductor structure and the second semiconductor structure.

[0029] The following is in conjunction with the appendix Figures 1 to 5 The semiconductor components and structures described above are described in detail. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0030] Please refer to Figure 1 and combine when necessary Figures 2 to 5 As shown, this application provides a semiconductor component 100, which includes a first semiconductor structure 1 and a second semiconductor structure 2.

[0031] The first semiconductor structure 1 includes a first wafer 10, a plurality of first electrical connection portions 20, a first dielectric layer 40, and a plurality of first conductive pillars 30.

[0032] The first wafer 10 has a front side S1 and a back side S2. The front side S1 of the first wafer 10 has solder pads that can be electrically led out.

[0033] A plurality of first electrical connection portions 20 are spaced apart on the front side S1 of the first wafer 10 for electrical lead-out of the first wafer 10. It should be noted that the first electrical connection portion 20 can be a conductive metal structure for electrical lead-out formed on the bonding pads on the front side S1 of the first wafer 10 using semiconductor processes. In some other embodiments, the first electrical connection portion 20 can also be a bonding pad protruding from the front side of the first wafer 10. The first electrical connection portion 20 can be formed of copper or other conductive metals.

[0034] The first dielectric layer 40 is disposed on the front side S1 of the first wafer 10 and covers a plurality of the first electrical connection portions 20. Each first electrical connection portion 20 is correspondingly connected to at least one first conductive post 30; each first conductive post 30 penetrates the first dielectric layer 40, and the surface 301 of each first conductive post 30 facing away from the first wafer 10 is flush with the surface 401 of the first dielectric layer 40 facing away from the first wafer 10. That is, the surface 301 of each first conductive post 30 facing away from the first wafer 10 and the surface 401 of the first dielectric layer 40 facing away from the first wafer 10 are in the same plane.

[0035] The second semiconductor structure 2 includes a second wafer 80, a plurality of second electrical connections 90, a second dielectric layer 50, a plurality of second conductive pillars 70, and bonding pads 60.

[0036] The second wafer 80 has a front side S3 and a back side S4.

[0037] A plurality of second electrical connection portions 90 are spaced apart on the front side S3 of the second wafer 80 for electrically leading out the second wafer 80.

[0038] A plurality of second electrical connection portions 90 are spaced apart on the front side S3 of the second wafer 80 for electrical lead-out of the second wafer 80. It should be noted that the second electrical connection portion 90 can be a conductive metal structure for electrical lead-out provided on the bonding pad on the front side S3 of the second wafer 80 using semiconductor technology. In some other embodiments, the second electrical connection portion 90 can also be a bonding pad protruding from the front side of the second wafer 80. The second electrical connection portion 90 can be formed of copper or other conductive metals.

[0039] The second dielectric layer 50 is disposed on the front side S3 of the second wafer 80 and covers a plurality of second electrical connection portions 90. Each second electrical connection portion 90 corresponds to a bonding pad 60 and is connected through a corresponding second conductive post 70; the surface 601 of each bonding pad 60 facing away from the second wafer 80 is flush with the surface 501 of the second dielectric layer 50 facing away from the second wafer 80. That is, the surface 601 of each bonding pad 60 facing away from the second wafer 80 and the surface 501 of the second dielectric layer 50 facing away from the second wafer 80 are located in the same plane.

[0040] In the first semiconductor structure 1, the side of the first wafer 10 with front surface S1 is bonded to the side of the second wafer 80 with front surface S3 in the second semiconductor structure 2; wherein, each first electrical connection 20 is connected to a first conductive post 30 and is bonded to a bonding pad 60, and the orthographic projection of each first conductive post 30 on the surface of the corresponding bonding pad 60 facing away from the second wafer 80 falls into the corresponding bonding pad 60, and the projected area is smaller than the area of ​​the surface of the corresponding bonding pad 60 facing away from the second wafer 80.

[0041] It should be noted that the first semiconductor structure 1 and the second semiconductor structure 2 can be aligned using alignment marks during bonding. The alignment surfaces of the first semiconductor structure 1 and the second semiconductor structure 2 can be located in or near the central region.

[0042] In some embodiments, the orthographic projection of each of the first conductive pillars 30 onto the front surface S1 of the first wafer 10 is located within the orthographic projection range of the corresponding first electrical connection portion 20 onto the front surface S1 of the first wafer 10, and the projected area of ​​the first conductive pillar 30 is smaller than the projected area of ​​the first electrical connection portion 20.

[0043] In some embodiments, the distance d between the sidewall 3001 of each first conductive post 30 and the side edge 2001 of the connected first electrical connection portion 20 is greater than or equal to 300 nm, so as to ensure that the first conductive post 30 can also bond with the corresponding bonding pad 60 when there is an alignment deviation.

[0044] Combination Figures 2 to 3 As shown, in some embodiments, in the first semiconductor structure 1 of the semiconductor component 100, each of the first electrical connection portions 20 is connected to a corresponding first conductive post 30.

[0045] Combination Figure 4 and Figure 5 As shown, in some other embodiments, in the first semiconductor structure 1' of the semiconductor component 200, each of the first electrical connection portions 20 is connected to two corresponding first conductive pillars 30.

[0046] It is understood that, in some other embodiments, each first electrical connection 20 may also be connected to three or more first conductive posts 30, provided that the process conditions permit.

[0047] In some embodiments, the first conductive post 30 extends from the front side S1 near the first wafer 10 toward the front side S2 away from the first wafer 10, and the cross-sectional dimensions of the first conductive post 30 perpendicular to the extension direction of the first conductive post 30 are the same. That is, the first conductive post 30 can be a columnar conductive structure with a uniform thickness in the extension direction.

[0048] In some embodiments, the orthographic projection of each of the second conductive pillars 70 onto the front surface S3 of the second wafer 80 is located within the orthographic projection range of the corresponding bonding pad 60 onto the front surface S3 of the second wafer 80, and the projected area of ​​each of the second conductive pillars 70 is smaller than the projected area of ​​the corresponding bonding pad 60.

[0049] The orthographic projection of each of the second conductive pillars 70 onto the front surface S3 of the second wafer 80 is located within the orthographic projection range of the corresponding second electrical connection portion 90 onto the front surface S3 of the second wafer 80, and the projected area of ​​each of the second conductive pillars 70 is smaller than the projected area of ​​the corresponding second electrical connection portion 90.

[0050] In some embodiments, the first wafer 10 has a plurality of first through holes 4001, and each first conductive post 30 is filled in one of the first through holes 4001.

[0051] The second wafer 80 has a plurality of second through holes 701, and each second conductive post 70 is filled in one of the second through holes 701.

[0052] Both the first conductive pillar 30 and the second conductive pillar 70 are copper pillars. The first conductive pillar 30 can be formed in the first through-hole 4001 within the first dielectric layer 40 using a damascus electroplating process. The second conductive pillar 70 can be formed in the second through-hole 701 within the second dielectric layer 50 using a damascus electroplating process.

[0053] The bonding pad 60 is a copper pad.

[0054] It is understood that, in some embodiments, both the first wafer 10 and the second wafer 80 include a chip unit. The chip unit included in the first wafer 10 may include multiple first conductive pillars 30, and the chip unit included in the second wafer 80 may include multiple bonding pads. The semiconductor assembly formed after bonding is a stacked chip including a chip unit from the first wafer 10 and a chip unit from the second wafer. This stacked chip may be a processor chip, or a memory chip, sensor chip, or other chip. In other embodiments, the first wafer and the second wafer may each include multiple chip units. Each chip unit of the first wafer may include multiple first conductive pillars 30, and each chip unit of the second wafer may include multiple bonding pads. The semiconductor assembly formed after bonding is an assembly including multiple stacked chip units, which can be diced to form multiple bonded stacked chips. This stacked chip may be a processor chip, or a memory chip, sensor chip, or other chip. Each stacked chip may include a chip unit from the first wafer and a corresponding chip unit from the second wafer.

[0055] Please refer to Figure 2 As shown, this application also provides a semiconductor structure 1 and a semiconductor structure 1'. Both semiconductor structure 1 and semiconductor structure 1' include a first wafer 10, a plurality of first electrical connection portions 20, a first dielectric layer 40, and a plurality of first conductive pillars 30.

[0056] The first wafer 10 has a front side S1.

[0057] The first wafer 10 may have one chip unit or multiple chip units.

[0058] Multiple first electrical connection portions 20 are spaced apart on the front side S1 of the first wafer 10 for electrically leading out the first wafer 10.

[0059] The first dielectric layer 40 is disposed on the front side S1 of the first wafer 10 and covers a plurality of the first electrical connection portions 20.

[0060] Each of the first electrical connection portions 20 is correspondingly connected to at least one first conductive post 30; each of the first conductive posts 30 penetrates the first dielectric layer 40, and the surface of each of the first conductive posts 30 facing away from the first wafer 10 is flush with the surface of the first dielectric layer 40 facing away from the first wafer 10; wherein, the orthographic projection of each of the first conductive posts 30 on the front surface S1 of the first wafer 10 is located within the orthographic projection range of the corresponding first electrical connection portion 20 on the front surface S1 of the first wafer 10, and the projected area of ​​the first conductive post 30 is smaller than the projected area of ​​the first electrical connection portion 20.

[0061] Combination Figure 2 As shown, in some embodiments, the distance d between the sidewall 3001 of each first conductive post 30 and the side edge 2001 of the connected first electrical connection portion 20 is greater than or equal to 300 nm.

[0062] The specific structures of the first semiconductor structure 1 and semiconductor structure 1' can be referred to the above-mentioned descriptions, and will not be repeated here.

[0063] Embodiments of this disclosure also provide an electronic device including the semiconductor component 100 or semiconductor component 200 described above. Alternatively, the electronic device may include the semiconductor structure 1 or semiconductor structure 1' described above.

[0064] In some embodiments, the semiconductor component included in the electronic device may be a stacked chip having a chip unit corresponding to it. In other embodiments, the semiconductor component included in the electronic device may also be multiple stacked chips having multiple chip units corresponding to it.

[0065] The electronic device can be a mobile phone, a tablet, or other electronic product.

[0066] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0067] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A semiconductor component, characterized in that, The semiconductor component includes: A first semiconductor structure includes a first wafer, a plurality of first electrical connections, a first dielectric layer, and a plurality of first conductive pillars; wherein, the first wafer has a front side; the plurality of first electrical connections are spaced apart on the front side of the first wafer for electrically leading out the first wafer; the first dielectric layer is disposed on the front side of the first wafer and covers the plurality of first electrical connections; each first electrical connection is correspondingly connected to at least one first conductive pillar; each first conductive pillar penetrates the first dielectric layer, and the surface of each first conductive pillar facing away from the first wafer is flush with the surface of the first dielectric layer facing away from the first wafer; A second semiconductor structure includes a second wafer, a plurality of second electrical connections, a second dielectric layer, a plurality of second conductive pillars, and bonding pads; wherein, the second wafer has a front side, and the plurality of second electrical connections are spaced apart on the front side of the second wafer for electrical lead-out of the second wafer; the second dielectric layer is disposed on the front side of the second wafer and covers the plurality of second electrical connections; each second electrical connection corresponds to a bonding pad and is connected through a corresponding second conductive pillar; the surface of each bonding pad facing away from the second wafer is flush with the surface of the second dielectric layer facing away from the second wafer; In the first semiconductor structure, the front side of the first wafer is bonded to the front side of the second wafer in the second semiconductor structure; wherein, each first electrical connection is connected to a first conductive post and is correspondingly bonded to a bonding pad, and the orthographic projection of each first conductive post on the surface of the corresponding bonding pad away from the second wafer falls into the corresponding bonding pad, and the projected area is smaller than the area of ​​the surface of the corresponding bonding pad away from the second wafer.

2. The semiconductor component according to claim 1, characterized in that, The orthographic projection of each of the first conductive pillars on the front side of the first wafer is located within the orthographic projection range of the corresponding first electrical connection portion on the front side of the first wafer, and the projected area of ​​the first conductive pillar is smaller than the projected area of ​​the first electrical connection portion.

3. The semiconductor component according to claim 2, characterized in that, The distance between the sidewall of each first conductive post and the side edge of the first electrical connection to which it is connected is greater than or equal to 300 nm.

4. The semiconductor component according to claim 1, characterized in that, Each of the first electrical connection portions is connected to a corresponding first conductive post; or... Each of the first electrical connection portions is connected to two corresponding first conductive posts.

5. The semiconductor component according to claim 1, characterized in that, The first conductive post extends from the front side of the first wafer toward the front side away from the first wafer, and the cross-sectional dimensions of the first conductive post perpendicular to the extension direction of the first conductive post are the same.

6. The semiconductor component according to claim 1, characterized in that, The orthographic projection of each of the second conductive pillars on the front side of the second wafer is located within the orthographic projection range of the corresponding bonding pad on the front side of the second wafer, and the projected area of ​​each of the second conductive pillars is smaller than the projected area of ​​the corresponding bonding pad. The orthographic projection of each of the second conductive pillars on the front side of the second wafer is located within the orthographic projection range of the corresponding second electrical connection portion on the front side of the second wafer, and the projected area of ​​each of the second conductive pillars is smaller than the projected area of ​​the corresponding second electrical connection portion.

7. The semiconductor component according to claim 1, characterized in that, The first wafer has a plurality of first through holes, and each first conductive post is filled in one of the first through holes; The second wafer has multiple second through holes, and each second conductive post fills one of the second through holes.

8. The semiconductor component according to claim 1, characterized in that, Both the first conductive pillar and the second conductive pillar are copper pillars; The bonding pads are copper pads.

9. A semiconductor structure, characterized in that, include: The first wafer has a front side; Multiple first electrical connection portions are spaced apart on the front side of the first wafer for electrically leading out the first wafer; A first dielectric layer is disposed on the front side of the first wafer and covers a plurality of the first electrical connection portions; A plurality of first conductive pillars are provided, and each first electrical connection is connected to at least one first conductive pillar. Each first conductive pillar penetrates the first dielectric layer, and the surface of each first conductive pillar facing away from the first wafer is flush with the surface of the first dielectric layer facing away from the first wafer. The orthographic projection of each first conductive pillar on the front side of the first wafer is located within the orthographic projection range of the corresponding first electrical connection on the front side of the first wafer, and the projected area of ​​the first conductive pillar is smaller than the projected area of ​​the first electrical connection.

10. The semiconductor structure according to claim 9, characterized in that, The distance between the sidewall of each first conductive post and the side edge of the first electrical connection to which it is connected is greater than or equal to 300 nm.

11. An electronic device, characterized in that, It includes the semiconductor component as described in any one of claims 1-8 or the semiconductor structure as described in claim 9 or 10.

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