A receiving device for a track circuit

Abstract

The utility model discloses a receiving device of track circuit, and the receiving device includes: multiple sets of processing module, for each group processing module, processing module is constituted by processing chip, communication chip and conversion chip combination, and the first input of conversion chip is used for receiving track circuit signal, and the output of conversion chip is connected with the first input of processing chip, the second input of processing chip is connected with the first output of communication chip, and the first output of processing chip is connected with the first input of communication chip, and the second output of communication chip is connected with host computer through communication channel, wherein, through host computer, the decoding result of each group processing module transmission is compared, when consistent, any one decoding result is fed back to train control system. Thus through multiple sets of processing module independent decoding track circuit signal, ensure when decoding result is consistent, only then report decoding result, and effectively solve the problem that decoding is not accurate enough.

Description

Technical Field

[0001] This utility model relates to the field of rail transit technology, and in particular to a receiving device for a rail circuit. Background Technology

[0002] Track circuits are an important safety detection method in railway signaling systems, used to monitor the running status of trains on the tracks. Track circuits transmit specific electrical signals, which, through track circuit receiving devices, detect information such as whether a train has passed and whether the track is clear, thereby ensuring the safe operation of trains.

[0003] In existing technologies, the working principle of track circuit receiving devices is based on detecting current or voltage signals in track circuits, then analyzing these signals to output the analyzed signals for train information transmission.

[0004] However, when acquiring signals, the signals are easily affected by changes in the electrical state of the track circuit when the train passes by. This may cause errors in the subsequent demodulation and decoding process of the receiving device due to these effects. Especially when the track environment is more complex, the probability of misinterpretation increases, which in turn affects the reliability of the train control system, which is the system that ensures the safe and fast operation of the train. Utility Model Content

[0005] In view of the shortcomings of the prior art, the present invention provides a receiving device for track circuits to solve the problem of inaccurate decoding caused by the prior art.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] The first aspect of this utility model provides a receiving device for a track circuit, the receiving device comprising: multiple processing modules;

[0008] Each processing module consists of a combination of a processing chip, a communication chip, and a conversion chip.

[0009] The first input terminal of the conversion chip is used to receive track circuit signals, and the output terminal of the conversion chip is connected to the first input terminal of the processing chip. The conversion chip is used to convert the analog signal of the track circuit signal into a digital signal to obtain the target signal.

[0010] The second input terminal of the processing chip is connected to the first output terminal of the communication chip, and the first output terminal of the processing chip is connected to the first input terminal of the communication chip. The processing chip is used to decode the target signal to obtain a decoding result.

[0011] The second output terminal of the communication chip is connected to the host computer through a communication channel;

[0012] The host computer compares the decoding results sent by each group of processing modules. When all the decoding results are consistent, any one of the decoding results is fed back to the train control system.

[0013] Optionally, in the above-described receiving device for the track circuit, the receiving device further includes: a transformer;

[0014] The input terminal of the transformer is used to receive track circuit signals, and the output terminal of the transformer is connected to the first input terminal of the conversion chip in each group of processing modules.

[0015] Optionally, in the above-described receiving device for the track circuit, the processing module further includes a signal conditioning module;

[0016] The input terminal of the signal conditioning module is connected to the output terminal of the transformer, and the output terminal of the signal conditioning module is connected to the first input terminal of the conversion chip.

[0017] Optionally, in the above-described receiving device for the track circuit, the processing module further includes a storage chip;

[0018] The input terminal of the memory chip is connected to the second output terminal of the processing chip, and the output terminal of the memory chip is connected to the third input terminal of the processing chip.

[0019] Optionally, in the above-described receiving device for the track circuit, the processing module further includes a power supply chip;

[0020] The output terminal of the power chip is connected to the fourth input terminal of the processing chip, the second input terminal of the communication chip, and the second input terminal of the conversion chip.

[0021] Optionally, in the above-described receiving device for the track circuit, the receiving device further includes an optical coupler;

[0022] Each group of processing modules is connected to the other group via the optocoupler.

[0023] Optionally, in the above-mentioned receiving device for the track circuit, the number of optical couplers is 3;

[0024] The input terminal of the first optocoupler is connected to the third output terminal of the processing chip in each group of processing modules, and the output terminal of the first optocoupler is connected to the fifth input terminal of the processing chip in each group of processing modules.

[0025] The input terminal of the second optocoupler is connected to the fourth output terminal of the processing chip in each group of processing modules, the first output terminal of the second optocoupler is connected to the sixth input terminal of the processing chip in each group of processing modules, and the second output terminal of the second optocoupler is connected to the third input terminal of the communication chip in the target processing module; wherein, the target processing module refers to the processing module other than the first group of processing modules; the first group of processing modules refers to the processing module whose output terminal of the second optocoupler is not connected to the input terminal of the communication chip;

[0026] The input terminal of the third optocoupler is connected to the third output terminal of the communication chip in each group of the processing modules, and the output terminal of the third optocoupler is connected to the fourth input terminal of the communication chip in each group of the processing modules.

[0027] Optionally, in the receiving device of the above-mentioned track circuit, the processing chip is model AVP32F335BA176S.

[0028] Optionally, in the receiving device of the above-mentioned track circuit, the communication chip is model EG4X20BG256I8.

[0029] Optionally, in the receiving device of the above-mentioned track circuit, the conversion chip is model SGM51622HXTS16G / TR.

[0030] This utility model provides a track circuit receiving device, comprising multiple processing modules. Each processing module consists of a processing chip, a communication chip, and a conversion chip. The first input terminal of the conversion chip receives track circuit signals, and its output terminal is connected to the first input terminal of the processing chip. The conversion chip converts the analog track circuit signals into digital signals to obtain the target signal. The second input terminal of the processing chip is connected to the first output terminal of the communication chip, and the first output terminal of the processing chip is connected to the first input terminal of the communication chip. The processing chip decodes the target signal to obtain the decoding result. The second output terminal of the communication chip is connected to a host computer via a communication channel. The host computer compares the decoding results sent by each processing module. When all decoding results are consistent, any one decoding result is fed back to the train control system. Thus, by having multiple processing modules independently decode the track circuit signals, ensuring that the decoding result is reported only when they are consistent, the problem of inaccurate decoding is effectively solved, and the safety level of the railway signaling system can be effectively improved. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0032] Figure 1 A first structural schematic diagram of a receiving device for a track circuit provided in an embodiment of this utility model;

[0033] Figure 2 A second structural schematic diagram of a receiving device for a track circuit provided in an embodiment of this utility model;

[0034] Figure 3 A third structural schematic diagram of a receiving device for a track circuit provided in an embodiment of this utility model;

[0035] Figure 4 A fourth structural schematic diagram of a receiving device for a track circuit provided in an embodiment of this utility model;

[0036] Figure 5 This is a fifth structural schematic diagram of a receiving device for a track circuit provided in an embodiment of the present utility model. Detailed Implementation

[0037] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0038] In this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0039] As the background technology shows, existing track circuit receiving devices operate by detecting current or voltage signals in the track circuit, analyzing these signals, and finally outputting decoded signals for information transmission by the train system. However, during signal acquisition, the electrical state of the track circuit changes when a train passes, which may interfere with the signal and affect the normal operation of the receiving device. In the subsequent demodulation and decoding processes, this interference may lead to errors, especially in complex track environments, where the probability of misinterpretation increases, thus affecting the reliability of the train control system.

[0040] Therefore, this utility model embodiment provides a receiving device for a track circuit. The receiving device includes multiple processing modules, each of which is composed of a processing chip, a communication chip, and a conversion chip. Thus, there are multiple independent processing modules that simultaneously decode the track circuit signal. Only when the decoding results are consistent will the decoding result be reported, effectively solving the problem of inaccurate decoding.

[0041] Therefore see Figure 1 The diagram shows a first structural schematic of a receiving device for a track circuit according to an embodiment of the present invention. The receiving device includes multiple processing modules 1.

[0042] For each processing module 1, the processing module 1 is composed of a processing chip 3, a communication chip 4 and a conversion chip 2.

[0043] The first input terminal of the conversion chip 2 is used to receive track circuit signals, and the output terminal of the conversion chip 2 is connected to the first input terminal of the processing chip 3.

[0044] In some embodiments, the conversion chip 2 is an AD chip, specifically an SGM51622HXTS16G / TR chip from a domestic company. The conversion chip 2 (AD chip) is used to convert the analog signal of the track circuit signal into a digital signal to obtain the target signal, thereby providing basic data for subsequent digital signal processing. Furthermore, the high performance of the AD chip ensures the accuracy and reliability of signal acquisition.

[0045] In some embodiments, the conversion chip 2 (AD chip) can also be connected to the communication chip 4 via an SPI interface or an I2C interface, thereby transmitting the data acquired by the AD chip to the communication chip 4 for further processing. For example, the communication chip 4 can perform noise reduction, verification, and correction operations.

[0046] Optionally, the sampling rate and resolution of the conversion chip 2 can be adjusted according to actual needs to meet the signal acquisition requirements in different scenarios.

[0047] The second input terminal of the processing chip 3 is connected to the first output terminal of the communication chip 4, and the first output terminal of the processing chip 3 is connected to the first input terminal of the communication chip 4. The processing chip 3 is used to decode the target signal and obtain the decoding result.

[0048] Specifically, by combining the processing chip 3 and the communication chip 4, data processing can be made both efficient and flexible, and can respond quickly to changes in track circuit signals.

[0049] In some embodiments, the processing chip 3 is a DSP chip, wherein the DSP chip is an AVP32F335BA176S from a domestic company and serves as the main processor.

[0050] Optionally, the DSP chip can communicate with the communication chip 4 via an SPI interface or an I2C interface, and can receive sampled data from the communication chip 4, and process and decode the sampled data.

[0051] The second output terminal of communication chip 4 is connected to the host computer through a communication channel.

[0052] In some embodiments, the communication chip 4 is an FPGA chip, wherein the FPGA chip is connected to the AD chip through an SPI interface or an I2C interface to acquire digital data of analog signals from the AD chip.

[0053] In some embodiments, the communication chip 4 (FPGA chip), specifically the EG4X20BG256I8 from a domestic company, is responsible for the processing and control of the peripheral device interface.

[0054] Communication chip 4 also implements dual-port RAM (DPRAM) functionality for efficient data exchange with the DSP chip. Communication chip 4 can also communicate with other modules, such as display modules and communication modules, via parallel or serial interfaces.

[0055] In some embodiments, the communication channel is an MS9E channel, thereby enabling the communication chip 4 to communicate with external modules via the MS9E channel.

[0056] The system compares the decoding results sent by each processing module 1 through the host computer. When all decoding results are consistent, any one of the decoding results is fed back to the train control system.

[0057] It should be noted that, in this embodiment of the utility model, in addition to transmitting the decoding result to the host computer through the communication channel, it can also be transmitted to the host computer or other control systems through the communication interface (such as RS485, CAN, DPRAM, etc.).

[0058] It should also be noted that in this embodiment of the utility model, the receiving device is designed according to the SIL4 security level, and the number of processing modules 1 is 2, using a 2-out-of-2 structure. Therefore, there are two sets of independent hardware and software that decode the track circuit signal at the same time. The result is only reported when the decoding results of the two sets of hardware are consistent, thereby ensuring the high security of the system and the accuracy of decoding.

[0059] Therefore, in this embodiment of the utility model, a receiving device for a fully domestically produced chip track circuit is realized through multiple processing modules, which also ensures the high reliability, high safety and complete autonomous controllability of the train control system. The receiving device can also effectively improve the safety level of the railway signaling system and ensure the accuracy of decoding.

[0060] In some embodiments, combined with Figure 1 See Figure 2 The diagram shows a second structural schematic of a receiving device for a track circuit, which also includes a transformer 5.

[0061] The input terminal of transformer 5 is used to receive track circuit signals, and the output terminal of transformer 5 is connected to the first input terminal of conversion chip 2 in each processing module 1.

[0062] Specifically, since track circuit signals are easily affected by changes in the electrical state of the track circuit when a train passes, a transformer 5 is installed at the beginning of the receiving device. The transformer 5 is used to adjust the voltage and current of the track circuit signals and provide electrical isolation to ensure the stability, efficiency and safety of the receiving device.

[0063] In this embodiment of the invention, a transformer is used to address the impact of changes in the electrical state of the track circuit when a train passes, thereby ensuring the stable operation of the receiving device.

[0064] In some embodiments, combined with Figure 1 and Figure 2 See Figure 3 The diagram shows a third structural schematic of a receiving device for a track circuit, wherein the processing module 1 further includes a signal conditioning module 6.

[0065] The input terminal of the signal conditioning module 6 is connected to the output terminal of the transformer 5, and the output terminal of the signal conditioning module 6 is connected to the first input terminal of the conversion chip 2.

[0066] Specifically, after the signal conditioning module 6 receives the track circuit signal transmitted after being processed by the transformer 5, the signal conditioning module 6 will further process the track circuit signal to make it meet the requirements of the subsequent processing module 1. The signal conditioning module 6 may include signal amplification, signal filtering, signal isolation, linearization, and standardization, etc.

[0067] In this embodiment of the invention, the signal conditioning module ensures that the track circuit signal meets the processing requirements of the processing module in terms of quality and format, thereby improving the accuracy and reliability of the receiving device.

[0068] In some embodiments, combined with Figure 1 , Figure 2 and Figure 3 See Figure 4 The diagram shows a fourth structural schematic of a receiving device for a track circuit, wherein the processing module 1 also includes a memory chip 7.

[0069] The input terminal of the storage chip 7 is connected to the second output terminal of the processing chip 3, and the output terminal of the storage chip 7 is connected to the third input terminal of the processing chip 3.

[0070] Optionally, the memory chip 7 is an SRAM chip, but it can also be other memory chips 7, which can be selected according to the requirements.

[0071] Specifically, the SRAM chip used is the IS61WV25616BLL-10BLI from a domestic company. Other models can also be used, depending on the requirements, but it must meet the requirement of full domestic production. The SRAM chip is used to store intermediate calculation results, that is, to store the results of the decoding of the track circuit signals by the processing chip 3.

[0072] In this embodiment of the invention, the result of decoding by the processing chip can be stored through a storage chip, thereby avoiding the loss of the decoding result.

[0073] In some embodiments, the processing module 1 further includes a power supply chip.

[0074] The output terminal of the power supply chip is connected to the fourth input terminal of the processing chip 3, the second input terminal of the communication chip 4, and the second input terminal of the conversion chip 2.

[0075] Specifically, the power supply chips selected are domestically produced DC / DC converters and LDOs, such as a certain model of DC / DC converter and LDO regulator. The specific model of the power supply chip can be selected according to actual needs, but it must be ensured that it meets the requirement of full domestic production.

[0076] The power supply chip provides stable power support for the AD chip, FPGA chip and DSP chip, ensuring the stable operation of processing module 1 in various working environments.

[0077] It should be noted that after the receiving device is powered on, the power chip starts to supply power to the AD chip, FPGA chip and DSP chip so that the FPGA chip and DSP chip can be initialized and the firmware program can be loaded, and the AD chip can start sampling analog signals.

[0078] In this embodiment of the invention, a power supply chip is used to power the AD chip, FPGA chip, and DSP chip, thereby ensuring the stable operation of these chips.

[0079] In some embodiments, combined with Figure 1 , Figure 2 , Figure 3 as well as Figure 4 See Figure 5 The diagram shows a fifth structural schematic of a receiving device for a track circuit, which also includes an optical coupler.

[0080] Each processing module 1 is connected to the other via an optocoupler.

[0081] Specifically, optocouplers can electrically isolate each group of processing modules 1, preventing high voltage, noise, or electrical interference from being transmitted to other processing modules 1.

[0082] In some embodiments, the number of optical couplers is three, namely a first optical coupler, a second optical coupler, and a third optical coupler.

[0083] Specifically, the input terminal of the first optocoupler 8 is connected to the third output terminal of the processing chip 3 in each processing module 1, and the output terminal of the first optocoupler is connected to the fifth input terminal of the processing chip 3 in each processing module 1.

[0084] The input terminal of the second optocoupler 9 is connected to the fourth output terminal of the processing chip 3 in each processing module 1, the first output terminal of the second optocoupler 9 is connected to the sixth input terminal of the processing chip 3 in each processing module 1, and the second output terminal of the second optocoupler 9 is connected to the third input terminal of the communication chip 4 in the target processing module.

[0085] The target processing module refers to the processing modules other than the first group of processing modules; the first group of processing modules refers to the processing modules whose output terminal of the second optocoupler 9 is not connected to the input terminal of the communication chip 4.

[0086] The input terminal of the third optocoupler 10 is connected to the third output terminal of the communication chip 4 in each processing module 1, and the output terminal of the third optocoupler is connected to the fourth input terminal of the communication chip 4 in each processing module 1.

[0087] It should be noted that the first, second, and third optocouplers can effectively protect the chip in the processing module 1 from damage caused by excessive voltage. Furthermore, this embodiment of the invention combines the processing chip 3 and the communication chip 4 to achieve high-frequency and high-speed signal transmission. However, during transmission, electromagnetic interference may occur. Therefore, the first, second, and third optocouplers can suppress electromagnetic interference (EMI) and other high-frequency noise, thereby preventing interference or distortion of the track circuit signal.

[0088] Therefore, in this embodiment of the invention, by isolating each group of processing modules 1 through optical couplers, the impact of electrical faults on the receiving device can be reduced, thereby improving the stability and reliability of the entire receiving device.

[0089] Optionally, combined Figure 1 , Figure 2 , Figure 3 , Figure 4 as well as Figure 5 The present invention provides a receiving device for a track circuit, comprising: two processing modules 1, a transformer 5, and an optocoupler module. The optocoupler module includes a first optocoupler 8, a second optocoupler 9, and a third optocoupler 10.

[0090] Each processing module 1 consists of a signal conditioning module 6, a processing chip 3, a communication chip 4, a conversion chip 2, and a storage chip 7. Each processing module 1 is connected to the others via an optocoupler module.

[0091] The input terminal of transformer 5 is used to receive track circuit signals, and the output terminal of transformer 5 is connected to the input terminal of signal conditioning module 6.

[0092] The output of the signal conditioning module 6 is connected to the first input of the conversion chip 2.

[0093] The output of the conversion chip 2 is connected to the first input of the processing chip 3.

[0094] The second input terminal of the processing chip 3 is connected to the first output terminal of the communication chip 4, and the first output terminal of the processing chip 3 is connected to the first input terminal of the communication chip 4.

[0095] The input terminal of the storage chip 7 is connected to the second output terminal of the processing chip 3, and the output terminal of the storage chip 7 is connected to the third input terminal of the processing chip 3.

[0096] The output terminal of the power supply chip is connected to the fourth input terminal of the processing chip 3, the second input terminal of the communication chip 4, and the second input terminal of the conversion chip 2.

[0097] The input terminal of the first optocoupler 8 is connected to the third output terminal of the processing chip 3 in the processing module 1, and the output terminal of the first optocoupler 8 is connected to the fifth input terminal of the processing chip 3 in the processing module 1.

[0098] The input terminal of the second optocoupler 9 is connected to the fourth output terminal of the processing chip 3 in the processing module 1, and the output terminal of the second optocoupler 9 is connected to the sixth input terminal of the processing chip 3 in the processing module 1.

[0099] The input terminal of the second optocoupler 9 is connected to the fourth output terminal of the processing chip 3 in each processing module 1, the first output terminal of the second optocoupler 9 is connected to the sixth input terminal of the processing chip 3 in each processing module 1, and the second output terminal of the second optocoupler 9 is connected to the third input terminal of the communication chip 4 in the target processing module.

[0100] The target processing module refers to the processing modules other than the first group of processing modules; the first group of processing modules refers to the processing modules whose output terminal of the second optocoupler 9 is not connected to the input terminal of the communication chip 4.

[0101] The input terminal of the third optocoupler 10 is connected to the third output terminal of the communication chip 4 in the processing module 1, and the output terminal of the third optocoupler 10 is connected to the fourth input terminal of the communication chip 4 in the processing module 1.

[0102] The second output terminal of communication chip 4 is connected to the host computer through a communication channel.

[0103] This utility model provides a track circuit receiving device, comprising multiple processing modules. Each processing module consists of a processing chip, a communication chip, and a conversion chip. The first input terminal of the conversion chip receives track circuit signals, and its output terminal is connected to the first input terminal of the processing chip. The conversion chip converts the analog track circuit signals into digital signals to obtain the target signal. The second input terminal of the processing chip is connected to the first output terminal of the communication chip, and the first output terminal of the processing chip is connected to the first input terminal of the communication chip. The processing chip decodes the target signal to obtain the decoding result. The second output terminal of the communication chip is connected to a host computer via a communication channel. The host computer compares the decoding results sent by each processing module. When all decoding results are consistent, any one decoding result is fed back to the train control system. Thus, by having multiple processing modules independently decode the track circuit signals, ensuring that the decoding result is reported only when they are consistent, the problem of inaccurate decoding is effectively solved, and the safety level of the railway signaling system can be effectively improved.

[0104] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention.

[0105] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A receiving device for a track circuit, characterized in that, The receiving device includes: multiple processing modules; Each processing module consists of a combination of a processing chip, a communication chip, and a conversion chip. The first input terminal of the conversion chip is used to receive track circuit signals, and the output terminal of the conversion chip is connected to the first input terminal of the processing chip. The conversion chip is used to convert the analog signal of the track circuit signal into a digital signal to obtain the target signal. The second input terminal of the processing chip is connected to the first output terminal of the communication chip, and the first output terminal of the processing chip is connected to the first input terminal of the communication chip. The processing chip is used to decode the target signal to obtain a decoding result. The second output terminal of the communication chip is connected to the host computer through a communication channel; The host computer compares the decoding results sent by each group of processing modules. When all the decoding results are consistent, any one of the decoding results is fed back to the train control system.

2. The receiving device according to claim 1, characterized in that, The receiving device further includes: a transformer; The input terminal of the transformer is used to receive track circuit signals, and the output terminal of the transformer is connected to the first input terminal of the conversion chip in each group of processing modules.

3. The receiving device according to claim 2, characterized in that, The processing module also includes a signal conditioning module; The input terminal of the signal conditioning module is connected to the output terminal of the transformer, and the output terminal of the signal conditioning module is connected to the first input terminal of the conversion chip.

4. The receiving device according to claim 1, characterized in that, The processing module also includes a storage chip; The input terminal of the memory chip is connected to the second output terminal of the processing chip, and the output terminal of the memory chip is connected to the third input terminal of the processing chip.

5. The receiving device according to claim 1, characterized in that, The processing module also includes a power chip; The output terminal of the power chip is connected to the fourth input terminal of the processing chip, the second input terminal of the communication chip, and the second input terminal of the conversion chip.

6. The receiving device according to claim 1, characterized in that, The receiving device also includes an optical coupler; Each group of processing modules is connected to the other via the optocoupler.

7. The receiving device according to claim 6, characterized in that, The number of optical couplers is 3; The input terminal of the first optocoupler is connected to the third output terminal of the processing chip in each group of processing modules, and the output terminal of the first optocoupler is connected to the fifth input terminal of the processing chip in each group of processing modules. The input terminal of the second optocoupler is connected to the fourth output terminal of the processing chip in each group of processing modules, the first output terminal of the second optocoupler is connected to the sixth input terminal of the processing chip in each group of processing modules, and the second output terminal of the second optocoupler is connected to the third input terminal of the communication chip in the target processing module; wherein, the target processing module refers to the processing module other than the first group of processing modules; the first group of processing modules refers to the processing module whose output terminal of the second optocoupler is not connected to the input terminal of the communication chip; The input terminal of the third optocoupler is connected to the third output terminal of the communication chip in each group of the processing modules, and the output terminal of the third optocoupler is connected to the fourth input terminal of the communication chip in each group of the processing modules.

8. The receiving device according to claim 1, characterized in that, The processing chip is model AVP32F335BA176S.

9. The receiving device according to claim 1, characterized in that, The communication chip is model EG4X20BG256I8.

10. The receiving device according to claim 1, characterized in that, The conversion chip is model SGM51622HXTS16G / TR.

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