Dicing of a wafer and semiconductor structure

Abstract

The utility model provides a kind of tube core and semiconductor structure.Semiconductor structure includes semiconductor layer.Semiconductor structure includes grating coupler configured on semiconductor layer.Grating coupler includes multiple grating lines.Each grating line extends along the curve conforming to ellipse segment, wherein ellipse is defined by radius R1 and radius R2 less than radius R1.Semiconductor structure further includes waveguide configured on semiconductor layer.Waveguide is adjacent grating coupler along transverse direction.

Description

Technical Field

[0001] This utility model relates to a die and semiconductor structure. Background Technology

[0002] Silicon photonics technology is playing a crucial role in high-speed optical data communication. For example, optical transceiver modules, including high-speed phase modulators, grating couplers, and waveguides, are used in high-speed optical communication systems. These modules conform to various international standard specifications for communication speeds exceeding 100 Gbps. The performance of an optical transceiver module is determined by the coupling efficiency of the grating coupler within it. While existing grating coupler structures for optical transceiver modules are generally sufficient, they are not entirely satisfactory in all aspects. Utility Model Content

[0003] This invention provides a semiconductor structure. The semiconductor structure includes a semiconductor layer. The semiconductor structure includes a grating coupler disposed on the semiconductor layer. The semiconductor structure also includes a waveguide disposed on the semiconductor layer and laterally adjacent to the grating coupler. The grating coupler includes a plurality of grating lines. Each grating line extends along a segment curve conforming to an ellipse, wherein the ellipse is defined by a radius R1 and a radius R2 smaller than radius R1.

[0004] This invention provides a photonic chip. The photonic chip includes a substrate. The photonic chip also includes a device layer disposed on the substrate. The device layer includes a grating coupler and a waveguide adjacent to the grating coupler. The grating coupler includes a plurality of grating lines arranged concentrically in the transverse direction on the device layer. Each grating line extends along a segment of an ellipse, wherein the ellipse is defined by a major radius and a minor radius. The ratio of the major radius to the minor radius is greater than one. Attached Figure Description

[0005] When with attachment Figure 1 Upon reading this document, the best understanding of all aspects of this utility model can be obtained from the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity, the dimensions of the various features can be arbitrarily increased or decreased.

[0006] Figure 1 This is a block diagram of an example optical transceiver according to some embodiments of the present invention.

[0007] Figure 2 This is a top view of an example photonic die having a grating coupler connected to a waveguide, according to some embodiments of the present invention.

[0008] Figure 3 According to some embodiments of the present invention, it includes optical fibers and along... Figure 2A schematic diagram of a device, showing a cross-sectional view of an example photonic chip embodiment taken along line A-A'.

[0009] Figure 4 This is a schematic diagram of a light spot provided by an optical fiber according to some embodiments of the present invention.

[0010] Figure 5 According to some embodiments of this utility model Figure 2 A cross-sectional view of an example photonic chip embodiment taken along line A-A'.

[0011] Figure 6 , Figure 7 , Figure 8 These are some embodiments of the present utility model. Figure 5 A partial cross-sectional view of an example photonic chip.

[0012] Figure 9 This refers to the manufacture of semiconductor structures according to some embodiments of the present invention (e.g.) Figure 2 and Figure 3 The flowchart shows an example method for an example photonic chip.

[0013] Figures 10-21 According to some embodiments of the present utility model Figure 9 A cross-sectional view of the semiconductor structure in the intermediate stage of the example method. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the scope of this invention. These are, of course, merely examples and not intended to be limiting. For instance, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the invention. This repetition is for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0016] Figure 1 This illustrates a block diagram of an example optical transceiver 100. The optical transceiver 100 may include a light modulator 117, a monitoring photodiode 113, and grating couplers 115 and 121. The optical transceiver 100 may also include electrical devices and circuitry, including amplifiers 105 and 123, a digitizer circuit 111, a digital control circuit 101, one or more photodiodes 107, and a control unit 109. For example, amplifiers 105 and 123 may include a transimpedance amplifier and a limiting amplifier (TIA / LA). In some embodiments, the optical transceiver 100 also includes a photonic die 103 with a laser assembly. In some embodiments, the laser assembly includes one or more lasers 131, a lens, a rotator for guiding one or more continuous wave (CW) optical signals, and one or more laser drivers 129.

[0017] In a further embodiment, the optical transceiver 100 includes an input grating coupler 137 configured to receive an optical signal from the laser 131 and an optical beam splitter 133 configured to split the optical signal into four substantially equal power optical signals. In various embodiments, the split power signals are transmitted from the optical beam splitter 133 to the optical modulator 117 via optical waveguides. In some embodiments, the optical beam splitter 133 is coupled to the input grating coupler 137 and at least four output waveguides 102. In some embodiments, the optical beam splitter 133 includes a low-loss Y-junction power divider. In some embodiments, the input grating coupler 137 includes a single polarization grating coupler (SPGC). In some embodiments, the SPGC is a one-dimensional (1D) grating coupler.

[0018] In some embodiments, the optical modulator 117 may include, for example, a Mach-Zehnder or ring modulator, and enable modulation of a continuous-wave (CW) laser input signal. The optical modulator 117 may also include high-speed and low-speed phase modulation sections and be controlled by the control unit 109. In some embodiments, at least one output of each of the optical modulators 117 may be optically coupled to an optical output 120, such as an optical fiber, via a grating coupler 115. In some embodiments, the grating coupler 115 may include a single-polarization grating coupler (SPGC). Other outputs of the optical modulators 117 may be optically coupled to a monitoring photodiode 113, which is configured to provide a feedback path from the outputs of the optical modulators 117 to the control unit 109.

[0019] In addition, the optical transceiver 100 can also utilize the grating coupler 121 to transmit from the optical fiber 400 (see Figure 3 The optical signal is received by an optical fiber 400 array or a grating coupler. In this embodiment, the grating coupler 121 includes a polarization split grating coupler (PSGC), which uses two waveguides (or output waveguides) to transmit the received optical signal to one or more photodiodes 107.

[0020] In some embodiments, the optical transceiver 100 employs one or more photodiodes 107, which may be implemented using epitaxial germanium (Ge) / silicon-germanium (SiGe) films directly deposited on silicon (Si). In some embodiments, the one or more photodiodes 107 may include, for example, a high-speed heterojunction phototransistor and may include germanium (Ge) in the collector and base regions for absorption in the 1200 nm to 1600 nm light wavelength range (e.g., in the 1310 nm to 1550 nm range), and may be integrated on a complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) wafer. The one or more photodiodes 107 may be configured to convert optical signals received from the grating coupler 121 into electrical signals for transmission to the receiver (Rx) 123, which may be configured to combine data streams and multiplex the received optical signals. Furthermore, the received optical signal may be amplified, for example, by a transimpedance amplifier 125 and then transmitted to a small form-factor pluggable (SFP) interface circuit 127. In some embodiments, the optical transceiver 100 also includes digital control circuitry 101 coupled to a serial interface 135 and configured to transmit the received optical data through the serial interface 135.

[0021] like Figure 1As shown, the grating couplers 115 and 137 of the optical transceiver 100 enable the coupling of light into and out of the integrated circuit containing the optical transceiver 100. In some embodiments, the geometric parameters of the grating couplers 115 and 137 can be parameterized during the wiring and placement of the photonic integrated circuit and optimized based on performance indices.

[0022] Figure 2 This illustration shows a top view of a photonic die 200 or a portion thereof according to some embodiments of the present invention. The photonic die 200 includes at least one grating coupler 224 coupled to a waveguide 228. The grating coupler 224 includes a tapered structure 226 (also referred to as a taper region 226) disposed near the waveguide 228. A portion of the grating coupler 224 (e.g., grating line 230 hereinafter) is configured to receive and modulate from an optical fiber (e.g., optical fiber 400 (or an array thereof); see...). Figure 3 The optical input is transmitted via a tapered structure 226 to a waveguide 228. In the depicted embodiment, the grating coupler 224 and the waveguide 228 are arranged adjacent to each other along a first lateral direction (e.g., the X-axis). In some embodiments, the tapered structure 226 is configured immediately adjacent to the waveguide 228 along the first lateral direction. The grating coupler 224 and the waveguide 228 are disposed on (or therein) a semiconductor layer 206. In this respect, the semiconductor layer 206 may also be referred to as a device layer 206 (or photonic device layer 206).

[0023] Reference Figure 3 , it is along Figure 2 A cross-sectional view of the photonic die 200 along line A-A', wherein a semiconductor layer 206 is formed on (or provided on) a dielectric layer 204, which covers a semiconductor substrate 212. In some embodiments, the photonic die 200 corresponds to Figure 1 The portion of the optical transceiver 100 depicted within each dashed-line enclosed area. For example, grating coupler 224 may correspond to grating coupler 115 or 137, and waveguide 228 corresponds to waveguide 102. A tapered structure 226 extends between the portion of grating coupler 224 that receives and modulates the optical input (e.g., grating line 230 hereinafter) and waveguide 228.

[0024] In this embodiment, referencing the return Figure 2 The grating coupler 224 is a one-dimensional (1D) grating coupler, such as a single-polarization grating coupler. The grating coupler 224 includes a set of grating lines 230a, 230b, 230c, 230d, 230e, 230f, 230g, and 230h (hereinafter collectively referred to as grating lines 230). The grating lines 230 are arranged in a concentric pattern and spaced apart from each other along a first transverse direction. As will be described in detail below, the dimensions between the grating lines 230 can vary along the first transverse direction. It is worth noting that, although... Figure 2The image depicts a set of eight grating lines 230, but the embodiments of the photonic chip 200 described in this invention are not limited thereto, and may include, for example, more or fewer grating lines 230.

[0025] In this embodiment, each of the grating lines 230a-230h extends along a curve conforming to a segment of its respective ellipse 232a-232h (or elliptical shapes 232a-232h; hereinafter collectively referred to as ellipse 232). For example, grating line 230a extends along a curve conforming to a segment of ellipse 232a; grating line 230b extends along a curve conforming to a segment of ellipse 232b; grating line 230c extends along a curve conforming to a segment of ellipse 232c; grating line 230d extends along a curve conforming to a segment of ellipse 232d; grating line 230e extends along a curve conforming to a segment of ellipse 232e; grating line 230f extends along a curve conforming to a segment of ellipse 232f; grating line 230g extends along a curve conforming to a segment of ellipse 232g; and grating line 230h extends along a curve conforming to a segment of ellipse 232h. Ellipses 232 are arranged in a concentric pattern 234, wherein the center 236 of the concentric pattern 234 (i.e., the center of each ellipse 232) is located on an axis extending along a first lateral direction. In some embodiments, the center 236 is configured in a tapered structure 226. It is worth noting that the ellipses 232 are not actually present in the photonic die 200, but are used as guidelines to describe the shape and size of their corresponding grating lines 230.

[0026] Still refer to Figure 2 Each ellipse 232 is defined by a major radius R1 and a minor radius R2. The major radius R1 extends along a first lateral direction, and the minor radius R2 extends along a second lateral direction (e.g., the Y-axis) perpendicular to the first lateral direction. For each ellipse 232, the major radius R1 is larger than the minor radius R2, such that the ratio S (S = R1 / R2) of the major radius R1 to the minor radius R2 is greater than 1. In this respect, each ellipse 232 is elongated in the first lateral direction relative to the second lateral direction. In this embodiment, both the major radius R1 and the minor radius R2 decrease along the first lateral direction from ellipse 232h to ellipse 232a. In other words, the major radius R1 and the minor radius R2 of ellipse 232h are both larger than the corresponding dimensions of ellipse 232g, which in turn are larger than the corresponding dimensions of ellipse 232f, and so on. In some embodiments, the ratio S remains substantially constant within the concentric pattern 234. In some embodiments, the ratio S varies between ellipses 232 along the first lateral direction. In some non-limiting examples, the long radius R1 and the short radius R2 each range from about 10 nanometers to about 100 nanometers. In some non-limiting examples, the ratio S ranges from about 1.5 to about 2.6, corresponding to certain optical input conditions described in detail below.

[0027] Figure 3 The illustration depicts a device 500 or a portion thereof according to some embodiments of the present invention. Device 500 includes at least the following: Figure 2 A cross-sectional view along line A-A' shows one embodiment of the photonic chip 200. The device 500 also includes an optical fiber 400 disposed on the photonic chip 200 and configured to provide optical input to the photonic chip 200. In some embodiments, incident light emitted through the fiber core 402 of the optical fiber 400 at an angle of incidence... Apply. In this embodiment, the angle of incidence. Defined as the angle between the axis extending from the fiber core 402 and the standard 213 of the photonic die 200 (i.e., the standard of the top surface of the semiconductor substrate 212 or semiconductor layer 206). In some non-limiting examples, the angle of incidence... The range can be from about 0 degrees to about 15 degrees, for example from about 5 degrees to about 15 degrees. In some embodiments, fiber 400 is single-mode fiber (SMF).

[0028] like Figure 3 and Figure 4 As shown, the fiber core 402 illuminates the grating coupler 224, forming a light spot 410 on the grating coupler 224. The size of the light spot 410 is related to the effective area of ​​the fiber core 402, which is proportional to the optical power when the fiber core 402 is illuminated. The effective area of ​​the fiber core 402 can be further defined by the mode field diameter (MFD). For example, refer to... Figure 4 The light spot 410 provided to the grating coupler has a first radius D1 extending along a first lateral direction and a second radius D2 extending along a second lateral direction. In various embodiments, radii D1 and D2 are determined according to the incident angle as defined herein. And it changes. Regarding the angle of incidence... In an embodiment with an angle of approximately 0 degrees (i.e., the fiber core 402 is substantially parallel to the standard 213 of the photonic core 200), the spot 410 is characterized by a substantially circular shape (not depicted here), with a first radius D1 that is substantially the same as the second radius D2. In this respect, the ratio Q of D1 to D2 (Q = D1 / D2) is approximately 1, and the spot 410 is said to have equal MFD in the first and second transverse directions.

[0029] However, in the existing technology, the angle of incidence Typically, the angle is adjusted to be greater than 0 degrees (i.e., the fiber core 402 is at an angle relative to the standard 213 of the photonic chip 200), for example, about 5 degrees to about 15 degrees, to reduce the reflection of incident light from the grating coupler 224, thereby improving the coupling efficiency of the photonic chip 200. Therefore, referring to Figure 4The light spot 410 illuminating the grating coupler 224 does not have a circular shape, but is characterized by a basic elliptical shape, where the first radius D1 is greater than the second radius D2. As a result, the ratio Q is greater than 1, and the light spot 410 is said to have unequal MFDs in the first and second transverse directions. Radius D1 and D2 can also be referred to as the major and minor radii of the light spot 410, respectively.

[0030] This invention provides a photonic die with a grating coupler whose geometry more closely approximates the geometry of the light spot illuminating the grating coupler, thereby improving coupling efficiency and enhancing the overall performance of the photonic device. For example, compared to the prior art, the grating coupler geometry provided herein improves the peak loss of the grating coupler from approximately 75% to approximately 81%. In this embodiment, the geometry (e.g., shape and size) of the grating lines 230 of the grating coupler 224 is configured such that the curvature of each grating line 230 at least partially overlaps a given incident angle. The curvature of the light spot 410. In other words, the major radius R1 and minor radius R2 of each ellipse 232 are configured such that the curvature of each corresponding grating line 230 is related to the given incident angle. The resulting light spot 410 curvature matches or otherwise crosses that curvature.

[0031] In this regard, according to various embodiments, the ratio S of ellipse 232, defined as the ratio of major radius R1 to minor radius R2, is configured to closely match or be similar to the ratio Q of light spot 410, where ratio Q is defined as the ratio of a given fiber 400 at a given incident angle. The ratio of the long radius D1 to the short radius D2. In some embodiments, the ratio S is substantially equal to the ratio Q. In some embodiments, the long radius R1 and the short radius R2 of the grating line 230 are configured such that the difference between the ratio S and the ratio Q is within ±5% numerically.

[0032] In some embodiments, with the angle of incidence As the angle of incidence increases, the value of the ratio S also increases. This is because, given the angle of incidence... To obtain the value (or range) of the ratio S, first determine (e.g., empirically) the value corresponding to the angle of incidence based on the correlation defined in this paper. The ratio Q can then be used to determine the ratio S as described above. For the angle of incidence... In embodiments ranging from about 0 degrees to about 15 degrees, the ratio S may range from about 1 to about 2.6. Specifically, for the angle of incidence... Examples ranging from about 5 degrees to about 15 degrees, with ratio S ranging from about 1.5 to about 2.6.

[0033] In some instances, the angle of incidence The correlation between the ratio S of the grating lines 230 and the grating line ratio can be determined empirically or by direct measurement. For example, it can be determined at a given incident angle. The size of the light spot 410 is directly measured. In some embodiments, the ratio S of each grating line 230 of the grating coupler 224 remains substantially constant within the concentric pattern.

[0034] Figure 5 Depicting along Figure 2 A cross-sectional view of the photonic chip 200 or a portion thereof taken along line A-A'. As shown, grating lines 230a-230h are defined (or separated) in semiconductor layer 206 by grooves 250a, 250b, 250c, 250d, 250e, 250f, 250g, 250h and 250i (hereinafter collectively referred to as grooves 250). For example, grating line 230a is separated from tapered region 226 by groove 250a; grating line 230b is separated from grating line 230a by groove 250b; grating line 230c is separated from grating line 230b by groove 250c; grating line 230d is separated from grating line 230c by groove 250d; grating line 230e is separated from grating line 230d by groove 250e; grating line 230f is separated from grating line 230e by groove 250f; grating line 230g is separated from grating line 230f by groove 250g; grating line 230h is separated from grating line 230g by groove 250h; and grating line 230h is separated from edge portion 225 of semiconductor layer 206 by groove 250i, wherein edge portion 225 is opposite tapered region 226 along a first lateral direction.

[0035] In this embodiment, the structure of the grating line 230 and the corresponding groove 250 can be defined by various shapes and sizes and can vary within the grating coupler 224. In some cases, the shape and size of the grating line 230 can be adjusted accordingly based on factors such as the peak loss and bandwidth of the grating coupler (e.g., narrow bandwidth or wide bandwidth).

[0036] In some embodiments, refer to Figure 5 The dielectric layer 204 has a thickness BH, and the semiconductor layer 206 has a thickness H1, which is less than the thickness BH. In some non-limiting examples, the thickness H1 may be about 200 nm to about 500 nm, for example, at least about 270 nm and less than about 500 nm. In some non-limiting examples, the thickness BH may be less than about 3 nm. Non-zero values, for example, at least about 2 .

[0037] In some embodiments, still refer to Figure 5The depth of the groove 250 varies along a first lateral direction, wherein each depth extends along a vertical direction (e.g., the Z-axis). For example, grooves 250a-250e may each have a depth H2, while grooves 250f-250i may each have a depth H3, which is less than depth H2. As provided herein, both depths H2 and H3 are less than thickness H1, such that the groove 250 does not penetrate the semiconductor layer 206. Depths H2 and H3 can also be alternatively considered as the height of the grating line 230.

[0038] Various depths of the grooves 250 can be achieved by varying the parameters of the etching process used to pattern the semiconductor layer 206 to form the grating lines 230. For example, various depths can be achieved by varying the duration of the etching process applied to different portions of the semiconductor layer 206 corresponding to different groove locations 250. In this regard, the etching time for grooves 250a-250e with a greater depth (e.g., depth H2) is longer than the etching time for grooves 250f-250i with a shallower depth (e.g., depth H3). In some non-limiting examples, depths H2 and H3 may each be from about 70 nm to about 210 nm. In some non-limiting examples, depth H2 may be at least about 200 nm and depth H3 may be at least about 100 nm. Although not depicted herein, two adjacent grooves 250 may be configured to have different depths. For example, groove 250a has a depth H2, while groove 250b has a depth H3.

[0039] In some embodiments, the width of the groove 250 may vary along a first lateral direction, wherein each width extends along the first lateral direction. For example, groove 250a has a width L1, groove 250b has a width L2, and groove 250c has a width L3, wherein width L1 is greater than width L2, and width L2 is greater than width L3. Widths L1, L2, and L3 may also be alternatively considered as the spacing between adjacent grating lines 230. Although not described in detail herein, additional grooves 250d-250i may also have varying widths along the first lateral direction.

[0040] In some embodiments, still refer to Figure 5 The width of the grating lines 230 also varies along the first transverse direction, with each width extending along this direction. For example, grating line 230a has a width W1, grating line 230b has a width W2, and grating line 230c has a width W3, where width W1 is smaller than width W2, and width W2 is larger than width W3. Although not described in detail herein, additional grating lines 230d-230h may also have varying widths along the first transverse direction.

[0041] In some non-limiting examples, the widths W1, W2, and W3 may each be from about 10 nm to about 600 nm. In some non-limiting examples, the pitch Pn of each grating line 230 (e.g., P1, P2, P3, etc.) is defined as the sum of the width Wn (e.g., W1, W2, W3, etc.) of each grating line 230 and the width Ln (e.g., L1, L2, L3, etc.) of each groove 250 adjacent to that grating line 230, and may also vary along a first lateral direction. In the depicted embodiments, for example, P1 is the sum of width W1 and width L1; P2 is the sum of width W2 and width L2; and P3 is the sum of width W3 and width L3. In some non-limiting examples, for incident light with a wavelength of about 1310 nm, the pitch Pn is less than about 600 nm.

[0042] Furthermore, the grating lines 230 may include various profiles. For example, refer to Figure 6 , Figure 7 and Figure 8 Each of these describes an example embodiment of a cross-sectional view of the grating line 230, wherein each sidewall 260 of the grating line 230 forms a non-zero angle with the horizontal surface 262 of the grating coupler 224. The horizontal surface 262 is parallel to the top surface (not shown) of the semiconductor substrate 212. In some embodiments, reference is made to... Figure 6 The sidewall 260 is substantially perpendicular to the horizontal surface 262, making the angle Approximately 90°. In some embodiments, reference is made to... Figure 7 and Figure 8 The top portions of the opposite sidewalls 260 slope toward each other, causing the angle to... It is an acute angle (i.e., less than approximately 90°). In some non-limiting instances, the angle... It can be from about 60° to about 90°, for example, at least about 85° and less than about 90°. In some embodiments, refer to Figure 7 The bottom portion 264 of the sidewall 260 has a sloping (or sharp) profile. Alternatively, refer to... Figure 8 The bottom portion 264 has a rounded (or smooth) outline.

[0043] It is worth noting that this invention does not limit the various dimensions (e.g., depths H2 and H3, widths Wn and Ln, etc.) of the aforementioned grating lines 230 and grooves 250 to any specific values, nor to any specific variation pattern. In fact, according to some embodiments of this invention, these dimensions may be intentionally randomized to reduce optical reflections (e.g., optical noise) of incident light from the grating coupler 224, thereby improving the coupling efficiency of the photonic die 200. For example, along the first lateral direction from grating line 230a to grating line 230h, the width Wn may first decrease and then increase, while the width Ln may continuously decrease. Although the dimensions of the aforementioned grating lines 230 are not limited to any specific values, grating couplers (such as grating coupler 224) configured with dimensions within the numerical range described herein may exhibit enhanced device performance in terms of peak loss of the photonic die 200.

[0044] Figure 9 A flowchart illustrating a method 600 for forming a semiconductor structure 700 according to one or more embodiments of the present invention is provided. The semiconductor structure 700 may include (or provide) a photonic die 200. It is worth noting that method 600 is merely one example and is not intended to limit the present invention. Therefore, it is understood that various methods may be implemented. Figure 9 Additional operations are provided before, during, and after method 600, and some other operations may only be briefly described herein. In some embodiments, the operation of method 600 may be related to... Figures 10-21 The cross-sectional views of the semiconductor structure 700 at each manufacturing stage are shown in relation to each other, which will be discussed in more detail later.

[0045] Reference Figure 10 Method 600 provides a semiconductor wafer W in operation 602, including a semiconductor substrate 202 (or semiconductor layer), a dielectric layer 204 disposed on the semiconductor substrate 202, and a semiconductor layer 206 disposed on the dielectric layer 204. The semiconductor wafer W may be a silicon-on-insulator (SOI) wafer, including a silicon substrate (e.g., semiconductor substrate 202), a silicon dioxide (SiO2) layer (e.g., dielectric layer 204) disposed on the silicon substrate, and a silicon layer (e.g., semiconductor layer 206) disposed on the silicon dioxide layer, wherein the silicon layer may be a doped layer. The dielectric layer 204 may completely cover the top surface (or front side) of the semiconductor substrate 202. The semiconductor layer 206 may completely cover the top surface of the dielectric layer 204. The thickness of the semiconductor substrate 202 may be between approximately 50 nm. Approximately 760 Between these points, the thickness of the dielectric layer 204 can be between approximately 0.5 mm. Approximately 5 The thickness of the semiconductor layer 206 can be between approximately 100 nm and approximately 5 nm. Between. For example, the thickness of the semiconductor substrate 202 can be approximately 100. The thickness of dielectric layer 204 can be approximately 2. The thickness of semiconductor layer 206 may be approximately 270 nm. The semiconductor wafer W may include other types of semiconductor and dielectric materials, arranged in the configuration described herein.

[0046] Reference Figure 11 and Figure 12 Method 600 involves patterning the semiconductor layer 206 in operation 604 to define the photonic device region of the semiconductor structure 700. (See reference...) Figure 11 A patterned photoresist layer 251 is formed on a semiconductor wafer W to cover a portion of the semiconductor layer 206. The semiconductor layer 206 may include a photonic device region covered by the patterned photoresist layer 251. In some embodiments, the semiconductor layer 206 may also include an electronic device region for forming a semiconductor device (not shown), such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a capacitor, an inductor, a resistor, similar devices, or combinations thereof. The patterned photoresist layer 251 may be formed on the semiconductor layer 206 by a photolithography process, which may include spin coating of the photoresist material, baking of the photoresist material, exposure of the baked photoresist material, and development of the exposed photoresist material.

[0047] Reference Figure 12 A patterning process is performed to remove portions of the semiconductor layer 206 exposed by the patterned photoresist layer 251, thereby forming the semiconductor layer 206 on the dielectric layer 204. The patterning process for the semiconductor layer 206 may include etching processes, such as dry etching, reactive ion etching (RIE), wet etching, similar processes, or combinations thereof, to remove portions of the semiconductor layer 206 until portions of the dielectric layer 204 are exposed. After the patterning process is performed, the patterned photoresist layer 251 is removed from the semiconductor layer 206 by any suitable process, such as plasma ashing, photoresist stripping, or similar processes.

[0048] Reference Figures 13-15 In operation 606, method 600 further patternes the semiconductor layer 206 to form a grating coupler 224, which includes grating lines 230, a tapered structure 226, and a waveguide 228. (See reference...) Figure 13 and Figure 14 A patterned photoresist layer 252 is formed to cover the semiconductor layer 206 and the dielectric layer 204. The patterned photoresist layer 252 can be formed on the semiconductor layer 206 and the dielectric layer 204 by the photolithography process provided herein.

[0049] In this embodiment, the patterned photoresist layer 252 includes a slit pattern corresponding to a set of grating line 230 geometries of the grating coupler 224. In one example, the slit pattern defined in the patterned photoresist layer 252 may correspond to... Figure 2 This is one embodiment of the arrangement of grating lines 230 depicted. In another example, the slit pattern defined in the patterned photoresist layer 252 may correspond to... Figure 3 One embodiment of the arrangement of grating lines 230 depicted herein. In yet another example, the slit pattern defined in the patterned photoresist layer 252 may correspond to... Figure 5 One embodiment of the arrangement of grating lines 230 depicted herein. In particular, the shape, position, and / or size of the grating lines 230 correspond to the shape, position, and / or size of the slits that will be formed in the semiconductor layer 206 by a subsequent patterning process.

[0050] Reference Figure 14 A patterning process is performed to remove portions of the semiconductor layer 206 exposed by the patterned photoresist layer 252, such that the semiconductor layer 206, including a grating coupler 224 and a waveguide 228, is formed on the top surface of the dielectric layer 204. The grating coupler 224 includes a set of grating lines 230 and a tapered structure 226 extending from the set of grating lines 230 toward the waveguide 228. The patterning process may include an etching process to remove portions of the semiconductor layer 206 exposed by the patterned photoresist layer 252. The etching depth of the removal process may be less than the thickness H1 of the semiconductor layer 206. In this embodiment, the etching depth of the patterning process may correspond to depths H2 and H3, for example, from about 70 nanometers to about 210 nanometers as described herein (see...). Figure 5 In some embodiments, the patterning process may include multiple etching processes, such as dry etching, reactive ion etching (RIE), wet etching, similar processes, or combinations thereof.

[0051] After patterning, the grating coupler 224 and waveguide 228 are interconnected along a first lateral direction on a portion of the semiconductor layer 206 overlapping the dielectric layer 204. (Refer to...) Figure 15 After performing the patterning process, the patterned photoresist layer 252 is removed from the semiconductor layer 206 and the dielectric layer 204 using any suitable process provided herein.

[0052] Reference Figure 16 Then, a patterned photoresist layer 254 can be formed using the photolithography process provided herein to cover portions of the semiconductor layer 206 and the dielectric layer 204. In some embodiments, the semiconductor layer 206 is completely covered by the patterned photoresist layer 254.

[0053] Reference Figure 17A patterning process is performed to remove portions of the dielectric layer 204 exposed by the patterned photoresist layer 254, thereby giving the dielectric layer 204 a predetermined pattern on the semiconductor substrate 202. The patterning process may include an etching process to remove portions of the dielectric layer 204 until portions of the semiconductor substrate 202 are exposed. After the patterning process is performed, the patterned photoresist layer 254 is removed from the semiconductor layer 206 and the dielectric layer 204 using any suitable process provided herein. In some embodiments, the patterning process for removing portions of the dielectric layer 204 may be omitted.

[0054] Reference Figure 18 In method 600, in operation 608, a semiconductor structure 700 is bonded to a carrier 272 (also called a carrier wafer, control wafer, etc.) using an adhesive layer 270 formed on the carrier 272. The carrier 272 may include a glass carrier, and the adhesive layer 270 may be a photothermal conversion (or photothermal conversion, or LTHC) layer adhered to the surface of the carrier 272. The resulting semiconductor wafer W1 includes a semiconductor substrate 202, a dielectric layer 204, and a semiconductor layer 206, which are temporarily bonded to the carrier 272 via the adhesive layer 270. After the semiconductor wafer W1 is temporarily bonded to the carrier 272, the semiconductor layer 206 comes into contact with the adhesive layer 270. In other words, the carrier 272 and the semiconductor wafer W1 are located on opposite sides of the adhesive layer 270.

[0055] Reference Figure 19 In method 600, operation 610 removes the semiconductor substrate 202 from the back side 204a (or bottom surface) of the dielectric layer 204, temporarily placing the front side (or top surface) of the semiconductor structure 700 under the support 272 and exposing the back side of the dielectric layer 204. In some embodiments, the semiconductor substrate 202 is removed from the dielectric layer 204 by a laser lift-off process, a back-side etching process, a polishing process, or a similar process. The polishing process may include mechanical polishing, chemical-mechanical polishing (CMP), similar processes, or combinations thereof.

[0056] Reference Figure 20 In method 600, in operation 612, the front side 212a (or top surface) of the semiconductor substrate 212 (or semiconductor layer) is bonded to the back side of the dielectric layer 204. In some embodiments, the front side of the semiconductor substrate 212 is bonded to the back side of the dielectric layer 204 via a wafer-to-wafer fusion bonding process, a hybrid bonding process, or a similar process. The bonding temperature of the wafer-to-wafer fusion bonding process can range from about 200 degrees Celsius to about 600 degrees Celsius.

[0057] Reference Figure 21In method 600, a debonding process is performed in operation 614 to remove the carrier 272 and the adhesive layer 270 from the semiconductor structure 700. The carrier 272 and the adhesive layer 270 can be debonded from the semiconductor layer 206 by irradiating the semiconductor structure 700 with a laser, which heats and subsequently releases the adhesive layer 270 and the carrier 272 from the semiconductor layer 206. In various embodiments of this invention, operations 608 to 614 described herein are optional and may be omitted during the fabrication of the semiconductor structure 700.

[0058] Method 600 can perform additional operations in operation 616. For example, still refer to Figure 21 The semiconductor structure 700 can be cut along the dicing line SL to obtain the photonic die 200, such as... Figure 3 As shown, it includes a semiconductor substrate 212, a dielectric layer 204 on the semiconductor substrate 212, and a semiconductor layer 206 on the dielectric layer 204. The semiconductor layer 206 includes a grating coupler 224 connected (or coupled) to the waveguide 228. In this embodiment, the grating coupler 224 includes, as shown... Figure 2 , Figure 3 and / or Figure 5 A set of grating lines 230 is shown. The photonic die 200 may be further packaged, integrated with other dies (e.g., electronic dies, photonic dies, etc.), or otherwise processed to form a semiconductor device.

[0059] In one aspect, the present invention provides a semiconductor structure. The semiconductor structure includes a semiconductor layer. The semiconductor structure includes a grating coupler disposed on the semiconductor layer. The semiconductor structure also includes a waveguide disposed on the semiconductor layer and laterally adjacent to the grating coupler. The grating coupler includes a plurality of grating lines. Each grating line extends along a segmental curve conforming to an ellipse, wherein the ellipse is defined by a radius R1 and a radius R2 smaller than radius R1.

[0060] In some embodiments, the grating lines are spaced apart from each other along the lateral direction.

[0061] In some embodiments, the grating lines are arranged in a concentric pattern.

[0062] In some embodiments, the grating coupler includes a first grating line and a second grating line, the first grating line having a first width along the lateral direction, the second grating line having a second width along the lateral direction, and the second width being different from the first width.

[0063] In some embodiments, the grating coupler further includes a third grating line. The first grating line and the second grating line are separated by a first groove having a third width along the lateral direction, the second grating line and the third grating line are separated by a second groove having a fourth width along the lateral direction, and the third width is different from the fourth width.

[0064] In some embodiments, the first groove has a first depth along a vertical direction perpendicular to the lateral direction, the second groove has a second depth along the vertical direction, and the first depth is different from the second depth.

[0065] In some embodiments, the sidewalls of each of the grating lines include a bottom portion having a circular profile.

[0066] In some embodiments, the sidewalls of each of the grating lines are inclined relative to the top surface of the semiconductor layer.

[0067] On the other hand, this invention provides a photonic chip. The photonic chip includes a substrate. The photonic chip also includes a device layer disposed on the substrate. The device layer includes a grating coupler and a waveguide adjacent to the grating coupler. The grating coupler includes a plurality of grating lines arranged concentrically in the transverse direction on the device layer. Each grating line extends along a segment of an ellipse, wherein the ellipse is defined by a major radius and a minor radius. The ratio of the major radius to the minor radius is greater than one.

[0068] In some embodiments, the die further includes a dielectric layer disposed between the substrate and the device layer.

[0069] In some embodiments, the grating coupler includes a tapered structure, and the tapered structure is disposed adjacent to the waveguide along the lateral direction.

[0070] In some embodiments, the sidewalls of each of the grating lines include a bottom portion having a circular profile.

[0071] In some embodiments, the spacing between two adjacent grating lines varies along the lateral direction, and each of the spacings extends along the lateral direction.

[0072] In some embodiments, the width of the grating lines varies along the lateral direction, and each of the widths extends along the lateral direction.

[0073] In some embodiments, the height of the grating lines varies along the lateral direction, and each of the heights extends along a vertical direction perpendicular to the lateral direction.

[0074] In another aspect, the present invention provides a method comprising providing a first semiconductor layer on a dielectric layer, wherein the dielectric layer includes a bottom surface. The method includes forming a grating coupler and a waveguide in the first semiconductor layer. The grating coupler includes a plurality of bent grating lines spaced laterally from each other. Each bent grating line extends along a segment of an ellipse, wherein the ellipse is defined by a first radius and a second radius different from the first radius. The method includes providing a second semiconductor layer having a second top surface. The method further includes bonding the bottom surface to the second top surface to form a semiconductor structure.

[0075] In some embodiments, forming the grating coupler includes etching the first semiconductor layer to form the curved grating lines.

[0076] In some embodiments, forming the grating coupler includes forming a plurality of grooves, each groove being inserted between two adjacent curved grating lines, and wherein the depth of the grooves varies along the lateral direction.

[0077] In some embodiments, the dielectric layer is provided on a third semiconductor layer, and the method further includes: bonding the first semiconductor layer having the grating coupler to a carrier before bonding the bottom surface to the top surface; and removing the third semiconductor layer to expose the bottom surface of the dielectric layer.

[0078] In some embodiments, the method further includes dicing the semiconductor structure to form a photonic die including the grating coupler and the waveguide.

[0079] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor layer; A grating coupler, disposed on the semiconductor layer, includes a plurality of grating lines, each of which extends along a curve conforming to an ellipse, the ellipse being defined by a radius R1 and a radius R2 smaller than radius R1; and A waveguide is disposed on the semiconductor layer and adjacent to the grating coupler in the lateral direction.

2. The semiconductor structure according to claim 1, characterized in that, The grating lines are arranged in a concentric pattern.

3. The semiconductor structure according to claim 1, characterized in that, The grating coupler includes a first grating line and a second grating line. The first grating line has a first width along the lateral direction. The second grating line has a second width along the lateral direction, and The second width is different from the first width.

4. The semiconductor structure according to claim 3, characterized in that, The grating coupler also includes a third grating line. The first grating line and the second grating line are separated by a first groove having a third width along the lateral direction. The second grating line and the third grating line are separated by a second groove having a fourth width along the lateral direction, and The third width is different from the fourth width.

5. The semiconductor structure according to claim 4, characterized in that, The first groove has a first depth along a vertical direction perpendicular to the lateral direction. The second groove has a second depth along the vertical direction, and The first depth is different from the second depth.

6. The semiconductor structure according to claim 1, characterized in that, The sidewalls of each of the grating lines are inclined relative to the top surface of the semiconductor layer.

7. A die, characterized in that, include: Substrate; as well as A device layer, disposed above the substrate, the device layer comprising: A grating coupler has a plurality of grating lines arranged in a concentric pattern along a transverse direction on a device layer, wherein each of the grating lines extends along an ellipse defined by a major radius and a minor radius, and the ratio of the major radius to the minor radius is greater than one. Waveguide, adjacent to the grating coupler.

8. The die according to claim 7, characterized in that, It also includes a dielectric layer disposed between the substrate and the device layer.

9. The die according to claim 7, characterized in that, The grating coupler includes a tapered structure, and The tapered structure is disposed adjacent to the waveguide along the lateral direction.

10. The die according to claim 7, characterized in that, Each of the grating lines has a bottom portion with a circular outline on its sidewalls.

Images