Silicon light engine and co-packaged optical system

Abstract

The application discloses a silicon light engine and a co-encapsulation optical system, the silicon light engine comprising a carrier plate, a silicon light chip, a driving chip and a fiber array; the carrier plate has a first face and a second face opposite to each other, the first face is provided with a quick plug connector used for plugging with a plug on a mainboard. The silicon light chip and the driving chip are arranged on the second face, and the driving chip and the silicon light chip are coupled with the quick plug connector; the fiber array is coupled with an outlight end face of the silicon light chip. In this way, when a fault occurs in a certain channel, the corresponding silicon light engine can be directly removed and replaced with a new one, so that the system availability, operation and maintenance efficiency are ensured, and the failure risk is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a silicon photonics engine and a co-packaged optical system. Background Technology

[0002] With the continuous growth in bandwidth demands from data centers and high-performance computing, co-packaged optics (CPO) technology has become a research hotspot in the communications field. CPO technology significantly shortens the electrical interconnect path by directly integrating traditionally independently deployed optical modules onto the motherboard where the switch's main chip resides. This effectively reduces losses and delays in high-speed signal transmission and drastically reduces the power consumption and size of the entire system. Currently, CPO systems typically employ surface mount technology (SMT) to densely solder or bond multiple sets of optical and electrical components around the switch's main chip in a specific layout, achieving extremely high system integration.

[0003] However, increased system integration also brings a series of new engineering challenges, especially in fault repair and component replacement. When an optical or electrical component in a channel fails, the common practice in current technology is to power off the entire switch motherboard, remove it from the device, and send it back to the manufacturer for repair. During this process, since optical components are typically bonded with adhesive and cured at high temperatures, while electrical components are soldered to the motherboard, replacing either optical or electrical components requires subjecting the entire motherboard to high-temperature baking again to complete the repair. This overall high-temperature reprocessing inevitably poses a risk of thermal stress damage to other normally functioning optical and electrical components on the motherboard, affecting their long-term reliability.

[0004] To alleviate the aforementioned problems, existing technologies have proposed a partially pluggable design approach. This involves designing high-temperature-sensitive critical components (such as fiber optic arrays) in optical devices as pluggable modules. These sensitive components are removed before rework and reinserted after the high-temperature rework process is completed. While this approach reduces the risk of thermal damage to some extent, it still has significant shortcomings: First, even if only one channel fails, the entire switch motherboard still needs to be powered off and disassembled and returned to the factory, which seriously affects system availability and maintenance efficiency. Secondly, during the repair process, to avoid high-temperature damage, all pluggable optical modules of all channels must be removed, not just the faulty channel. Considering that switch motherboards typically integrate a large number of channels, removing all of them is not only extremely time-consuming and labor-intensive, but each plugging and unplugging process itself will also cause mechanical wear or contamination to the optical interfaces, increasing the additional risk of failure. Utility Model Content

[0005] The purpose of this application is to provide a silicon photonics engine and a co-packaged optical system. When a certain channel fails, the corresponding silicon photonics engine can be directly removed and replaced with a new one, ensuring system availability and maintenance efficiency while reducing the risk of failure.

[0006] The embodiments of this application can be implemented as follows: In a first aspect, this utility model provides a silicon photonics engine, including a carrier board, a silicon photonics chip, a driver chip, and an optical fiber array; The carrier board has a first side and a second side facing away from each other. The first side is provided with a quick-connect connector, which is used to connect to a plug on the motherboard. Both the silicon photonics chip and the driver chip are disposed on the second surface, and both the driver chip and the silicon photonics chip are coupled to the quick-connect connector. The fiber array is coupled to the light-emitting end face of the silicon photonic chip.

[0007] In an optional embodiment, the carrier plate is provided with a clearance window that extends through the first surface and the second surface; The silicon photonics chip partially covers the avoidance window; A portion of the fiber optic array is located within the avoidance window.

[0008] In an optional embodiment, the fiber array includes a glass block, optical fibers, a glass cover plate, and an adhesive pad. The glass block and the glass cover plate together clamp the optical fiber, and the glass block and the glass cover plate are bonded together; The optical fiber's input end is coupled to the silicon photonic chip; Both the glass block and the glass cover are bonded to the light-emitting end face of the silicon photonic chip; The adhesive pad is located inside the clearance window, and a portion of the adhesive pad is bonded to the glass cover plate, while the other portion is bonded to the side of the silicon photonic chip facing the clearance window.

[0009] In an optional embodiment, a preset gap is left between the outer peripheral wall of the adhesive pad and the inner peripheral wall of the clearance window.

[0010] In an optional implementation, the preset gap is greater than or equal to 1 mm.

[0011] In an optional embodiment, the glass cover portion is recessed into the clearance window; The adhesive pad has a first adhesive surface and a second adhesive surface. The first adhesive surface is bonded to the glass cover plate, and the second adhesive surface protrudes relative to the first adhesive surface and is closer to the glass block. The second adhesive surface is bonded to the silicon photonic chip.

[0012] In an optional embodiment, the first adhesive surface protrudes beyond the edge of the glass cover along the length of the optical fiber; An avoidance groove is formed between the first adhesive surface and the silicon photonic chip.

[0013] In an optional embodiment, the width of the clearance groove in the direction of the fiber length is greater than or equal to 0.5 mm.

[0014] In an optional embodiment, the fiber array further includes a multi-core fiber connector connected to the light-emitting end of the fiber.

[0015] Secondly, this utility model provides a co-packaged optical system, including a motherboard and a silicon photonic engine as described in any of the foregoing embodiments, wherein the motherboard has a plug and the quick-connect connector is plugged into the plug.

[0016] Compared with the prior art, the beneficial effects of the embodiments of this application include, for example: By integrating the silicon photonics chip and driver chip onto the second side of the carrier board, and providing quick-connect connectors on the first side of the carrier board for interfacing with the connectors on the motherboard, a modular and pluggable packaging form for the entire silicon photonics engine is achieved. This structure allows the silicon photonics engine to function as an independent functional unit, enabling quick and easy replacement directly from the system without disassembling or powering off the entire switch motherboard. When a silicon photonics engine in a certain channel fails, maintenance personnel only need to unplug the corresponding silicon photonics engine for the faulty channel and replace it with a new one to complete the device replacement, eliminating the need to return the entire board to the factory for repair, significantly improving the maintainability and availability of the system.

[0017] Meanwhile, because the fiber array inside the silicon photonics engine is directly coupled to the light-emitting end face of the silicon photonics chip and is entirely encapsulated on the carrier board, the risks of multiple mechanical connections and contamination caused by the need for separate plugging and unplugging of the fiber array in traditional CPO solutions are avoided. During maintenance, there is no need to disassemble the optical components of other normal channels; only the faulty silicon photonics engine needs to be replaced. This reduces operational complexity and effectively avoids additional failure risks introduced by repeated plugging and unplugging of non-faulty channels.

[0018] Furthermore, the electrical connection between the quick-connect connector and the motherboard plug replaces the traditional SMT soldering or adhesive bonding process, completely avoiding the risk of thermal stress damage to surrounding components caused by high-temperature rework. The compact coupling layout of the driver chip and silicon photonics chip on the second side of the carrier not only shortens the electrical interconnection path, which is beneficial to high-speed signal integrity, but also further reduces power consumption and latency, continuing the core advantages of CPO technology. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is one of the schematic diagrams of a silicon photonics engine according to an embodiment of this application; Figure 2 This is a second schematic diagram of a silicon photonics engine according to an embodiment of this application; Figure 3 This is the third schematic diagram of the silicon photonics engine in the embodiments of this application; Figure 4 for Figures 1 to 3 One of the partial structural diagrams of a fiber optic array; Figure 5 for Figures 1 to 3 Partial structural diagram of a fiber optic array (Part 2); Figure 6 for Figure 3 One of the sectional views; Figure 7 for Figure 3 The second sectional view.

[0021] Icons: 010-Carrier board; 011-Quick connector; 012-Avoidance window; 013-First side; 014-Second side; 020-Silicon photonic chip; 030-Driver chip; 040-Fiber array; 041-Glass block; 042-Fiber optic cable; 043-Glass cover; 044-Adhesive pad; 045-Multi-core fiber optic connector; 046-First adhesive surface; 047-Second adhesive surface; 048-Avoidance groove. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0027] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0029] This application discloses a co-packaged optical system that can be applied to optical switches, as well as to high-performance computing devices, artificial intelligence accelerators, data center interconnect systems, optical interconnect network devices, and other communication or computing platforms that require high bandwidth, low power consumption, and high-density optoelectronic integration.

[0030] The co-packaged optical system includes a motherboard and multiple silicon photonic engines. The motherboard integrates chips (such as the main chip of a switch), and each silicon photonic engine serves as an optical channel, which is coupled to a connector on the motherboard to achieve high-speed conversion and transmission between electrical signals and optical signals.

[0031] refer to Figures 1 to 3 The silicon photonics engine includes a carrier board 010, a silicon photonics chip 020, a driver chip 030, and a fiber array 040. The carrier board 010 has a first side 013 and a second side 014 that are opposite to each other. The first side 013 is provided with a quick connector 011, which is used to connect to a plug on the motherboard.

[0032] Both the silicon photonics chip 020 and the driver chip 030 are located on the second surface 014, and both the driver chip 030 and the silicon photonics chip 020 are coupled to the quick connector 011. The driver chip 030 and the silicon photonics chip 020 are coupled. The fiber array 040 is coupled to the light-emitting end face of the silicon photonic chip 020.

[0033] Thus, by integrating the silicon photonics chip 020 and driver chip 030 onto the second side 014 of the carrier board 010, and setting a quick-connect connector 011 on the first side 013 of the carrier board 010 for connection with the plug on the motherboard, a modular and pluggable packaging form for the entire silicon photonics engine is achieved. This structure allows the silicon photonics engine to function as an independent functional unit, which can be quickly plugged in and replaced directly from the system without disassembling or powering off the entire switch motherboard. When a silicon photonics engine in a certain channel fails, maintenance personnel only need to unplug the silicon photonics engine corresponding to the failed channel and replace it with a new one to complete the device replacement, without having to return the entire board to the factory for repair, significantly improving the maintainability and availability of the system.

[0034] Meanwhile, since the fiber array 040 inside the silicon photonics engine is directly coupled to the light-emitting end face of the silicon photonics chip 020 and is entirely encapsulated on the carrier board 010, the risks of multiple mechanical connections and contamination caused by the need to individually plug and unplug the fiber array 040 in traditional CPO solutions are avoided. During maintenance, there is no need to disassemble the optical components of other normal channels; only the faulty silicon photonics engine needs to be replaced. This reduces operational complexity and effectively avoids additional failure risks introduced by repeated plugging and unplugging of non-faulty channels.

[0035] Furthermore, the electrical connection between the quick-connect connector 011 and the motherboard connector replaces the traditional SMT soldering or adhesive bonding process, completely avoiding the risk of thermal stress damage to surrounding components caused by high-temperature rework. The compact coupling layout of the driver chip 030 and the silicon photonics chip 020 on the second side 014 of the carrier board 010 not only shortens the electrical interconnection path, which is beneficial to high-speed signal integrity, but also further reduces power consumption and latency, continuing the core advantages of CPO technology.

[0036] In this embodiment, the carrier board 010 is provided with an avoidance window 012 that penetrates the first surface 013 and the second surface 014; the silicon photonic chip 020 partially covers the avoidance window 012; and part of the fiber array 040 is located within the avoidance window 012.

[0037] Thus, the clearance window 012 provides installation space for the fiber array 040, allowing the fiber array 040 to be partially recessed into the clearance window 012, reducing the overall thickness of the silicon photonic engine and improving structural compactness.

[0038] For details, please refer to the following: Figure 4 and Figure 5 The fiber array 040 includes a glass block 041, an optical fiber 042, a glass cover plate 043, and an adhesive pad 044. Glass block 041 and glass cover plate 043 together clamp optical fiber 042, and glass block 041 and glass cover plate 043 are bonded together. The light-inlet end of optical fiber 042 is coupled to silicon photonic chip 020; Both the glass block 041 and the glass cover plate 043 are bonded to the light-emitting end face of the silicon photonic chip 020. The adhesive pad 044 is located inside the clearance window 012, and a portion of the adhesive pad 044 is bonded to the glass cover plate 043, while the other portion is bonded to the side of the silicon photonic chip 020 facing the clearance window 012.

[0039] This configuration, firstly, utilizes the structure where glass block 041 and glass cover plate 043 jointly clamp the optical fiber 042, enabling high-precision and stable mechanical positioning and protection for multiple optical fibers 042. Secondly, by directly bonding glass block 041 and glass cover plate 043 to the light-emitting end face of silicon photonic chip 020, an integrated optical coupling interface is formed. This not only shortens the optical path transmission distance but also reduces Fresnel reflection and mode field mismatch losses introduced by air gaps or intermediate media, significantly improving coupling efficiency. The adhesive pad 044 is recessed into the clearance window 012, with one end bonded to the glass cover plate 043 and the other end bonded to the side of silicon photonic chip 020 facing the clearance window 012. This enhances the mechanical connection stability of the entire fiber array 040 and silicon photonic chip 020 coupling, preventing shaking or displacement during insertion, removal, transportation, or operation, further ensuring the long-term reliability of the optical coupling.

[0040] Understandably, glass materials possess excellent thermal stability, dimensional stability, and optical transparency, which can effectively suppress the displacement of fiber 042 caused by temperature changes or mechanical vibrations. This ensures long-term stable coupling alignment between fiber 042 and the light-emitting end face of silicon photonic chip 020, thereby improving the reliability and consistency of optical interconnects.

[0041] refer to Figure 2 A pre-set gap is left between the outer peripheral wall of the adhesive pad 044 and the inner peripheral wall of the clearance window 012. This decouples the direct mechanical contact between the adhesive pad 044 and the carrier plate 010, avoiding additional shear stress or constraint force generated during temperature changes due to the difference in thermal expansion coefficients between the carrier plate 010 (usually an organic substrate or ceramic material) and the adhesive pad 044 (which may be silicone, epoxy resin or other polymer materials). This improves the structural stability and long-term reliability of the entire silicon photonic engine under wide temperature range operating conditions.

[0042] Furthermore, the pre-set gap provides the necessary tolerance space for the minor deformation of the adhesive gasket 044 during the curing process or service. In the packaging process, the adhesive material may shrink in volume during curing; in actual operation, localized strain may occur due to vibration, impact, or thermal cycling. If the adhesive gasket 044 is tightly fitted to the wall of the clearance window 012, these deformations will be forcibly constrained, leading to internal stress accumulation and affecting the optical coupling alignment accuracy. By providing a pre-set gap, the adhesive gasket 044 can deform freely within a controlled range, maintaining its connection function while avoiding interference with optical alignment.

[0043] Furthermore, this gap simplifies the assembly process. During the alignment and bonding of the fiber array 040 and the silicon photonics chip 020, there is no need to strictly control the fit tolerances between the bonding pad 044 and the clearance window 012 wall, reducing manufacturing difficulty and yield loss. Simultaneously, when the silicon photonics engine is replaced as a single module via quick-plugging, this gap also avoids jamming or interference problems caused by minor deformations of the carrier board 010 or assembly deviations, improving the smoothness of module insertion and removal and repeatability.

[0044] Optionally, the preset gap is greater than or equal to 1mm. A larger gap ensures that even under extreme temperature changes, the deformation of the adhesive gasket 044 due to material expansion or contraction will not be physically restricted by the wall of the avoidance window 012, thereby preventing stress from being transmitted back to the silicon photonics chip 020 or the fiber optic coupling interface 042, significantly improving the reliability of the module under long-term thermal cycling. Moreover, a gap of ≥1mm is compatible with the processing precision of conventional PCBs or ceramic substrates, reducing reliance on high-cost precision machining, which is beneficial for large-scale mass production and cost control.

[0045] Of course, in some embodiments, the preset gap can be less than 1mm, such as 0.5mm, 0.8mm, etc., as long as there is a gap.

[0046] refer to Figure 6 and Figure 7 The glass cover plate 043 is partially recessed into the clearance window 012; the adhesive pad 044 has a first adhesive surface 046 and a second adhesive surface 047 (the dimensions of length, width and thickness are not limited, for example, 1.5mm, 1mm and 0.15mm respectively, the length direction is perpendicular to the length direction of the optical fiber 042 and parallel to the second surface 014, the width direction is the length direction of the optical fiber 042, and the thickness direction is perpendicular to the second surface 014). The first adhesive surface 046 is bonded to the glass cover plate 043, and the second adhesive surface 047 protrudes relative to the first adhesive surface 046 and is closer to the glass block 041. The second adhesive surface 047 is bonded to the silicon photonic chip 020.

[0047] In this way, firstly, the design of the glass cover plate 043 being partially recessed into the avoidance window 012 effectively reduces the overall height of the entire fiber array 040 in the thickness direction of the carrier plate 010, which helps to achieve a more compact module packaging.

[0048] Secondly, the adhesive pad 044 adopts an asymmetrical stepped structure. The first adhesive surface 046 connects to the recessed glass cover plate 043, while the second adhesive surface 047 protrudes and directly bonds to the side of the silicon photonic chip 020 facing the clearance window 012. This achieves precise adaptation of the three-dimensional spatial position between the silicon photonic chip 020 and the fiber array 040. Since the silicon photonic chip 020 is typically located on the second surface 014 of the carrier plate 010, and its light-emitting end face needs to be aligned with the end face of the fiber optic cable 042 embedded in the clearance window 012, there is a natural height difference between the two in the thickness direction of the glass cover plate 043. By making the second adhesive surface 047 protrude to match this height difference, the adhesive pad 044 can provide reliable adhesion while naturally compensating for the step between the silicon photonic chip 020 and the glass cover plate 043, avoiding torsional stress or alignment deviations introduced by forced planar bonding.

[0049] The light-emitting end face of the silicon photonic chip 020, together with the glass block 041 and the glass cover plate 043, constitutes a critical coupling region for optical signal transmission. Here, an optical adhesive with low refractive index matching, high transmittance, and low curing shrinkage (such as UV-curable acrylate or silicone-based optical adhesives) is used. This means that the light-emitting end face of the silicon photonic chip 020, the glass block 041, and the glass cover plate 043 can all be bonded together using optical adhesive. This minimizes Fresnel reflection, scattering loss, and mode field mismatch, ensuring efficient and stable optical coupling. Simultaneously, the optical adhesive typically possesses good long-term aging stability and low fluorescence properties, avoiding interference with high-speed optical signals.

[0050] The second adhesive surface 047 of the adhesive pad 044 is bonded to the non-optical path area of ​​the silicon photonic chip 020 (i.e., the side of the silicon photonic chip 020 facing the second surface 014) using a high-strength, high-modulus, and heat-resistant reinforcing adhesive (such as modified epoxy resin or polyimide adhesive). In other words, the second adhesive surface 047 is bonded to the silicon photonic chip 020 using this reinforcing adhesive, which primarily serves mechanical fixing, stress buffering, and heat conduction functions. Although this adhesive does not participate in light transmission, its high adhesive strength effectively resists displacement caused by insertion / removal impacts, vibrations, and thermal cycling, preventing warping or delamination of the silicon photonic chip 020.

[0051] On the one hand, since silicon photonics chips 020 are usually separated into individual chips through wafer dicing (such as dicing or laser cutting) processes, their edges inevitably have micron-level burrs, chipping, or irregular shapes. If there is no clearance, these burrs may scratch the surface of the glass cover plate 043, the fiber optic cladding 042, or the adhesive pad 044 during the mounting process.

[0052] On the other hand, during the encapsulation process, the reinforcing adhesive used between the second adhesive surface 047 and the silicon photonic chip 020 usually has high viscosity, large curing shrinkage rate, or contains filler components. If it overflows into the optical coupling area, it may contaminate the light-emitting end face of the silicon photonic chip 020 or the end face of the glass block 041 / optical fiber 042.

[0053] To address the aforementioned issues, this embodiment continues to refer to... Figure 6 and Figure 7 The first adhesive surface 046 protrudes from the edge of the glass cover plate 043 along the length direction of the optical fiber 042; a clearance groove 048 is formed between the first adhesive surface 046 and the silicon photonic chip 020.

[0054] In this way, on the one hand, by setting the clearance groove 048, the corner areas of the silicon photonic chip 020 are suspended in the groove, avoiding direct contact with the first bonding surface 046 or other structures. This fundamentally eliminates the physical interference and potential damage risks caused by burrs, improving packaging yield and long-term mechanical stability. On the other hand, the clearance groove 048, as a physical isolation channel, can effectively collect and limit the flow range of the reinforcing adhesive, confining it to the non-optical area. Even if the reinforcing adhesive slightly overflows due to over-dispensing or curing expansion, it will preferentially fill the clearance groove 048 and will not spread to the optical adhesive bonding interface above (i.e., between the light-emitting end face of the silicon photonic chip 020 and the glass block 041 / glass cover plate 043), thereby ensuring the cleanliness of the optical path area and the specificity of the adhesive function.

[0055] The clearance groove 048 has a width of 0.5mm or greater along the length of the fiber 042. This ensures that even with large burrs, the fiber 042 will fall completely within the groove without contacting the surrounding structure, thus guaranteeing the coplanarity and structural integrity of the chip mounting. Furthermore, it provides ample space for adhesive to be contained, preventing any overflowing reinforcing adhesive from crossing into the optically sensitive area. This achieves physical isolation of the functional adhesive material, ensuring stable and reliable optical performance.

[0056] Of course, in some embodiments, the width of the clearance groove 048 can also be 0.4 mm, etc.

[0057] The fiber array 040 also includes a multi-core fiber optic connector 045, which connects to the output end of fiber optic cable 042. By directly integrating the multi-core fiber optic connector 045 (such as standard or customized interfaces like MPO and MXC) at the output end of fiber optic cable 042, standardized and rapid interfacing between the silicon photonics engine and external optical cables or backplanes is achieved. Therefore, the introduction of the multi-core fiber optic connector 045 is highly compatible with the modular design concept of the silicon photonics engine. When the silicon photonics engine in a certain channel fails, the entire module (including the internal silicon photonics chip 020, driver chip 030, fiber array 040, and connectors) can be quickly replaced as a unified unit, while the connectors on the external optical cable side remain unchanged or only require simple decoupling. This plug-and-play approach avoids the problem of entire board rework due to single-point failure in traditional CPO solutions, achieving independent maintenance at the single-channel level and greatly improving system availability and operational flexibility.

[0058] In summary, this embodiment has at least the following advantages compared to the prior art: 1. Achieve rapid maintainability at the single-channel level: By integrating the silicon photonics chip 020, driver chip 030, fiber array 040, and multi-core fiber connector 045 onto the carrier board 010, and setting a quick-connect connector 011 on the first side 013 of the carrier board 010, the entire silicon photonics engine becomes a standardized, hot-swappable, independent module. When a channel fails, only the silicon photonics engine of that channel needs to be replaced, without requiring the entire board to be powered off, disassembled, or returned to the factory for repair, significantly improving system availability and operational efficiency.

[0059] 2. Effectively avoid thermal damage to non-faulty components during high-temperature repairs: Abandoning the traditional SMT soldering and adhesive curing followed by overall baking rework method, it adopts quick-connect electrical connection and pre-cured modular packaging, completely avoiding the risk of thermal stress to surrounding normal optical / electrical components caused by high-temperature reprocessing, and ensuring the long-term reliability of the system.

[0060] 3. The 048 clearance groove design solves multiple engineering pain points: The clearance groove 048 (width ≥ 0.5 mm) not only effectively accommodates the burrs generated during the cutting of the silicon photonic chip 020, avoiding assembly interference and stress concentration, but also contains the overflow of reinforcing adhesive, preventing it from intruding into the optical coupling area and contaminating the optical adhesive or the end face of the optical fiber 042, significantly improving manufacturing yield and long-term operational stability.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A silicon photonics engine, characterized in that, It includes a carrier board (010), a silicon photonics chip (020), a driver chip (030), and a fiber array (040). The carrier board (010) has a first side (013) and a second side (014) facing away from each other. The first side (013) is provided with a quick connector (011) for connecting to a plug on the motherboard. The silicon photonics chip (020) and the driving chip (030) are both disposed on the second surface (014), and the driving chip (030) and the silicon photonics chip (020) are both coupled to the quick connector (011). The driving chip (030) and the silicon photonics chip (020) are coupled. The fiber array (040) is coupled to the light-emitting end face of the silicon photonic chip (020).

2. The silicon photonics engine according to claim 1, characterized in that, The carrier plate (010) is provided with a clearance window (012) that penetrates the first surface (013) and the second surface (014). The silicon photonics chip (020) partially covers the avoidance window (012); A portion of the fiber array (040) is located within the avoidance window (012).

3. The silicon photonics engine according to claim 2, characterized in that, The fiber array (040) includes a glass block (041), an optical fiber (042), a glass cover plate (043), and an adhesive pad (044). The glass block (041) and the glass cover plate (043) together clamp the optical fiber (042), and the glass block (041) and the glass cover plate (043) are bonded together; The light-inlet end of the optical fiber (042) is coupled to the silicon photonic chip (020); Both the glass block (041) and the glass cover plate (043) are bonded to the light-emitting end face of the silicon photonic chip (020); The adhesive pad (044) is located inside the clearance window (012), and a portion of the adhesive pad (044) is bonded to the glass cover plate (043), while the other portion is bonded to the side of the silicon photonic chip (020) facing the clearance window (012).

4. The silicon photonics engine according to claim 3, characterized in that, A preset gap is left between the outer peripheral wall of the adhesive pad (044) and the inner peripheral wall of the clearance window (012).

5. The silicon photonics engine according to claim 4, characterized in that, The preset gap is greater than or equal to 1 mm.

6. The silicon photonics engine according to claim 3, characterized in that, The glass cover plate (043) is partially recessed into the clearance window (012); The adhesive pad (044) has a first adhesive surface (046) and a second adhesive surface (047). The first adhesive surface (046) is bonded to the glass cover plate (043). The second adhesive surface (047) protrudes relative to the first adhesive surface (046) and is closer to the glass block (041). The second adhesive surface (047) is bonded to the silicon photonic chip (020).

7. The silicon photonics engine according to claim 6, characterized in that, The first adhesive surface (046) protrudes from the edge of the glass cover plate (043) along the length direction of the optical fiber (042); An avoidance groove (048) is formed between the first adhesive surface (046) and the silicon photonic chip (020).

8. The silicon photonics engine according to claim 7, characterized in that, The clearance groove (048) has a groove width dimension greater than or equal to 0.5 mm in the length direction of the optical fiber (042).

9. The silicon photonics engine according to claim 3, characterized in that, The fiber array (040) also includes a multi-core fiber connector (045), which is connected to the light-emitting end of the fiber (042).

10. A co-packaged optical system, characterized in that, Includes a motherboard and a silicon photonics engine as described in any one of claims 1-9, wherein the motherboard has a plug and the quick-connect connector (011) is plugged into the plug.

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