A data acquisition device and system based on optical signal synchronization

Abstract

The utility model discloses a kind of data acquisition equipment and system based on optical signal synchronization, including multiple signal chains, analog-digital converter, clock signal generator, FPGA, optical module, microcontroller, communication module, wherein, multiple signal chains are connected with analog-digital converter, analog-digital converter is connected with FPGA, FPGA is connected with communication module by microcontroller, clock signal generator, optical module are connected with FPGA;Optical module has fiber interface for external optical fiber;The working mode of the optical module includes host computer working mode and slave machine working mode.The utility model utilizes the advantages that optical signal transmission loss is small, is not affected by electromagnetic interference, transmission speed is faster compared with electric signal, and realizes the high-precision synchronous sampling between multiple data acquisition equipment of long-distance deployment.

Description

Technical Field

[0001] This utility model relates to the field of structural safety monitoring technology, and in particular to a data acquisition device and system based on optical signal synchronization. Background Technology

[0002] Currently, in the field of structural safety monitoring technology, the monitoring of dynamic physical quantities often employs synchronous data acquisition instruments. This means that the channels within the acquisition instrument sample synchronously to ensure that the monitored data is captured at the same moment. Because the structural response (such as vibration, strain, and displacement) is a dynamic process, the data from each measuring point are highly correlated over time. For example, the vibration waves generated by an impact event (such as an earthquake, vehicle passage, or strong wind) will arrive at different locations on the structure sequentially. Synchronous acquisition ensures that all sensors record the structural state at the same moment, which is crucial for analyzing event propagation paths, identifying mode shapes, and calculating phase differences. When the number of locations to be monitored on a structure exceeds the number of channels in a single data acquisition instrument, synchronization technology between multiple data acquisition instruments is required to meet the synchronous monitoring needs of more sensors.

[0003] Currently, the synchronization technologies between multiple data acquisition devices mainly include synchronization triggering based on GPS second pulse signals and synchronization clocks based on electrical signals. These technologies have the following problems: The main problems with existing technologies are: 1. Synchronization triggering method based on GPS second pulse signal: Synchronization cannot be achieved indoors or in tunnels where there is no GPS signal, thus limiting its application in scenarios without GPS signal. To solve this limitation, the GPS feeder length needs to be increased, and the antenna needs to be installed in a location with GPS signal, increasing feeder and usage costs. In addition, GPS signals are susceptible to environmental factors such as weather, ionospheric disturbances, and solar storms.

[0004] 2. Synchronization clock method based on electrical signals: The distance is limited, and the synchronization distance is generally only tens of meters. At the same time, the signal is susceptible to electromagnetic interference. Utility Model Content

[0005] The purpose of this invention is to address the shortcomings of the prior art by providing a data acquisition device and system based on optical signal synchronization, thereby solving at least one of the problems of the prior art.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows: A data acquisition device based on optical signal synchronization is characterized by comprising multiple signal chains, an analog-to-digital converter (ADC), a clock signal generator, an FPGA, an optical module, a microcontroller, and a communication module. The multiple signal chains are all connected to the ADC, which is connected to the FPGA. The FPGA is connected to the communication module via the microcontroller. The clock signal generator and the optical module are both connected to the FPGA. The optical module has an optical fiber interface for connecting to an external optical fiber. The optical module operates in both a host mode and a slave mode.

[0007] In a preferred embodiment, the signal chain includes a signal amplifier, an anti-aliasing filter, a level converter, and an analog-to-digital converter driver connected in sequence; the signal amplifier is used to receive sensor measurement signals, and the analog-to-digital converter driver is connected to the analog-to-digital converter.

[0008] As a preferred embodiment, the analog-to-digital converter is an analog-to-digital converter employing multiple independent cores, with each independent core corresponding to a signal chain of one channel.

[0009] As another preferred embodiment, the analog-to-digital converter is a multi-channel analog-to-digital converter with multiple sample-and-hold circuits. The analog-to-digital converter includes a shared high-speed analog-to-digital converter core. Each analog input channel of the analog-to-digital converter is equipped with a sample-and-hold circuit at the front end. At the sampling time, the sample-and-hold circuits of each channel are sequentially connected to the shared high-speed analog-to-digital converter core through a high-speed multiplexer.

[0010] As a preferred embodiment, the clock signal generator is a crystal oscillator.

[0011] As a preferred embodiment, the communication module is a wired communication module or a wireless communication module.

[0012] Based on the same inventive concept, this utility model also provides a data acquisition system based on optical signal synchronization. Its structural feature is that it includes multiple data acquisition devices, the optical modules of the multiple data acquisition devices are interconnected through optical fibers, the microprocessor of each data acquisition device receives working mode instructions through a communication module, and at the same time, the microprocessor of each data acquisition device sets the corresponding optical module to master working mode or slave working mode through FPGA based on the working mode instructions.

[0013] As a preferred approach, the optical modules of multiple data acquisition devices form a bus-type multi-level network. The first-level optical module operates in host mode, while the optical modules of the remaining levels operate in slave mode.

[0014] As another preferred approach, the optical modules of multiple data acquisition devices are arranged in a star network, with each optical module operating in slave mode.

[0015] In a preferred embodiment, the clock signal generator provides a reference synchronization clock signal to the FPGA, and the FPGA generates the operating frequency required by the analog-to-digital converter for the sampling rate. The optical module in master mode sends the corresponding operating frequency to the next-level optical module in slave mode. After receiving the optical signal containing the operating frequency, the optical module in slave mode converts the optical signal into an electrical signal and sends it to the corresponding FPGA for sampling. At the same time, it converts the synchronization clock electrical signal into a synchronization clock optical signal and continues to transmit it to the next-level optical module in slave mode.

[0016] Compared with existing technologies, this invention utilizes the advantages of optical signal transmission, such as low transmission loss, immunity to electromagnetic interference, and faster transmission speed compared to electrical signals, to achieve high-precision synchronous sampling between multiple data acquisition devices deployed over long distances. Attached Figure Description

[0017] Figure 1 This is a system block diagram of an embodiment of the data acquisition device based on optical signal synchronization according to this utility model.

[0018] Figure 2 for Figure 1 A schematic diagram of the circuit structure of an embodiment of the optical module.

[0019] Figure 3 This is a system block diagram of an embodiment of the data acquisition system based on optical signal synchronization of this utility model.

[0020] In this array, 1 is the signal chain, 2 is the analog-to-digital converter, 3 is the clock signal generator, 4 is the FPGA, 5 is the optical module, 51 is the host optical module, 52 is the slave optical module, 6 is the microcontroller, 7 is the communication module, and 8 is the optical fiber. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort should fall within the protection scope of the present invention.

[0022] like Figure 1As shown, the first aspect of this utility model provides a data acquisition device based on optical signal synchronization, including multiple signal chains 1, an analog-to-digital converter 2, a clock signal generator 3, an FPGA 4, an optical module 5, a microcontroller 6, and a communication module 7. The multiple signal chains 1 are all connected to the analog-to-digital converter 2, the analog-to-digital converter 2 is connected to the FPGA 4, the FPGA 4 is connected to the communication module 7 via the microcontroller 6, and the clock signal generator 3 and the optical module 5 are both connected to the FPGA 4. The optical module 5 has an optical fiber interface for connecting to an external optical fiber 8. The optical module 5 has two operating modes: a host operating mode and a slave operating mode.

[0023] The signal chain 1 includes a signal amplifier, an anti-aliasing filter, a level converter, and an analog-to-digital converter driver connected in sequence; the signal amplifier is used to receive sensor measurement signals, and the analog-to-digital converter driver is connected to the analog-to-digital converter 2.

[0024] In some preferred embodiments, the analog-to-digital converter 2 is an analog-to-digital converter 2 employing multiple independent cores, each independent core corresponding to a signal chain 1 for one channel. In other preferred embodiments, the analog-to-digital converter 2 is a multiplexed analog-to-digital converter 2 equipped with multiple sample-and-hold circuits, the analog-to-digital converter 2 including a shared high-speed analog-to-digital converter core; each analog input channel of the analog-to-digital converter 2 is equipped with a sample-and-hold circuit at the front end, and at the sampling time, the sample-and-hold circuits of each channel are sequentially connected to the shared high-speed analog-to-digital converter core through a high-speed multiplexer.

[0025] The clock signal generator 3 is preferably, but not limited to, a crystal oscillator.

[0026] The communication module 7 is either a wired communication module or a wireless communication module.

[0027] A circuit structure diagram of one embodiment of the optical module 5 is shown below. Figure 2 As shown.

[0028] like Figure 3 As shown, the second aspect of this utility model provides a data acquisition system based on optical signal synchronization, which includes multiple data acquisition devices. The optical modules 5 of the multiple data acquisition devices are interconnected through optical fibers 8. The microprocessor of each data acquisition device receives working mode instructions through a communication module 7. At the same time, the microprocessor of each data acquisition device sets the corresponding optical module 5 to master working mode or slave working mode through FPGA4 based on the working mode instructions. Figure 3 In this system, the optical modules 5 of multiple data acquisition devices form a bus-type multi-level network. The first-level optical module 5 operates in host mode, while the optical modules 5 of the remaining levels operate in slave mode. Figure 3The diagram is for simplification. In the data acquisition device where the optical module 5 is located in slave working mode, other functional modules are not shown except for the optical module 5, but this does not affect the understanding and implementation of this utility model by those skilled in the art.

[0029] In addition to bus-type multi-level networks, optical modules 5 of multiple data acquisition devices can also form a star network, with each optical module 5 operating in slave mode.

[0030] The clock signal generator 3 is used to provide a reference synchronization clock signal to the FPGA4. The FPGA4 generates the operating frequency required by the analog-to-digital converter 2 for the sampling rate. The optical module 5 in master mode sends the corresponding operating frequency to the next-level optical module 5 in slave mode. After receiving the optical signal containing the operating frequency, the optical module 5 in slave mode converts the optical signal into an electrical signal and sends it to the corresponding FPGA4 for sampling. At the same time, it converts the synchronization clock electrical signal into a synchronization clock optical signal and continues to transmit it to the next-level optical module 5 in slave mode.

[0031] The detailed descriptions of each functional unit are as follows: Signal chain 1: The signal conditioning circuit of the optical signal synchronization-based data acquisition device of this invention generally includes signal amplification, anti-aliasing filter, level conversion, analog-to-digital converter driver, etc. Signal chain 1 can measure various electrical parameters, such as voltage signals, current signals, IEPE signals, bridge signals, etc., the difference lying in the signal conditioning circuit at the front end of signal chain 1. Because strict synchronous sampling is required between channels of a single synchronous data acquisition device, each channel uses an independent signal chain 1 design to ensure the highest synchronization performance, which increases the corresponding cost and power consumption.

[0032] The signal chain 1 is designed based on the functional requirements of the acquisition equipment, such as the type of signal to be measured, signal bandwidth, signal amplitude, and signal accuracy. For example, if a voltage signal sensor is commonly used, the first stage of the signal chain 1 can use a programmable amplifier or instrumentation amplifier as the gain configuration for the original signal. The power rail of the signal chain 1 is selected according to the signal measurement range, typically ±10V, to ensure compatibility with most voltage signal sensors. Based on the sampling rate, the maximum bandwidth that the equipment can measure can be determined, and an anti-aliasing filter is designed based on this maximum bandwidth. Generally, a multi-order active filter is used for anti-aliasing. To ensure passband flatness, Butterworth low-pass filters are often selected, and the circuit topology uses an SK type.

[0033] Analog-to-digital converter 2: For multi-channel synchronous data acquisition devices, multiple independent-core analog-to-digital converters (ADCs) are used, with each independent core corresponding to a signal chain 1 for one channel, achieving true synchronous sampling across multiple channels. For less demanding scenarios, a multi-channel ADC with sample-and-hold circuits (SPCs) can also be used for synchronous sampling, employing a shared high-speed ADC core. Each analog input channel is equipped with a SPC at its front end. During sampling, a high-speed multiplexer sequentially and rapidly connects the SPCs of each channel to the shared ADC core for conversion; however, its synchronization performance will be lower than that of a multi-core ADC.

[0034] The bit depth of analog-to-digital converter 2 (ADC 2) is determined based on the dynamic measurement range of the synchronous acquisition device. For example, if a dynamic range of over 100dB is required, a 24-bit ADC 2 is needed. Simultaneously, the output of signal chain 1 must match the input signal range requirements of ADC 2. Since synchronous sampling is required between channels, a multi-conversion-core ADC 2 is necessary.

[0035] Clock signal generator 3: Clock signal generator 3 is preferably a crystal oscillator, used to provide FPGA4 with a highly stable, low-jitter clock signal for frequency calculation, which is crucial for ensuring the conversion accuracy and signal-to-noise ratio (SNR) of analog-to-digital converter 2. This clock signal is divided, multiplied, phase-shifted, de-jittered, and clock skew eliminated through the FPGA4's internal DCM (Digital Clock Management Module). It achieves high-precision clock control through components such as a delay-locked loop (DLL) and a digital frequency synthesizer (DFS), generating clock signals of different frequencies and phases, and supporting dynamic reconfiguration to meet real-time adjustment needs. For example, different sampling rates can set different division coefficients to provide different conversion clock frequencies to analog-to-digital converter 2.

[0036] The crystal oscillator primarily provides an accurate conversion clock for the analog-to-digital converter 2 (ADC2), and also serves as a synchronous clock signal transmitted to the data acquisition device in slave mode. Therefore, the crystal oscillator requires stable frequency. Generally, a temperature-compensated crystal oscillator (TCXO) is used, with a temperature coefficient of ±0.1~2.5 ppm / °C, to ensure consistent sampling rate across the entire temperature range. At the same time, the frequency of the crystal oscillator needs to meet the sampling frequency requirements of the ADC2.

[0037] FPGA4: It has five main functions: ① The internal DCM divides and multiplies the original clock frequency of the crystal oscillator to achieve conversion frequencies corresponding to different sampling rates, providing them to the analog-to-digital converter 2; ② Simultaneously, this conversion frequency (synchronization clock signal) drives the host optical module 51 to convert electrical signals into optical signals, which are then transmitted through optical fiber 8, providing accurate synchronization clock signals to other sub-devices; the FPGA4 of the slave device directly receives the synchronization clock signal converted from the optical module and transmits it directly to the analog-to-digital converter 2; ③ It performs logic and timing control on the analog-to-digital converter 2, realizing functions such as parameter configuration and data reading; ④ It buffers the data read from the analog-to-digital converter; ⑤ It interacts with the microcontroller 6. Synchronous sampling can also be achieved between the host and slave devices by sending a synchronization trigger signal, or all synchronization devices can act as slave devices, using a dedicated external trigger source or synchronization clock as an independent signal source to form a star network, providing a reference signal for all acquisition devices.

[0038] In synchronous clock control, the main function of FPGA4 is to perform mathematical operations on the original clock frequency of the crystal oscillator. Through frequency multiplication and division, the required frequencies for different sampling rates are obtained. This can be achieved using the DCM module inside FPGA4. For example, with an external crystal oscillator of 20.48MHz, two DCM modules inside FPGA4 can generate a clock of 33.554432MHz. This clock can achieve sampling rates that are powers of 2, such as 128sps, 256sps, and 2048sps. DCM1: 20.48MHz * 32 / 25 = 26.2144MHz DCM2: 26.2144MHz * 32 / 25 = 33.554432MHz The crystal oscillator provides a stable reference synchronization clock signal to the FGPA. The FGPA generates the operating frequency required by the analog-to-digital converter 2 corresponding to the sampling rate through its internal DCM, and samples the sensor data conditioned by the signal chain 1.

[0039] Microcontroller 6: Its main functions include: ① reading the sampling data buffer inside FPGA4; ② processing the raw sampling data using a custom algorithm and packaging it into a protocol, and then transmitting it to the APP or cloud platform through the communication module 7; ③ receiving acquisition configuration instructions, working mode instructions, etc. sent by the APP or cloud platform through the communication module 7; ④ configuring the initial parameters and working parameters of FPGA4.

[0040] The selection of microcontroller 6 only needs to meet the sampling rate and channel requirements of the data acquisition device. That is, the processing speed of microcontroller 6 can meet the requirements of data transmission bandwidth and algorithm, and at the same time meet the requirements of data interaction with external communication module 7. Generally, microcontroller 6 with Cortex-M4 or Cortex-M7 architecture is selected.

[0041] The crystal oscillator provides a stable reference synchronization clock signal to the FGPA. The FGPA generates the operating frequency required by the analog-to-digital converter 2 corresponding to the sampling rate through its internal DCM. The host computer APP or remote cloud platform configures the data acquisition device as a master or slave through the communication module 7. The master transmits the operating frequency to the slave optical module 52 (i.e., the optical module 5 operating in master mode) through the optical fiber 8 of the master optical module 51 (i.e., the optical module 5 operating in master mode). The slave receives the optical signal sent by the master to synchronize the clock, realizing master-slave synchronous sampling of multiple data acquisition devices.

[0042] Communication Module 7: As a channel for transmitting data in a synchronous data acquisition system, wired methods such as Ethernet, USB, and RS485 interfaces can be used, or wireless methods such as cellular mobile communication modules and WIFI modules can be used to transmit the data collected by the synchronous data acquisition system to local software or a remote cloud platform. Depending on the operating mode of the data acquisition equipment, a 100 Mbps Ethernet interface can be selected to implement a continuous data acquisition instrument, or a 4G module can be used to achieve a remote cloud mode, enabling timed or triggered acquisition.

[0043] The microcontroller 6 receives instructions from the host computer APP or remote cloud platform through the communication module 7, configures the FGPA to realize the logic control of the analog-to-digital converter 2 and the working mode of the device, and determines whether the sampling clock of the device is from the local crystal oscillator or the synchronous clock signal sent by the host, depending on whether the device is a master or a slave.

[0044] Fiber optic 8: As a medium for transmitting synchronous clock optical signals, its advantages, such as low transmission loss, immunity to electromagnetic interference, and stable signal transmission, are mainly considered. It can transmit MHz-level synchronous clock signals over long distances (at least tens of kilometers). A 1310nm wavelength single-mode optical fiber is used, with a loss of approximately 0.2 dB / km. In practical engineering applications, attention should be paid to the protection of fiber 8 and ensuring that its radius of curvature meets requirements. The interface can be an SC / FC / ST socket type optical interface, depending on the selected optical module 5.

[0045] Host optical module 51 (i.e., optical module 5 operating in host mode): The transceiver integrated optical module is used. Its main function is to convert the synchronous clock electrical signal sent by FPGA4 into a synchronous clock optical signal for long-distance, low-loss transmission and to provide the synchronous clock signal to the next-level slave optical module 52.

[0046] Slave optical module 52 (i.e., optical module 5 operating in slave mode): Similar to the host optical module 51, it adopts a transceiver integrated optical module to receive the synchronous clock optical signal transmitted from the host optical module 51, convert the optical signal into an electrical signal, and use it for sampling after being received by the internal FPGA4. At the same time, the synchronous clock electrical signal is converted into a synchronous clock optical signal by the slave optical module 52 and then transmitted to the next level slave synchronous data acquisition device.

[0047] Whether the data acquisition device operates as a host or slave device is determined by the configuration of the host computer software (APP). In other words, the host and slave devices are defined by software, but their hardware is exactly the same.

[0048] See circuit Figure 2 The optical module 5 adopts a transceiver integrated optical module U1, which can be a 1*9 interface optical module or an SFP interface optical module (for high-speed transmission scenarios). This utility model adopts a 1*9 interface optical module.

[0049] When receiving signals, the optical signal is converted into an electrical signal output after passing through the internal photodetector, transimpedance amplifier, and signal shaping of U1. The electrical signal is a digital PECL (Positive Voltage Emitter Coupled Logic) signal (a TTL level optical module can also be used, selected according to the synchronization clock rate; generally, TTL is tens of MHz, while PECL can reach hundreds of MHz). The PECL level is converted into a TTL level by U2 and then transmitted to FPGA4. U2 is a PECL driver and transceiver, realizing the conversion between PECL and TTL levels. When sending the synchronization clock signal, FPGA4 sends it to U2 through the TTL signal pin. U2 converts the TTL signal into a PECL signal and then transmits it to the optical module U1. The PECL electrical signal passes through the internal driving circuit of U1 and the laser diode LD, converting the PECL electrical signal into a 1310nm optical signal, and then is transmitted to the next-level data acquisition device through fiber optic cable 8. The optical modular design can adopt SC / FC / ST socket-type optical interfaces, single-mode optical transceiver integrated module, with a working wavelength of 1310nm, a transmission rate of 155Mb / s, and a transmission distance of about 40km when the output optical power is -10dBm, which fully meets the needs of structural safety monitoring.

[0050] The entire synchronous clock signal transmission and operating logic is as follows: ① A data acquisition device needs to be set as the host M. The reference clock signal is generated by its internal crystal oscillator and FPGA4. FPGA4 transmits the signal through... Figure 2The circuit converts the electrical signal synchronization clock into an optical signal synchronization clock; ② The optical signal synchronization clock output by the host is transmitted along the optical fiber 8 to the optical module of the first slave A, and the optical signal is converted into an electrical signal and transmitted to the FPGA4 of slave A. On the one hand, the FPGA4 inside slave A provides the synchronization clock signal to the analog-to-digital converter 2 for signal conversion, and at the same time, the synchronization signal is sent to the next slave B through the optical module of slave A, and so on, to realize the bus-type optical signal synchronization clock transmission.

[0051] In a bus-type data acquisition system, only one master can exist within the same synchronous clock network. Slave devices do not generate their own clocks; their operating clock signals are obtained from the master. In this mode, only the master listens for the start sampling command; the slave's sampling has already begun at this point, and it will start switching samples as soon as the synchronous clock from the master arrives.

[0052] In practical applications, a dedicated synchronous trigger can be used as the trigger source signal for all synchronous data acquisition devices. A star network can be formed through 8 optical fibers to achieve synchronous triggering and sampling among multiple devices. Alternatively, a dedicated synchronous clock generator can be used to provide a synchronous clock signal for all devices.

[0053] This invention replaces electrical signals with optical signals, solving the problem of simultaneous sampling by multiple data acquisition devices in scenarios where GPS signals are unavailable or the synchronization distance exceeds that of an electrical signal synchronization clock, such as tunnels, internal structures of water conservancy dams, and inside bridge box girders. At the same time, the synchronization clock signal has high transmission efficiency and reliability, and the transmission distance fully meets the requirements for online safety monitoring of large structures.

[0054] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application.

[0055] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0056] The embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0057] The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0058] In addition, in the various embodiments of this utility model, each functional unit can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0059] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. A data acquisition device based on optical signal synchronization, characterized in that, include: Multiple signal chains (1), analog-to-digital converter (2), clock signal generator (3), FPGA (4), optical module (5), microcontroller (6), and communication module (7), among which, Multiple signal chains (1) are connected to analog-to-digital converter (2), analog-to-digital converter (2) is connected to FPGA (4), FPGA (4) is connected to communication module (7) through microcontroller (6), clock signal generator (3) and optical module (5) are connected to FPGA (4); optical module (5) has an optical fiber interface for connecting to external optical fiber (8); the working mode of optical module (5) includes host working mode and slave working mode.

2. The data acquisition device based on optical signal synchronization according to claim 1, characterized in that, The signal chain (1) includes a signal amplifier, an anti-aliasing filter, a level converter, and an analog-to-digital converter driver connected in sequence; the signal amplifier is used to receive sensor measurement signals, and the analog-to-digital converter driver is connected to the analog-to-digital converter (2).

3. The data acquisition device based on optical signal synchronization according to claim 1, characterized in that, The analog-to-digital converter (2) is an analog-to-digital converter (2) with multiple independent cores, each independent core corresponding to a channel signal chain (1).

4. The data acquisition device based on optical signal synchronization according to claim 1, characterized in that, The analog-to-digital converter (2) is a multi-channel analog-to-digital converter with multiple sample-and-hold circuits, and the analog-to-digital converter (2) includes a shared high-speed analog-to-digital converter core; Each analog input channel of the analog-to-digital converter (2) is equipped with a sample-and-hold circuit at the front end. At the sampling time, the sample-and-hold circuits of each channel are connected to the shared high-speed analog-to-digital converter core in sequence through a high-speed multiplexer.

5. The data acquisition device based on optical signal synchronization according to claim 1, characterized in that, The clock signal generator (3) is a crystal oscillator.

6. The data acquisition device based on optical signal synchronization according to claim 1, characterized in that, The communication module (7) is a wired communication module or a wireless communication module.

7. A data acquisition system based on optical signal synchronization, characterized in that, The device includes multiple data acquisition devices as described in any one of claims 1-6. The optical modules (5) of the multiple data acquisition devices are interconnected through optical fibers (8). The microprocessor of each data acquisition device receives working mode instructions through a communication module (7). At the same time, the microprocessor of each data acquisition device sets the corresponding optical module (5) to host working mode or slave working mode through an FPGA (4) based on the working mode instructions.

8. The data acquisition system based on optical signal synchronization according to claim 7, characterized in that, The optical modules (5) of multiple data acquisition devices form a bus-type multi-level network. The working mode of the first-level optical module (5) is the host working mode, and the working mode of the other optical modules (5) is the slave working mode.

9. The data acquisition system based on optical signal synchronization according to claim 7, characterized in that, The optical modules (5) of multiple data acquisition devices form a star network, and the working mode of each optical module (5) is slave mode.

10. The data acquisition system based on optical signal synchronization according to claim 8, characterized in that, The clock signal generator is used to provide a reference synchronous clock signal to the FPGA (4). The FPGA (4) generates the operating frequency required for the sampling rate of the analog-to-digital converter. The optical module (5) in the host working mode sends the corresponding operating frequency to the next-level optical module (5) in the slave working mode. After receiving the optical signal containing the operating frequency, the optical module (5) in the slave working mode converts the optical signal into an electrical signal and sends it to the corresponding FPGA (4) for sampling. At the same time, it converts the synchronous clock electrical signal into a synchronous clock optical signal and continues to transmit it to the next-level optical module (5) in the slave working mode.

Images