A computing power device

Abstract

The utility model discloses a kind of computing power device, the utility model embodiment SOM is connected by motherboard expansion: storage circuit, interface chip and logic IC circuit and peripheral chip circuit, for simultaneously compatible multiple types of communication systems, adaptation camera, radar, host computer and the like Equipment provides foundation;Through the power distribution circuit of motherboard, the power supply of the computing power of access is handled, and the adaptation power supply for the expansion circuit connected based on motherboard is provided;Through power-on timing control circuit, the connection order based on enable driving circuit and the power-on interval generated by timing control IC circuit, in turn, power-on control is carried out to corresponding power supply branch, and the safe and stable operation of power supply circuit is ensured.

Description

Technical Field

[0001] This utility model relates to intelligent transportation technology, and more specifically, to a computing power device. Background Technology

[0002] Currently, intelligent transportation (especially in the highway sector) is accelerating the construction of edge intelligent control. As the core carrier of vehicle-road collaboration and intelligent monitoring, roadside edge devices need to meet core requirements such as high-performance data processing (e.g., multi-channel high-definition video analysis, AI inference), access to multiple types of devices (cameras, radar, etc.), wide environmental adaptability (high and low temperatures, vibration and shock), and high-reliability communication. According to industry standards such as "General Technical Requirements and Testing Methods for Highway Electromechanical System Equipment" and "Tunnel Programmable Controllers", roadside edge devices must have hard indicators such as "CPU ≥ 8 cores, GPU computing power ≥ 250 TOPS, memory ≥ 32GB, storage ≥ 12TB, support for ≥ 24 channels of 1080P camera access, 5G communication and GNSS timing (accuracy < 10ms)".

[0003] Similar products in the market suffer from the following key shortcomings, making them unsuitable for the needs of roadside edge devices: 1. Significant computing power bottleneck: Using ordinary industrial-grade CPUs, AI computing power is only at the "tens of TOPS" level, which cannot meet the real-time analysis and AI inference requirements of more than 24 channels of high-definition video; 2. Poor interface scalability: Difficult to simultaneously support multiple types of interfaces such as 5G, Gigabit Ethernet, CAN, and RS485, making it unsuitable for scenarios involving multiple devices such as cameras, radar, and host computers; weak environmental adaptability with a narrow operating temperature range (mostly 0℃~50℃), insufficient vibration and shock protection, and EMC protection capabilities, making it unsuitable for complex environments such as highways and tunnels; 3. Unbalanced storage solutions: Relying solely on SSDs (too expensive) or HDDs (slow read / write speeds), failing to meet the dual requirements of "high-speed local caching" and "large-capacity data storage"; 4. Inadequate reliability design: Inadequate power protection, reset mechanisms, and heat dissipation systems, making the devices prone to failure due to voltage fluctuations, high temperatures, and system crashes.

[0004] Designing a roadside edge device that meets application requirements has become an unsolved problem. Utility Model Content

[0005] This utility model embodiment provides a computing power device, including: a motherboard 1, which includes a system-level module SOM1-1, a power module 1-2, and a power-on timing control circuit 1-3. The SOM1-1 is connected through the motherboard 1 to: a storage circuit 1-1-1, an interface chip and logic IC circuit 1-1-2, and a peripheral chip circuit 1-1-3; wherein... Power module 1-2 includes a motherboard power distribution circuit 1-2-1, which includes the following power supply branches: a first power supply circuit 1-2-1-1, a second power supply circuit 1-2-1-2, a third power supply circuit 1-2-1-3, and a fourth power supply circuit 1-2-1-4 connected to the computing power supply, and a fifth power supply circuit 1-2-1-5 connected to the fourth power supply circuit 1-2-1-4; wherein, The first power supply circuit 1-2-1-1 is configured to convert the computing power power supply into a first power supply with a first voltage and a first current, and provide power for the first power consumption of SOM1-1; The second power supply circuit 1-2-1-2 is configured to convert the computing power power supply into a second power supply with a second voltage and a second current to power the storage circuit 1-1-1. The third power supply circuit 1-2-1-3 is configured to convert the computing power supply into a third power supply with a third voltage and a third current, providing power for the second power consumption of SOM1-1; The fourth power supply circuit 1-2-1-4 is configured to convert the computing power power supply into a fourth voltage and a fourth current to power the interface chip and logic IC circuit 1-1-2. The fifth power supply circuit 1-2-1-5 includes: a switching branch 1-2-1-5-1, a parallel first power supply branch 1-2-1-5-2, and a second power supply branch 1-2-1-5-3; wherein, The conversion branch 1-2-1-5-1 is configured to convert the fourth power supply to a fifth power supply with a fifth voltage and a fifth current. The first power supply branch 1-2-1-5-2 is configured to transform the fifth voltage of the fifth power supply to power two or more first peripheral chips with different power supply voltages connected in parallel in the peripheral chip circuit 1-1-3. The second power supply branch 1-2-1-5-3 is configured to supply power to two or more second peripheral chips connected in parallel in peripheral chip circuit 1-1-3 based on the fifth power supply. The power-on timing control circuit 1-3 includes: a power distribution drive circuit 1-3-1 and a timing control IC circuit 1-3-2 connected in series. The timing control IC circuit 1-3-2 for the power-on interval is connected to each power supply branch; wherein, The power distribution drive circuit 1-3-1 is configured to: when the motherboard power distribution circuit 1-2-1 is connected to power supply, drive the motherboard power distribution circuit 1-2-1 to power on and output the first enable signal to the timing control IC circuit 1-3-2. The timing control IC circuit 1-3-2 is configured to: upon receiving the first enable signal, output power-on drive signals to the power supply branch in the following power-on sequence to control the power supply branch to power on: the third power supply circuit 1-2-1-3, the first power supply circuit 1-2-1-1, the fourth power supply circuit 1-2-1-4, and other power supply circuits that are powered on synchronously. The other power supply circuits that are powered on synchronously include: the second power supply circuit 1-2-1-2 and the fifth power supply circuit 1-2-1-5.

[0006] This utility model embodiment of SOM expands the connection of storage circuits, interface chips, logic IC circuits, and peripheral chip circuits through the motherboard, providing a foundation for simultaneous compatibility with multiple types of communication systems and adaptation to devices such as cameras, radars, and host computers; the motherboard power distribution circuit processes the connected computing power supply, providing an adapted power supply for the expansion circuits connected to the motherboard; the power-on timing control circuit controls the power-on of the corresponding power supply branches in sequence based on the connection order of the enable drive circuit and the power-on interval generated by the timing control IC circuit, ensuring the safe and stable operation of the power supply circuit.

[0007] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0008] The accompanying drawings are provided to further illustrate the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solution of this utility model and do not constitute a limitation on the technical solution of this utility model.

[0009] Figure 1 This is a structural block diagram of the computing power device of this utility model; Figure 2 This is a schematic diagram of the circuit board composition of the computing device according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit composition of the power module in an embodiment of this utility model; Figure 4 This is a schematic diagram of the timing control IC circuit according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the backplate mounting structure of the computing device according to an embodiment of the present utility model; Figure 6 This is a schematic diagram of the ear-type mounting structure of the computing device according to an embodiment of the present utility model; Figure 7 This is a schematic diagram of the panel layout of the computing device in an embodiment of this utility model. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0011] Figure 1 This is a structural block diagram of the computing power device of this utility model, as shown below. Figure 1 As shown, it includes: a motherboard 1, which includes a system-level module SOM1-1, a power module 1-2, and a power-on timing control circuit 1-3. SOM1-1 is connected to: a storage circuit 1-1-1, an interface chip and logic IC circuit 1-1-2, and a peripheral chip circuit 1-1-3 via the motherboard 1; wherein, Power module 1-2 includes a motherboard power distribution circuit 1-2-1, which includes the following power supply branches: a first power supply circuit 1-2-1-1, a second power supply circuit 1-2-1-2, a third power supply circuit 1-2-1-3, and a fourth power supply circuit 1-2-1-4 connected to the computing power supply, and a fifth power supply circuit 1-2-1-5 connected to the fourth power supply circuit 1-2-1-4; wherein, The first power supply circuit 1-2-1-1 is configured to convert the computing power power supply into a first power supply with a first voltage and a first current, and provide power for the first power consumption of SOM1-1; The second power supply circuit 1-2-1-2 is configured to convert the computing power power supply into a second power supply with a second voltage and a second current to power the storage circuit 1-1-1. The third power supply circuit 1-2-1-3 is configured to convert the computing power supply into a third power supply with a third voltage and a third current, providing power for the second power consumption of SOM1-1; The fourth power supply circuit 1-2-1-4 is configured to convert the computing power power supply into a fourth voltage and a fourth current to power the interface chip and logic IC circuit 1-1-2. The fifth power supply circuit 1-2-1-5 includes: a switching branch 1-2-1-5-1, a parallel first power supply branch 1-2-1-5-2, and a second power supply branch 1-2-1-5-3; wherein, The conversion branch 1-2-1-5-1 is configured to convert the fourth power supply to a fifth power supply with a fifth voltage and a fifth current. The first power supply branch 1-2-1-5-2 is configured to transform the fifth voltage of the fifth power supply to power two or more first peripheral chips with different power supply voltages connected in parallel in the peripheral chip circuit 1-1-3. The second power supply branch 1-2-1-5-3 is configured to supply power to two or more second peripheral chips connected in parallel in peripheral chip circuit 1-1-3 based on the fifth power supply. The power-on timing control circuit 1-3 includes: a power distribution drive circuit 1-3-1 and a timing control IC circuit 1-3-2 connected in series. The timing control IC circuit 1-3-2 for the power-on interval is connected to each power supply branch; wherein, The power distribution drive circuit 1-3-1 is configured to: when the motherboard power distribution circuit 1-2-1 is connected to power supply, drive the motherboard power distribution circuit 1-2-1 to power on and output the first enable signal to the timing control IC circuit 1-3-2. The timing control IC circuit 1-3-2 is configured to: upon receiving the first enable signal, output power-on drive signals to the power supply branch in the following power-on sequence to control the power supply branch to power on: the third power supply circuit 1-2-1-3, the first power supply circuit 1-2-1-1, the fourth power supply circuit 1-2-1-4, and other power supply circuits that are powered on synchronously. The other power supply circuits that are powered on synchronously include: the second power supply circuit 1-2-1-2 and the fifth power supply circuit 1-2-1-5.

[0012] This utility model embodiment of SOM expands the connection of storage circuits, interface chips, logic IC circuits, and peripheral chip circuits through the motherboard, providing a foundation for simultaneous compatibility with multiple types of communication systems and adaptation to devices such as cameras, radars, and host computers; the motherboard power distribution circuit processes the connected computing power supply, providing an adapted power supply for the expansion circuits connected to the motherboard; the power-on timing control circuit controls the power-on of the corresponding power supply branches in sequence based on the connection order of the enable drive circuit and the power-on interval generated by the timing control IC circuit, ensuring the safe and stable operation of the power supply circuit.

[0013] In one exemplary instance, the second power consumption described in this embodiment of the present invention is less than the first power consumption.

[0014] In one exemplary instance, the motherboard 1 of this utility model embodiment is compatible with two or more system-level modules (SOMs).

[0015] When the motherboard of this utility model is compatible with two or more SOMs, the interfaces for connecting the two or more SOMs and the interface signals for transmitting are consistent. Figure 2This is a schematic diagram of the circuit board composition of the computing device according to an embodiment of the present invention. Apart from the different system-level modules, the interface connectors designed on the motherboard can accommodate two types of system-level modules, and the interface signals processed by the two system-level modules are completely identical. By setting a motherboard compatible with two or more different system-level modules (SOMs), a foundation is provided for flexible configuration of computing power for different scenarios; the SOM in this embodiment of the present invention includes the NVIDIA Jetson AGX series SOM. The motherboard is compatible with two SOMs: 275TOPS (ORIN module) and 30TOPS (XAVIER module). In this embodiment, the 275TOPS version uses a Jetson AGX Orin 64GB industrial-grade module (12-core A78AE CPU, 64GB LPDDR5 memory), and the 30TOPS version uses a Jetson AGX XAVIER Industrial-grade module (8-core Carmel CPU, 32GB LPDDR4X memory). It can be flexibly configured according to actual computing power requirements. Taking the 275 TOPS version as an example, the GPU computing power is more than 5 times higher than existing products, supporting 24 channels of 1080P camera data. It utilizes GPU / Tensor Cores to complete AI inference and video analysis, meeting the needs of high-density AI tasks such as vehicle-road collaboration and intelligent monitoring. By adapting to different computing power requirements with dual specifications of 275TOPS / 30TOPS, the motherboard circuit is compatible with both SOMs, reducing project customization costs. The key parameters of the 275TOPS and 30TOPS in this embodiment are shown in Table 1. Table 1 In this embodiment of the utility model, the SOM and the motherboard are connected by a 699-pin high-speed connector (8mm spacing). The height of the components below the module is ≤3.8mm (adapted to the SOM chassis height of 3.8~4.2mm), and it is fastened and supported by 4 M3 brackets (4.2mm in height).

[0016] In one exemplary embodiment, the SOM of this utility model is connected via several interface connectors on the motherboard: storage circuit, interface chip and logic IC circuit and peripheral chip circuit.

[0017] In one exemplary embodiment of the present invention, the motherboard power distribution circuit 1-2-1 further includes, in series, a reverse connection protection circuit 1-2-1-6 (e.g., a reverse connection protection circuit composed of a P-field-effect transistor and an eFUSE) and an electromagnetic interference (EMC) circuit 1-2-1-7; wherein, The reverse connection protection circuit 1-2-1-6 protects the connected computing power supply from reverse connection. EMC circuit 1-2-1-7 filters out interference from the computing power supply that passes through the reverse connection protection circuit.

[0018] In this embodiment of the utility model, the input terminal of the reverse connection protection circuit 1-2-1-6 is connected to the computing power supply, and the output terminal of the electromagnetic interference (EMC) circuit 1-2-1-7 is connected to the input terminals of the first power supply circuit 1-2-1-1, the second power supply circuit 1-2-1-2, the third power supply circuit 1-2-1-3, and the fourth power supply circuit 1-2-1-4.

[0019] In one exemplary embodiment, the present invention is as follows: The first power supply circuit 1-2-1-1 includes a first P-field-effect transistor and a first current limiting circuit; The second power supply circuit 1-2-1-2 includes a second P-field-effect transistor; The third power supply circuit 1-2-1-3 includes a third DC-DC step-down regulator (e.g., LTM4613), wherein the second power consumption is less than the first power consumption; The fourth power supply circuit 1-2-1-4 includes a fourth DC-DC step-down regulator (e.g., LTM4613). The reverse polarity protection circuit 1-2-1-6 includes a sixth P-field-effect transistor.

[0020] In one exemplary embodiment, the power module 1-2 of this utility model further includes a main power conversion circuit 1-2-2, configured to convert the external power supply into the aforementioned computing power supply. The main power conversion circuit 1-2-2 of this utility model may consist of a seventh P-field-effect transistor and a seventh current-limiting circuit.

[0021] In one exemplary embodiment, the storage circuit 1-1-1 of this utility model includes an HDD and a fan circuit, which is powered by a second power supply circuit 1-2-1-2.

[0022] In one exemplary embodiment, the present invention is as follows: When the first peripheral chip includes a DP, the circuit that supplies power to the DP in the first power supply branch 1-2-1-5-2 is connected in series with the first TSP (e.g., TSP25200). The second power supply branch 1-2-1-5-3 is configured to supply power to two or more second peripheral chips connected in parallel based on the fifth power supply. When the second peripheral chip includes CAN, the circuit that supplies power to CAN in the second power supply branch 1-2-1-5-2 is connected in series with the fifth DC-DC step-down regulator (e.g., LTM8067). When the second peripheral chip includes USB, the second power supply branch 1-2-1-5-2 is connected in series with the second TSP (e.g., TSP25200) to power the USB.

[0023] In this embodiment, a first TSP is connected in series in the DP power supply circuit to control the 3.3V power supply for DP communication, ensuring that the provided 3.3V power supply is available for DP communication; a fifth DC-DC step-down regulator is connected in series in the CAN power supply circuit to provide an isolated DC 5.0V power supply to the CAN transceiver, thereby improving the anti-interference capability of CAN communication; a second TSP is connected in series in the USB power supply circuit, which has a similar function to DP, to control the USB to provide DC 5.0V power, avoiding the situation where the inserted USB flash drive cannot be recognized due to the lack of DC 5.0V.

[0024] Figure 3 This is a schematic diagram of the circuit composition of the power module according to an embodiment of the present invention, as shown below. Figure 3 As shown, referring to relevant technologies, the power module input power is AC220V (50Hz±5%, voltage fluctuation±15%), which is used to power the computing device through the main power conversion circuit 1-2-2 and the motherboard power distribution circuit 1-2-1. The main power conversion circuit 1-2-2 is designed according to relevant technologies and meets industry specifications. For example, the main power conversion circuit 1-2-2 may include: AC220V passing through a Schaffner FN410-3-02 filter (150k~30MHz interference filtering) before being input to the TDKLambdaCUS200M-12 power module, outputting DC12V / 16.7A, meeting industry specifications such as "power failure support 10ms", "insulation withstand voltage AC1500VRMS (1 minute)" and "leakage current <3.5mA".

[0025] In this embodiment of the utility model, the SOM module RTC power supply can use a 1200mAh lithium-ion battery ER14250-VB, and achieve "5V power supply when the module is powered on and battery power supply after power failure" through dual Schottky diodes BAT54C. Among them, the XAVIER module can output 3.3V / 418uA through the L53 pin, without the need for an additional 5V power supply.

[0026] In this embodiment of the disclosure, the power distribution drive circuit 1-3-1 is configured such that: when the motherboard power distribution circuit 1-2-1 is connected to power (the first power supply circuit 1-2-1-1 and the third power supply circuit 1-2-1-3 are powered normally), the first enable drive signal ( Figure 3 The reverse connection protection circuit 1-2-1-6 receives the VIN-PWR-ON signal from its drive signal port, which powers on the motherboard power distribution circuit 1-2-1 and outputs the first enable signal to the timing control IC circuit 1-3-2. In one exemplary instance, the timing control IC circuit 1-3-2 of this utility model embodiment includes: a first three-voltage rail simple power sequence generator (e.g., LM3881) 1-3-2-1 with adjustable delay time connected in series and a second three-voltage rail simple power sequence generator 1-3-2-2. In one exemplary embodiment, each power supply branch of this utility model includes a corresponding drive signal input port for receiving drive signals.

[0027] In one exemplary embodiment, the enable signal output terminal of the power distribution drive circuit 1-3-1 of this utility model is connected to an AND gate, the enable signal output terminal of the AND gate is connected to the enable signal input terminal of the first three-voltage rail simple power sequence generator 1-3-2-1, and the enable signal output terminal of the first three-voltage rail simple power sequence generator 1-3-2-1 is connected to the enable signal input terminal of the second three-voltage rail simple power sequence generator 1-3-2-2. The timing control IC circuit 1-3-2 is configured as follows: The first three-voltage rail simplified power sequence generator 1-3-2-1 receives the first enable signal and enters the enable state. It then sequentially outputs the third drive signal to drive the third power supply circuit 1-2-1-3 (low-voltage DC-DC power supply for the computing device) at pre-set signal output time intervals. Figure 3 The third power supply circuit 1-2-1-3 receives the FLAG11 signal at its drive signal input terminal, and drives the first power supply circuit 1-2-1-1 (high-voltage power supply for computing device) with the first drive signal. Figure 3 The third power supply circuit 1-2-1-1 receives the drive signal input terminal of FLAG12 and the second enable signal (FLAG13) of the second three-voltage rail simple power sequence generator 1-3-2-2. The second three-voltage rail simplified power sequence generator 1-3-2-2 receives the second enable signal (FLAG13) through the enable input port. When the second enable signal is high, it outputs the fourth drive signal to drive the fourth power supply circuit 1-2-1-4. After the fourth power supply circuit 1-2-1-4 is powered on, SOM1-1 outputs a synchronous drive signal to the synchronously powered second power supply circuit 1-2-1-2 and fifth power supply circuit 1-2-1-5 through the fourth power supply circuit 1-2-1-4.

[0028] Figure 4 This is a schematic diagram of the timing control IC circuit according to an embodiment of the present invention, as shown below. Figure 4As shown, in this embodiment of the utility model, the first three-voltage rail simple power sequence generator 1-3-2-1 can be configured based on the physical circuit to ensure that the third driving signal, the first driving signal, and the second enable signal (FLAG11, FLAG12, and FLAG13) are 10ms apart. The first three-voltage rail simple power sequence generator 1-3-2-1 is configured based on the physical circuit to receive the second enable signal 10ms (FLAG13) and then output the fourth driving signal. The fourth driving signal (FLAG21) and the reset power-on signal (FLAG22) are 47ms apart.

[0029] In this embodiment of the invention, after the fourth power supply circuit 1-2-1-4 is powered on by the fourth drive signal, the fourth drive signal controls the P-MOS transistor to power on the motherboard using DC5.0V and DC12V power supplies. At this time, SOM1-1 is started. The start of SOM1-1 can be regarded as a component of the drive timing control IC circuit. When the motherboard is powered on using DC5.0V and DC12V power supplies, the SOM runs. Within 5 milliseconds, the SOM, based on its operating characteristics, outputs a synchronous drive signal (SOM PWR ON) to the synchronously powered second power supply circuit 1-2-1-2 and fifth power supply circuit 1-2-1-5.

[0030] In this embodiment, after the power-on timing control circuit 1-3 completes the power-on timing control of the power supply branch, the FLAG22 output by the second three-voltage rail simplified power sequence generator 1-3-2-2 serves as a reset power-on signal (SYS_RST_OK), which controls the reset circuit to notify the entire computing device (Ethernet, 5G, SOM, etc.) that the power-on is complete. The RST signal changes from low level to high level, and the system can start normally.

[0031] In this embodiment of the invention, the switching of the first power supply can be achieved using a P-MOS as a switch, and the first drive signal (FLAG2) is used to control the gate of the MOS transistor. This embodiment employs a pure hardware circuit consisting of a series-connected, adjustable-delay first three-rail simple power sequence generator (e.g., LM3881) 1-3-2-1 and a second three-rail simple power sequence generator 1-3-2-2 to control the power-on sequence. This can be combined with undervoltage monitoring and discharge circuitry to ensure stable start-up and shutdown of the SOM and peripheral chips.

[0032] In one exemplary embodiment, the power-down control of this utility model can be performed according to the following power-down sequence: When the MOT_PWR_ON signal is pulled low, the power supply discharge circuits at each stage are activated, and the SOM (System Oscillator) is powered down normally.

[0033] When the system is powered down in this embodiment of the present invention, the power-down sequence is the reverse of the power-up sequence. When the system detects a drop in the input power (VIN_PWR_ALM, implemented by the power monitoring ICTPS3808, threshold: 10.27V), the LTM3881 changes from enabled to disabled, and the FLGA signal changes from high to low level in sequence according to FLGA13→FLAG12→FLGA11, with the interval between each pair being the same as during power-up.

[0034] As described above, when a system power failure is detected, the reset signal resets all CPUs and peripheral ICs to a stopped state, resulting in extremely low power consumption. Furthermore, since various power control switches (P-MOS, E-FUSE, load switch TPS25200) and DC-DC converters are off, the 12V and DC 5.0V power supplies cannot be consumed. If power is restored shortly after this, the power-on sequence will be disrupted, easily causing the system to fail to start normally.

[0035] In this embodiment of the utility model, the MOTHER_PWR_ON signal in the power-on / off sequence is used to control the power supply circuit. After this signal changes from high to low, the DC12V power supply, the DC5.0V power supply and the discharge resistor are connected. The residual power energy is converted into heat energy by the discharge resistor and consumed, so that each power supply returns to zero.

[0036] In one exemplary instance, the storage circuit of this utility model embodiment may be a storage architecture including one or more of the following storage media: SSD, HDD, SD and EEPROM.

[0037] When the storage circuitry includes an SSD, the SSD can be used for local high-speed storage. The motherboard can connect an external SSD (e.g., Transcend MTE710T-INVMe SSD, 2TB, PCIe Gen4x4, read / write speed 3500MB / s) via an M.2 KEY M connector (e.g., MDT420M03001). Communicates through the SOM's PCIe x4 interface. The SSD supports an operating temperature of -40℃ to 85℃, has a write endurance of 1700TBW, and the PCB has a reserved 22×80mm mounting area (without component obstruction). When the storage circuit includes an HDD, which is used to expand large-capacity storage, the motherboard can implement a SATA interface through a PCIe x1 to SATA chip (e.g., 88SE9215A1 -40℃~85℃, supports 4 SATA 3.0 ports) to connect an external HDD (e.g., WD101EJRPSATA HDD, 10TB, 7200rpm, 256MB cache). The HDD can be connected via a SATA adapter cable (22-pin male to female). The structure is designed with a vibration-damping bracket (to meet vibration and shock requirements), and the operating temperature is 0℃~65℃. When the storage circuit includes auxiliary storage, the auxiliary storage may include SD and / or EEPROM; wherein, SD can be MicroSD, and the motherboard can be configured to connect MicroSD via one MicroSD interface, and the MicroSD can be an industrial-grade 32GB SD card (e.g., Transcend MD33-032GWS00M); EEPROM can be configured on the motherboard with one 8kB IIC EEPROM (CAT24C64WI, 1.7V~5.5V power supply) for storing special information such as module ID.

[0038] In this embodiment of the invention, real-time data can be cached to an SSD, historical data can be archived to an HDD, and module ID information can be stored in an EEPROM. The storage is cost-effective: this embodiment of the invention balances "high-speed real-time data caching" and "large-capacity historical data storage", which can meet the local retention requirements of one week's video data. The hybrid SSD and HDD solution ensures real-time data read and write speed (3500MB / s) and achieves 12TB large-capacity storage, with a cost reduction of more than 40% compared to the all-SSD solution.

[0039] This embodiment of the utility model connects an SSD via an M.2 KEY M interface and an HDD via a PCIe to SATA adapter, and is independently controlled by a second power supply circuit 1-2-1-2 to achieve high-speed and high-capacity storage synergy.

[0040] The motherboard of this utility model embodiment can be configured with interfaces covering high-speed communication, low-speed communication, and debugging to meet the needs of multi-device access and debugging. The motherboard is equipped with an M.2 KEY M connector (e.g., MDT245B03001) for connecting to an external 5G module (e.g., Quectel RM520N-GL5G module, -30℃~70℃, supports NSA / SA mode). It communicates with the SOM via PCIe x1 or USB 3.0. The module integrates a multi-constellation GNSS receiver (accuracy <10ms), and is equipped with a USIM card connector (261S01.31R00, ESD protection GBLC03-LF-T7) and 4 UF.L antenna interfaces (to SMA cable).

[0041] Ethernet communication can include: two Gigabit Ethernet ports, RGMII, and PCIe to Ethernet ports; the two Gigabit Ethernet ports can both support speeds of 10 / 100 / 1000Mbps, adapting to the access of 24 1080P cameras; the RGMII is based on the SOMRGMII interface, paired with the KSZ9031 PHY chip, and brought out through a dual-port RJ45 (5921S-LED); the PCIe to Ethernet port can be based on the LAN7430 chip (PCIe 3.1x1 to Gigabit, supporting IEEE 1588PTP), brought out through the second port of the same RJ45; USB communication can include one USB 3.0 Type A port and one USB 2.0 Type A port; wherein, the USB 3.0 Type A port (e.g. 21B4.33361.01R00) has ESD protection TP D4E05U06D and supports a speed of 5Gbps; the USB 2.0 Type A port (0482040001) has ESD protection PLR0502 and can be used in system recovery mode (FORCE_RECOVERY_N triggered).

[0042] Low-speed communication can include RS485 and CAN; it can include 2 isolated RS485 channels, which can use LTM2881 transceivers and be brought out through DB9 or RJ45, with a communication rate of ≤5Mbps; it can also include 2 isolated CAN channels, which can use ISO1050DUB transceivers and be brought out through DB9 or RJ45, supporting the CAN2.0 protocol.

[0043] The debugging interface may include a JTAG interface and / or a DEBUG UART; the JTAG interface uses a 1.8V level and supports SOC online debugging and BOOT firmware download; the DEBUG UART may be a UART3 interface (1.8V level), which can be converted to RS232 for software debugging.

[0044] The display and image acquisition system is used to implement display functions and reserved image acquisition functions. The display function can be implemented based on a motherboard with one DP interface (e.g., 0472720001), supporting 8K60DP1.4a or HDMI2.1. The 3.3V power supply can be controlled by a TPS25200DR load switch (current limited to 1042mA). The HPD signal can be converted to 1.8V via an SN74LVC1T45 and sent to the SOM. ESD protection is configured at the interface (e.g., GBLC03-LF-T7 for power AUX, TPD4E05U06D for high-speed signals). The image acquisition function can be implemented using 16 MIPICSI-2 interfaces supported by the SOM (e.g., C-PHY2.0, maximum 164Gbps). The motherboard can reserve a 120-pin CSI connector (e.g., QSH-060-01-HDAK-TR). In this embodiment, the camera can be accessed via Ethernet, and the CSI interface is reserved for future expansion.

[0045] This utility model embodiment can achieve full-scene interface coverage: integrating 2 Gigabit Ethernet (RGMII+PCIe to Ethernet), 2 isolated RS485, 2 isolated CAN, 1 USB3.0 + 1 USB2.0, 1 DP display interface, 1 M.25G module interface (supporting GNSS timing, accuracy <10ms, refresh rate >1Hz), and 16 MIPICSI-2 camera interfaces (reserved), which can stably connect ≥24 1080P Ethernet cameras.

[0046] In one exemplary embodiment, the SOM (Surface Mount Oven) of this utility model can be bonded to a custom heat sink (which can have a thermal resistance ≤0.133℃ / W) via a 0.25mm phase change material (e.g., RTP14), and the heat sink has a thermal resistance ≤0.133℃ / W; the 5G module can share heat dissipation with the SOM heat sink via a 3.0W / m・K thermally conductive silicone pad; In one exemplary embodiment, the fan of this utility model can be a 120×120×25mm PWM axial fan (21W, maximum wind speed 160.82CFM, for example, Yongli MGT12012UB-W25, 4800rpm), which can control the speed by outputting a PWM signal through the GPIO of the SOM (the larger the temperature margin, the lower the speed), and can achieve a module temperature ≤80℃ at 100% load in a 70℃ environment.

[0047] The computing device of this utility model operates within a temperature range of -25℃ to 70℃. With vibration and shock protection and EMC level three protection, it can operate stably in complex and harsh environments such as highways and tunnels. The operating temperature is -25℃ to 70℃ (HDD is 0℃ to 65℃), and the protection level is IP20. It is tested through a 2Hz to 150Hz sweep vibration (10m / s²). 2 (acceleration), 300m / s 2 Peak acceleration impact and EMC level 3 protection (ESD contact 4kV, EFT power line 2kV, surge 2kV).

[0048] In this embodiment of the invention, the SOM and the 5G module share the same heat sink through phase change material / thermal conductive silicone pad, which balances heat dissipation efficiency and structural compactness.

[0049] This utility model embodiment can achieve EMC protection based on the following design: the power module uses a dual filter of Schaffner FN410-3-02 and DNM03-S to cover interference from 150k to 1GHz; at the interface end, the following key interfaces, such as USB, Ethernet, RS485, and CAN communication, are all equipped with dedicated ESD protection devices (such as TPD4E05U06D for USB3.0 and PSM712-LF-T7 for RS485); the metal structural components are equipped with grounding posts to achieve a radiation immunity of 20V / m from 0 to 6000MHz.

[0050] The power module of this utility model is based on dual filters, dedicated ESD devices for interfaces, and grounding of a metal structure, forming a full-link EMC protection system.

[0051] The overall dimensions of the computing device in this embodiment are 200mm × 170mm × 95mm (length × width × height), and it is compatible with a 19-inch standard server rack. It supports two installation modes: backplane installation (see...). Figure 5 ): Installed in slots 5-6 of the edge control unit back panel, and secured to the back panel base with screws; ear-mounted installation (see...) Figure 6 It is fixed to the mounting plate by the two side lugs, supporting both vertical and horizontal directions.

[0052] Figure 7 This is a schematic diagram of the panel layout of the computing device according to an embodiment of the present invention, as shown below. Figure 7 As shown, the layout of the computing device panel (from top to bottom) is as follows: Power interface: DC12V Phoenix terminal (e.g., MSTB2.5 / 4-GF-5.08BK); Buttons: PWR (Power On), RST (Reset), RECOVERY (Recovery Mode); Indicator lights: RUN (Green, running status), ERR (Red, fault status), POWER (Yellow, power status), USB / CAN / RS485 / ETH (Yellow, communication status); Card interfaces: SD card connector, SIM card connector; Display interface: DP connector; Communication interfaces: Dual-port USB, Dual-port RJ45 (Ethernet), DB9 (RS485 / CAN).

[0053] The communication interaction of this utility model embodiment may include: uploading analysis results to the cloud via a 5G module, and communicating with the radar and host computer via RS485 and CAN.

[0054] In this embodiment of the invention, the SOM (Start of Operation) is triggered to shut down when the power supply is undervoltage, and the watchdog timeout (1.6S) is automatically reset. The fan speed is dynamically adjusted according to the temperature. This utility model embodiment improves the mean time between failures (MTBF) by 30% through full-link power protection, hardware watchdog, and dynamic heat dissipation design. The power module integrates reverse connection protection (P-MOSFET), overvoltage (TVS), undervoltage monitoring (threshold 10.27V), and discharge circuit. The reset system includes a hardware watchdog (MAX706, timeout 1.6S) and multi-power undervoltage monitoring. Key interfaces (USB, Ethernet, etc.) are equipped with ESD protection devices. Through the integrated architecture of high-performance computing core, multi-interface integration, hybrid storage, and strong protection design, it can directly adapt to the needs of highway edge intelligent controllers and fill the shortcomings of existing products in computing power, interface, environment, and reliability.

[0055] In the description of this utility model, it should be noted that the terms "upper", "lower", "one side", "the other side", "one end", "the other end", "side", "opposite", "four corners", "periphery", "'mouth' structure", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the structure referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0056] In the description of the embodiments of this utility model, unless otherwise expressly specified and limited, the terms "connection," "direct connection," "indirect connection," "fixed connection," "installation," and "assembly" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection. The terms "installation," "connection," and "fixed connection" can refer to a direct connection or an indirect connection through an intermediate medium, and can refer to the internal communication between two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0057] Although the embodiments disclosed in this utility model are as described above, the content described is only for the purpose of facilitating understanding of this utility model and is not intended to limit this utility model. Any person skilled in the art to which this utility model pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this utility model, but the patent protection scope of this utility model shall still be defined by the appended claims.

Claims

1. A computing power device, characterized in that, include: The motherboard (1) includes a system-level module (SOM) (1-1), a power module (1-2), and a power-on timing control circuit (1-3). The SOM (1-1) is connected to the following components via the motherboard (1): a storage circuit (1-1-1), an interface chip and logic IC circuit (1-1-2), and a peripheral chip circuit (1-1-3). The power module (1-2) includes a motherboard power distribution circuit (1-2-1). The motherboard power distribution circuit (1-2-1) includes the following power supply branches: a first power supply circuit (1-2-1-1), a second power supply circuit (1-2-1-2), a third power supply circuit (1-2-1-3), and a fourth power supply circuit (1-2-1-4) connected to the computing power supply, and a fifth power supply circuit (1-2-1-5) connected to the fourth power supply circuit (1-2-1-4); wherein, The first power supply circuit (1-2-1-1) is configured to convert the computing power supply into a first power supply with a first voltage and a first current, and provide power for the first power consumption of SOM (1-1); The second power supply circuit (1-2-1-2) is configured to convert the computing power supply into a second power supply with a second voltage and a second current to supply power to the storage circuit (1-1-1); The third power supply circuit (1-2-1-3) is configured to convert the computing power supply into a third power supply with a third voltage and a third current, and provide power for the second power consumption of SOM (1-1); The fourth power supply circuit (1-2-1-4) is set to convert the computing power power supply into a fourth power supply with a fourth voltage and a fourth current to power the interface chip and logic IC circuit (1-1-2); The fifth power supply circuit (1-2-1-5) includes: a switching branch (1-2-1-5-1), a parallel first power supply branch (1-2-1-5-2), and a second power supply branch (1-2-1-5-3); among which, The switching branch (1-2-1-5-1) is configured to convert the fourth power supply to a fifth power supply with a fifth voltage and a fifth current. The first power supply branch (1-2-1-5-2) is configured to transform the fifth voltage of the fifth power supply to supply power to two or more first peripheral chips with different power supply voltages connected in parallel in the peripheral chip circuit (1-1-3); The second power supply branch (1-2-1-5-3) is configured to supply power to two or more second peripheral chips connected in parallel in the peripheral chip circuit (1-1-3) based on the fifth power supply. The power-on timing control circuit (1-3) includes: a power distribution drive circuit (1-3-1) and a timing control IC circuit (1-3-2) connected in series. The timing control IC circuit (1-3-2) for each power supply branch is connected to the power-on interval. The power distribution drive circuit (1-3-1) is configured as follows: when the motherboard power distribution circuit (1-2-1) is connected to the power supply, the motherboard power distribution circuit (1-2-1) is powered on and the first enable signal is output to the timing control IC circuit (1-3-2). The timing control IC circuit (1-3-2) is configured to: after receiving the first enable signal, output power-on drive signals to the power supply branch in the following power-on sequence to control the power supply branch to power on: the third power supply circuit (1-2-1-3), the first power supply circuit (1-2-1-1), the fourth power supply circuit (1-2-1-4), and other power supply circuits that are powered on synchronously. The other power supply circuits that are powered on synchronously include: the second power supply circuit (1-2-1-2) and the fifth power supply circuit (1-2-1-5).

2. The computing power device according to claim 1, characterized in that, The motherboard (1) is compatible with more than two SOMs; Wherein, the interfaces for connecting the two or more SOMs and the interface signals for transmission are consistent.

3. The computing power device according to claim 1, characterized in that, The motherboard power distribution circuit (1-2-1) also includes, before the power supply branch, a series connection of: a reverse connection protection circuit (1-2-1-6) and an electromagnetic interference (EMC) circuit (1-2-1-7); wherein, The reverse connection protection circuit (1-2-1-6) is configured to protect the connected computing power supply from reverse connection. The EMC circuit (1-2-1-7) is configured to filter out interference from the computing power supply via the reverse connection protection circuit (1-2-1-6).

4. The computing power device according to claim 1, characterized in that, The storage circuit (1-1-1) also includes a fan circuit, and the second power supply circuit (1-2-1-2) is further configured to supply power to the fan circuit.

5. The computing power device according to claim 1, characterized in that, The power module (1-2) also includes a main power conversion circuit (1-2-2), configured to convert the external power supply into the computing power supply.

6. The computing power device according to claim 3, characterized in that: The first power supply circuit (1-2-1-1) includes a first P-field-effect transistor and a first current-limiting circuit; The second power supply circuit (1-2-1-2) includes a second P-field-effect transistor; The third power supply circuit (1-2-1-3) includes a third DC-DC step-down regulator; The fourth power supply circuit (1-2-1-4) includes a fourth DC-DC step-down regulator; The reverse connection protection circuit (1-2-1-6) includes a sixth P-field-effect transistor.

7. The computing device according to any one of claims 1 to 6, characterized in that: When the first peripheral chip includes a DP, the first power supply branch (1-2-1-5-2) is a circuit that supplies power to the DP connected in series with the first TSP; When the second peripheral chip includes CAN, the second power supply branch (1-2-1-5-3) is a circuit that supplies power to CAN connected in series with the fifth DC-DC step-down regulator; When the second peripheral chip includes USB, the second power supply branch (1-2-1-5-3) is a circuit that supplies power to USB connected in series with the second TSP.

8. The computing power device according to any one of claims 1 to 6, characterized in that, The timing control IC circuit (1-3-2) includes: a first three-voltage rail simple power sequence generator (1-3-2-1) and a second three-voltage rail simple power sequence generator (1-3-2-2) connected in series with adjustable delay time. Each power supply branch includes a corresponding drive signal input port for receiving drive signals.

9. The computing power device according to claim 8, characterized in that, The enable signal output terminal of the power distribution drive circuit (1-3-1) is connected to an AND gate. The enable signal output terminal of the AND gate is connected to the enable signal input terminal of the first three-voltage rail simple power sequence generator (1-3-2-1). The enable signal output terminal of the first three-voltage rail simple power sequence generator (1-3-2-1) is connected to the enable signal input terminal of the second three-voltage rail simple power sequence generator (1-3-2-2). The timing control IC circuit (1-3-2) is configured as follows: The first three-voltage rail simple power sequence generator (1-3-2-1) receives the first enable signal and enters the enable state. It sequentially outputs the third drive signal driving the third power supply circuit (1-2-1-3), the first drive signal driving the first power supply circuit (1-2-1-1), and the second enable signal enabling the second three-voltage rail simple power sequence generator (1-3-2-2) through a preset signal output time interval. The second three-voltage rail simplified power sequence generator (1-3-2-2) receives the second enable signal through the enable input port and outputs the fourth drive signal to drive the fourth power supply circuit (1-2-1-4) when the second enable signal is high. After the fourth power supply circuit (1-2-1-4) is powered on, SOM1-1 outputs a synchronous drive signal to the synchronously powered second power supply circuit (1-2-1-2) and fifth power supply circuit (1-2-1-5) through the fourth power supply circuit (1-2-1-4).

10. The computing power device according to any one of claims 1 to 6, characterized in that, The storage circuit may be a storage architecture that includes one or more of the following storage media: SSD, HDD, SD, and EEPROM.

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