A domestically produced 3UVPX architecture PCIe switching board

Abstract

The utility model provides a kind of PCIe exchange board of national production 3U VPX framework.PCIe exchange board takes SM8748EIP of Guo Wei as core, adopts the VPX framework of VITA standard 3U, connects PCIe signal to VPX backplane by VPX connector, and is used for the expansion PCIe of main control board card.This exchange board supports 1 way x16 upstream interface;Support 5 downstream interfaces, including 1 way x8 and 4 way x2;Port link rate supports 2.5GT / s, 5GT / s, 8GT / s, supports rate self negotiation;With test maintenance management function, can obtain board card state information.The utility model selects domestic chip to design, satisfies the requirement of domestic self-controlling.

Description

Technical Field

[0001] This utility model belongs to the field of switching boards, specifically relating to a fully domestically produced 3U VPX architecture PCIe switching board. Background Technology

[0002] The SM8748 is a PCIe 3.0 switching chip with 48 channels and up to 12 ports, enabling data exchange between ports. It is suitable for PCIe fan-out, multi-host systems, and host backup. It can be widely used in computer systems, embedded systems, industrial control, and other fields. However, existing components do not utilize domestically produced parts, leading to restrictions and embargoes on imported electronic components, as well as core technology blockades. Utility Model Content

[0003] To address the aforementioned technical issues, this utility model provides a fully domestically produced 3U VPX architecture PCIe switch board. Based on the Guowei SM8748EIP, it adopts the VITA standard 3U VPX architecture. PCIe signals are connected to the VPX baseboard via VPX connectors for PCIe expansion by the main control board. This switch board supports one x16 upstream interface and five downstream interfaces, including one x8 and four x2 interfaces. Port link speeds support 2.5GT / s, 5GT / s, and 8GT / s, with auto-negotiation. It also features test, maintenance, and management functions, enabling the acquisition of module status information.

[0004] To achieve the above functions, the technical solution of this utility model is as follows:

[0005] A fully domestically produced 3U VPX architecture PCIe switch board, based on Guowei's SM8748EIP, adopts the VITA standard 3U VPX architecture. PCIe signals are connected to the VPX baseboard via VPX connectors for PCIe expansion by the main control board. This switch board supports one x16 upstream interface and five downstream interfaces, including one x8 and four x2 interfaces. Port link speeds support 2.5GT / s, 5GT / s, and 8GT / s, with auto-negotiation. It also features test, maintenance, and management functions, enabling the acquisition of module status information.

[0006] Furthermore, the SM8748EIP is a PCIe 3.0 switching chip with 48 channels and up to 12 ports, enabling data exchange between ports. This chip supports basic mode and virtual switching mode. Using the basic mode, a standard PCIe switching mode, the entire PCIe system has only one host as the root node, managed by the root node, enabling data exchange between devices. The PCIe ports are compatible with the PCIe 3.0 specification and backward compatible, supporting speeds of 8GT / s, 5GT / s, and 2.5GT / s. The link width can be configured to x16, x8, and x4, and can also be automatically negotiated to x2 or x1.

[0007] Furthermore, each port of the SM8748EIP implements the PCIe 3.0 physical layer, data link layer, and transaction layer. The SM8748EIP divides the 12 ports into three groups, namely Station0 to Stationn2. Paths are sequentially assigned to each enabled port. The link width of the port is determined by 300h[8:0], which can be initialized by pins STRAP_STNx_PORTCFG[1:0]. These pins can be pulled up or bound to VDD18, pulled down or bound to VSS, or left floating. Station0 is configured in x16 mode, with all ports connected to the CPU board (or a custom host board) via VPX connectors. Station1 is configured in one x8 and two x4 modes. All x8 ports are connected to the GPU board (or a custom PCIe slave device) via VPX connectors, and the two x4 ports (lan0~lan1) are connected to the function board via VPX connectors. Station2 is configured in a 4x4 mode, with LAN0~LAN1 of two x4 ports brought out via VPX connectors as downstream ports to connect to the function board. The functions of the remaining two x4 ports are yet to be determined, and they are reserved for expansion storage by connecting to NVMe connectors.

[0008] Furthermore, the IPMB chassis management is implemented using the GD32F407 series chip, serving as the PCIe switch board management. The MCU on the main control board can be connected to the GD32F407 on the switch board via the I2C bus through a VPX connector. The GD32F407 on the switch board acts as the overall board power management chip. It first powers on and starts working via 3V3_AUX. After the 12V power supply is powered on, the MCU power supply switches to the on-board power supply. After startup, the GD32F407 waits for power-on / off commands and completes the configuration of relevant GPIOs, controlling the power-on / off of the 12V power supply for the other boards in the chassis.

[0009] Furthermore, the voltage monitoring module uses the ADC of GD32F407 to monitor the internal voltage of the system, SC810DFT-2P5F5 to monitor the current of the entire board, and DS18B20 to monitor the temperature of the entire board. When the temperature is too high and reaches the threshold, GD32F407 controls the system to power down and reports the board status. GD32F407 determines the board slot by reading the pull-up and pull-down status of GA[4:0] on VPX connector P0.

[0010] Furthermore, the PCIe clock of the SM8748EIP is provided by the baseboard, ensuring that the PCIe clock and the main control card clock are from the same source. A 100MHz crystal oscillator is also reserved on the board as a backup. The 25MHz clock signal required by the GD32F407 is provided by the crystal oscillator.

[0011] Furthermore, the power module consists of one ACT4630 chip and one ACT4622 chip. The ACT4630 has two outputs of 1.1V / 18A and 1.8V / 18A respectively, while the ACT4622 has two outputs of 3.3V / 4A and 5V / 4A respectively.

[0012] Furthermore, the switching board provides one standard NVMe interface with a standard M.2 connector, through which a standard NVMe disk can be connected. It supports PCIe 3.0 x4, and clock and reset signals are provided by the backplane.

[0013] Furthermore, the PCIe_REST# reset of the SM8748EIP is jointly controlled by the main control card sys_rest reset signal, the MCU, and the power-on RC reset circuit. Any reset enable can reset the SM8748EIP.

[0014] Beneficial effects:

[0015] The PCIe switch board developed using this invention supports one x16 upstream interface and five downstream interfaces, including one x8 and four x2 interfaces. Port link speeds support 2.5GT / s, 5GT / s, and 8GT / s, with auto-negotiation. It also features testing, maintenance, and management functions, enabling the acquisition of module status information. This PCIe switch board is designed using domestically produced chips, meeting the requirements of domestic production and independent control, and can be applied in computer systems, embedded systems, industrial control, and other fields. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a domestically produced 3U VPX architecture PCIe switching board according to the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the present utility model and are not intended to limit the present utility model. Furthermore, the technical features involved in the various embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.

[0018] like Figure 1 As shown, this utility model discloses a fully domestically produced 3U VPX architecture PCIe switching board, whose main chips consist of SM8748EIP, GD32F407, SC810DFT-2P5F5, DS18B20, ACT4630 and ACT4622.

[0019] The PCIe switch board uses the SM8748EIP from Guowei Microelectronics as its core, adopting the VITA standard 3U VPX architecture. PCIe signals are connected to the VPX baseboard via VPX connectors for PCIe expansion by the main control board. The SM8748EIP supports basic mode and virtual switching mode. Using the basic mode, the entire PCIe system has only one host as the root node, and the entire system is managed by the root node, enabling data exchange between devices. The SM8748EIP divides its 12 ports into three groups: Station0 to Station2. Paths are sequentially assigned to each enabled port. The link width of the port is determined by 300h[8:0], which can be initialized using the pins STRAP_STNx_PORTCFG[1:0]. These pins can be pulled up or bound to VDD18, pulled down or bound to VSS, or left floating. Station 0 is configured in x16 mode, with all ports (port 0) connected via VPX P1 connectors as upstream ports to the CPU board (or a custom motherboard). Station 1 is configured in one x8 and two x4 configurations. The x8 port (port 8) is connected via VPX P2 connectors as downstream ports to the GPU board (or a custom PCIe slave device). The two x4 ports (lan0-lan1) are connected via VPX P2 connectors on ports 9 and 10, respectively, as downstream ports to the function board. Station 2 is configured in four x4 configurations. The two x4 ports (lan0-lan1) are connected via VPX P2 connectors on ports 16 and 17, respectively, as downstream ports to the function board. The functions of the remaining two x4 ports are yet to be determined, and they are reserved for extended storage via an NVMe connector on port 19 (ports 11 and 18 are spares). Chassis management is implemented using GD32F407 series chips. The MCU on the main control board can be connected to the GD32F407 on the switch board via I2C bus through VPX connectors. The GD32F407 on the switching board serves as the overall power management unit. It first powers on via 3V3_AUX and begins operation. After the 12V power supply is applied, the GD32F407 switches to onboard power. Upon startup, the GD32F407 waits for power-on / off commands and completes the configuration of relevant GPIOs, controlling the power-on / off of the 12V power supplies for the remaining boards in the chassis. The GD32F407 monitors the internal system voltage using its own ADC, the SC810DFT-2P5F5 acts as a current detection module to monitor the overall board current, and the DS18B20 monitors the overall board temperature. When the temperature exceeds a threshold, the GD32F407 controls the system to power down and reports the board status. The GD32F407 determines the board slot by reading the pull-up / pull-down state of GA[4:0] on the VPX connector P0. The PCIe clock for the SM8748EIP is provided by the baseboard, ensuring that the PCIe clock is from the same source as the main control card clock. Meanwhile, a 100MHz crystal oscillator is reserved on the board as an alternative.The 25MHz clock signal required by the GD32F407 is provided by a crystal oscillator. The onboard power module consists of one ACT4630 chip and one ACT4622 chip. The ACT4630 outputs 1.1V / 18A and 1.8V / 18A on two channels respectively, while the ACT4622 outputs 3.3V / 4A and 5V / 4A on two channels respectively. The switch board provides one standard NVMe interface with a standard M.2 connector, allowing external standard NVMe drives to be connected via this M.2 interface. It supports PCIe 3.0 x4. Clock and reset signals are provided by the baseboard. The SM8748EIP's PCIe_REST# reset is jointly controlled by the main control card's sys_rest reset signal, the MCU, and the power-on RC reset circuit. Enabling any of these resets will reset the SM8748EIP.

[0020] The preferred embodiments of the present invention have been described above with reference to the accompanying drawings. However, it should be understood that the above description is merely exemplary. Those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. The scope of protection of the present invention is defined by the appended claims.

Claims

1. A fully domestically produced 3U VPX architecture PCIe switching board, characterized in that: The PCIe switch board is based on the Guowei SM8748EIP and adopts the VITA standard 3U VPX architecture. It connects the PCIe signals to the VPX baseboard through the VPX connector for the main control board to expand PCIe. It supports one x16 upstream interface and five downstream interfaces, including one x8 and four x2 interfaces. The port link speed supports 2.5GT / s, 5GT / s, and 8GT / s, and supports auto-negotiation of the speed. It has test, maintenance and management functions and can obtain module status information.

2. The domestically produced 3U VPX architecture PCIe switching board according to claim 1, characterized in that: The core switching chip is the Guowei SM8748EIP; the SM8748EIP is a PCIe 3.0 switching chip with 48 channels and up to 12 ports, enabling data exchange between ports. It supports the standard PCIe switching mode. The entire PCIe system has only one host as the root node, and the entire system is managed by the root node to realize data exchange between devices. The PCIe port is compatible with the PCIe 3.0 specification and backward compatible, supporting three speeds: 8GT / s, 5GT / s, and 2.5GT / s. The link width can be configured as x16, x8, or x4, or automatically negotiated to x2 or x1.

3. The domestically produced 3U VPX architecture PCIe switching board according to claim 1, characterized in that: Each port of the SM8748EIP implements the PCIe 3.0 physical layer, data link layer, and transaction layer. The SM8748EIP divides the 12 ports into three groups: Station0 to Station2. Paths are sequentially assigned to each enabled port. The link width of the port is determined by 300h[8:0], which is initialized through the pin STRAP_STNx_PORTCFG[1:0]. The pin can be pulled up or bound to VDD18, pulled down or bound to VSS, or left floating. Station0 is configured in x16 mode, and all ports are brought out through the VPX connector as upstream ports. The ports connect to the CPU board or a custom motherboard; Station1 is configured with one x8 and two x4 ports. All x8 ports are brought out through VPX connectors as downstream ports to connect to the GPU board or a custom PCIe slave device. The lan0~lan1 ports of the two x4 ports are brought out through VPX connectors as downstream ports to connect to the function board. Station2 is configured with four x4 ports. The lan0~lan1 ports of the two x4 ports are brought out through VPX connectors as downstream ports to connect to the function board. The functions of the remaining two x4 ports are yet to be determined. They are connected to NVMe connectors as reserved for extended storage.

4. A fully domestically produced 3U VPX architecture PCIe switching board according to claim 1, characterized in that: It supports IPMB chassis power management, and an internal GD32F407 series chip is designed for PCIe switch board power management. The MCU on the main control board is connected to the GD32F407 on the switching board via the I2C bus and the VPX connector.

5. A fully domestically produced 3U VPX architecture PCIe switching board according to claim 1, characterized in that: The internal voltage of the system is monitored by the ADC of GD32F407; the current of the whole board is monitored by SC810DFT-2P5F5 and the temperature of the whole board is monitored by DS18B20. When the temperature is too high and reaches the threshold, GD32F407 controls the system to power down and reports the board status; GD32F407 determines the board slot by reading the pull-up and pull-down status of GA[4:0] on VPX connector P0.

6. A fully domestically produced 3U VPX architecture PCIe switching board according to claim 5, characterized in that: The PCIe clock of the SM8748EIP is provided by the baseboard, ensuring that the PCIe clock and the main control card clock are from the same source; at the same time, a 100MHz crystal oscillator is reserved on the board; the 25MHz clock signal required by the GD32F407 is provided by the crystal oscillator.

7. A fully domestically produced 3U VPX architecture PCIe switching board according to claim 1, characterized in that: One ACT4630 chip and one ACT4622 chip are used as the power supply module on the board. The ACT4630 has two outputs of 1.1V / 18A and 1.8V / 18A respectively; the other ACT4622 has two outputs of 3.3V / 4A and 5V / 4A respectively.

8. A fully domestically produced 3U VPX architecture PCIe switching board according to claim 1, characterized in that: The switching board provides one standard NVMe interface, and the connector is a standard M.2 connector. A standard NVMe disk is connected through the M.2 interface. It supports PCIe 3.0 x4. Clock signals and reset signals are provided by the backplane.

9. A fully domestically produced 3U VPX architecture PCIe switching board according to claim 1, characterized in that: The PCIe_REST# reset of SM8748EIP is jointly controlled by the main control card sys_rest reset signal, MCU and power-on RC reset circuit. Any reset enable can reset SM8748EIP.

10. A fully domestically produced 3U VPX architecture PCIe switching board according to claim 1, characterized in that: The GD32F407 on the switching board serves as the overall power management system. It first powers on and starts working via 3V3_AUX. After the 12V power supply is powered on, the GD32F407 switches to internal power supply. After the GD32F407 starts up, it waits for power-on / off commands and completes the configuration of relevant GPIOs to control the power-on / off of the 12V power supply for the other boards in the chassis.

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