A quick key destroying circuit with special lightning protection function

Abstract

The utility model discloses a kind of special lightning protection function's quick key destroying circuit, for with the key body to be destroyed electrically connected, wherein special lightning protection function's quick key destroying circuit includes lightning protection circuit, logic control circuit and power supply switching circuit connected in turn, and power supply switching circuit is electrically connected with the key body to be destroyed, logic control circuit includes delay module and microprocessor connected with lightning protection circuit, and microprocessor is equipped with the first interface of key power detection, and the second interface of the key body to be destroyed electrically connected with.Because of the present application, special lightning protection function's quick key destroying circuit is destroyed by soft key and hard key double key, so that key destroying function is more comprehensive and complete, and the destruction time is short;And through lightning protection circuit and delay module, the residual voltage of external lightning is filtered, to prevent lightning residual voltage signal from triggering key destroying function or breaking overvoltage and overcurrent protector to realize key destroying function.

Description

Technical Field

[0001] This utility model belongs to the field of data recording and key destruction technology, specifically relating to a fast key destruction circuit with special lightning protection function. Background Technology

[0002] With the continuous progress and development of electronic information technology, the bandwidth and capacity of data recording products are constantly increasing. In some special application areas where data confidentiality is required, the rapid destruction function has become one of its indispensable functions. However, the increase in capacity and the timeliness of destruction are contradictory.

[0003] In existing technologies, the destruction of electronic disks is mainly achieved by relying on the hardware destruction function of the electronic disk manufacturer. However, this method has a long destruction time and high power requirements for the destruction key; in addition, there is no special lightning protection function in existing technologies. Summary of the Invention

[0004] The purpose of this invention is to address the problems raised in the background art by proposing a fast key destruction circuit with special lightning protection function.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows: This utility model proposes a fast key destruction circuit with special lightning protection function, which is used to be electrically connected to the key body to be destroyed. The fast key destruction circuit with special lightning protection function includes a lightning protection circuit, a logic control circuit and a power switching circuit connected in sequence, and the power switching circuit is electrically connected to the key body to be destroyed. The logic control circuit includes a delay module and a microprocessor, both of which are connected to the lightning protection circuit. The microprocessor is provided with a first interface for detecting the power supply of the key to be destroyed, and a second interface electrically connected to the key body to be destroyed. The power switching circuit includes an overvoltage and overcurrent protector and a switch. The overvoltage and overcurrent protector is electrically connected to one input terminal of the delay module and the switch, respectively. The other input terminal of the switch is used to connect to the normal operating power supply. The output terminal of the switch is electrically connected to the key body to be destroyed.

[0006] Preferably, the lightning protection circuit includes a third interface for inputting the key-destroying power supply, a fuse, a TVS diode, and a fifth capacitor. The third interface, the fuse, and the TVS diode are connected in sequence, and the end of the TVS diode furthest from the fuse is grounded. The fifth capacitor is connected in parallel with the TVS diode.

[0007] Preferably, the delay module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first delay circuit, a second delay circuit, a third delay circuit, and a fourth delay circuit, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all PMOS transistors, and the fifth MOS transistor is an NMOS transistor, wherein: One plate of the fifth capacitor is connected to the first delay circuit, the second delay circuit, and the source of the first MOSFET. The other plate of the fifth capacitor is connected to the second delay circuit, the drain of the fifth MOSFET, and the source of the second delay circuit. The first delay circuit is also connected to the gate of the first MOSFET and the source of the fifth MOSFET. The third delay circuit is connected to the drain of the first MOSFET, the drain of the second MOSFET, the gate of the second MOSFET, the drain of the third MOSFET, the drain of the fourth MOSFET, and the gate of the fourth MOSFET. The second delay circuit is connected to the source of the second MOSFET, the gate of the fifth MOSFET, and the drain of the fifth MOSFET. The fourth delay circuit is connected to the gate of the third MOSFET, the source of the third MOSFET, and the source of the fourth MOSFET, and is grounded. The fourth delay circuit is also connected to an overvoltage and overcurrent protector.

[0008] Preferably, the first delay circuit includes a first resistor, a sixth resistor, and a first capacitor. One end of the first resistor is connected to one plate of the fifth capacitor, one plate of the first capacitor, and the source of the first MOS transistor, respectively. The other end of the first resistor is connected to one end of the sixth resistor, the other plate of the first capacitor, and the gate of the first MOS transistor, respectively. The other end of the sixth resistor is connected to the source of the fifth MOS transistor.

[0009] Preferably, the second delay circuit includes a second resistor, a fifth resistor, and a second capacitor. One end of the fifth resistor is connected to one plate of the fifth capacitor, and the other end of the fifth resistor is connected to one end of the second resistor, one plate of the second capacitor, and the gate of the fifth MOS transistor. The other end of the second resistor is connected to the other plate of the second capacitor, the other plate of the fifth capacitor, and the drain of the fifth MOS transistor.

[0010] Preferably, the third delay circuit includes a third resistor, a seventh resistor, and a third capacitor. One end of the seventh resistor is connected to the drain of the first MOSFET and the drain of the third MOSFET, respectively. The other end of the seventh resistor is connected to the gate of the second MOSFET, one end of the third resistor, one plate of the third capacitor, and the gate of the fourth MOSFET, respectively. The other end of the third resistor is connected to the drain of the second MOSFET, the drain of the fourth MOSFET, and the other plate of the third capacitor, respectively.

[0011] Preferably, the fourth delay circuit includes a fourth resistor, an eighth resistor, and a fourth capacitor. One end of the fourth resistor is connected to one plate of the fourth capacitor, the source of the third MOSFET, and an overvoltage and overcurrent protector, respectively. The other end of the fourth resistor is connected to the gate of the third MOSFET, the other plate of the fourth capacitor, and one end of the eighth resistor, respectively. The other end of the eighth resistor is connected to the source of the fourth MOSFET and grounded.

[0012] Preferably, the microprocessor is also connected to an LDO power supply, and the LDO power supply is connected to one plate of the fifth capacitor or to a normal operating power supply, and the LDO power supply powers the microprocessor.

[0013] Preferably, the second interface of the microprocessor is also connected to an isolator, and the isolator is electrically connected to the key body to be destroyed.

[0014] Preferably, the key body to be destroyed is a memory that stores key information.

[0015] Compared with the prior art, the beneficial effects of this utility model are as follows: This device employs a fast key destruction circuit with special lightning protection, using both soft and hard key destruction to achieve a more comprehensive and thorough key destruction function with a short destruction time. Furthermore, it filters residual voltage from external lightning strikes through a lightning protection circuit and a delay module, preventing residual lightning voltage signals from falsely triggering the key destruction function or damaging the overvoltage and overcurrent protectors, thus preventing the key destruction function from being rendered ineffective. Attached Figure Description

[0016] Figure 1 This is a block diagram of the fast key destruction circuit with special lightning protection function of this utility model; Figure 2 This is a block diagram of the logic control circuit of this utility model. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] like Figures 1-2 As shown, a fast key destruction circuit with special lightning protection function is provided for electrical connection with the key body to be destroyed. The fast key destruction circuit with special lightning protection function includes a lightning protection circuit, a logic control circuit and a power switching circuit connected in sequence, and the power switching circuit is electrically connected to the key body to be destroyed. The logic control circuit includes a delay module and a microprocessor (such as the GD32F3 series) that are both connected to the lightning protection circuit. The microprocessor is equipped with a first interface (using an ADC detection interface) for detecting the key destruction power supply (in this embodiment, the key destruction power supply is a 28V power supply) and a second interface (using an I2C interface) that is electrically connected to the key body to be destroyed. The power switching circuit includes an overvoltage and overcurrent protector (such as the XC388 model overvoltage and overcurrent protector) and a switch (such as the XNM20N06S3 model switch). The overvoltage and overcurrent protector is electrically connected to one input terminal of the delay module and the switch, respectively. The other input terminal of the switch is used to connect to the normal operating power supply (in this embodiment, the normal operating power supply is a 3.3V power supply). The output terminal of the switch is electrically connected to the key body to be destroyed.

[0019] It should be noted that the key to be destroyed is a memory storing key information, specifically an EEPROM (Electrically Erasable Programmable Read-Only Memory). When the key to be destroyed is working normally (i.e., when key destruction is not required), a 3.3V power supply is provided to the microprocessor and the key to be destroyed to ensure normal operation, and the switch is connected to the normal power supply, providing power to the key to be destroyed through the switch. When key destruction is required, a 28V power supply is provided to the surge protection circuit and the microprocessor's ADC detection interface. When the microprocessor's ADC detection interface detects the 28V power supply, and the switch switches to the overvoltage and overcurrent protection, the microprocessor's I2C interface... The write operation erases the key information (i.e., soft key destruction, and the specific process of soft key destruction is a well-known technique in the prior art), and the microprocessor enables the switch (the microprocessor has an enable interface that is electrically connected to the switch). The 28V power supply passes through the surge protection circuit and the delay module to reach the overvoltage and overcurrent protector, and then provides 28V power to the key body to be destroyed through the switch, thus destroying the key body and completely destroying the EEPROM memory that stores the key information, thereby achieving hard key destruction. Through the dual destruction of the key by soft and hard keys, the key destruction function is more comprehensive and thorough, and the destruction time is short.

[0020] In one embodiment, the surge protection circuit includes a third interface for inputting the power supply, a fuse, a TVS diode (unidirectional), and a fifth capacitor (in...). Figure 1 (represented by C5 in the diagram), the third interface, the fuse, and the TVS diode are connected in sequence, with the end of the TVS diode furthest from the fuse grounded, and the fifth capacitor connected in parallel with the TVS diode.

[0021] It should be noted that the surge protection circuit limits the residual short and long pulse voltage values ​​of the external power supply (i.e., the residual voltage of external lightning) to the TVS tube clamping voltage of 8.4V or below. The peak power of the TVS tube is 5000W, which is a relatively large power. The ceramic capacitor helps to recover some energy and prevents the residual lightning voltage signal from accidentally triggering the key destruction function or damaging the overvoltage and overcurrent protector.

[0022] like Figures 1-2 As shown, in one embodiment, the delay module includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a first delay circuit, a second delay circuit, a third delay circuit, and a fourth delay circuit (each delay circuit is an RC delay circuit), and the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET are all PMOS transistors, and the fifth MOSFET is an NMOS transistor, wherein: in Figure 1 and Figure 2 In the diagram, the first MOSFET is represented by M1, the second MOSFET by M2, the third MOSFET by M3, the fourth MOSFET by M4, and the fifth MOSFET by M5. One plate of the fifth capacitor is connected to the first delay circuit, the second delay circuit, and the source of the first MOSFET. The other plate of the fifth capacitor is connected to the second delay circuit, the drain of the fifth MOSFET, and the source of the second delay circuit. The first delay circuit is also connected to the gate of the first MOSFET and the source of the fifth MOSFET. The third delay circuit is connected to the drain of the first MOSFET, the drain of the second MOSFET, the gate of the second MOSFET, the drain of the third MOSFET, the drain of the fourth MOSFET, and the gate of the fourth MOSFET. The second delay circuit is connected to the source of the second MOSFET, the gate of the fifth MOSFET, and the drain of the fifth MOSFET. The fourth delay circuit is connected to the gate of the third MOSFET, the source of the third MOSFET, and the source of the fourth MOSFET, and is grounded. The fourth delay circuit is also connected to an overvoltage and overcurrent protector.

[0023] It should be noted that the delay module isolates the residual lightning voltage after the lightning protection circuitry from the memory, further preventing damage to the memory chip (i.e., the key to be destroyed) or the overvoltage and overcurrent protector (which would render the key destruction function impossible). By adjusting the resistance and capacitance values ​​in the first, second, third, and fourth delay circuits, the MOSFET turn-on delay function is achieved, preventing the MOSFET from being mistakenly turned on due to residual lightning voltage.

[0024] like Figure 2As shown, in one embodiment, the first delay circuit includes a first resistor, a sixth resistor, and a first capacitor. One end of the first resistor is connected to one plate of the fifth capacitor, one plate of the first capacitor, and the source of the first MOSFET. The other end of the first resistor is connected to one end of the sixth resistor, the other plate of the first capacitor, and the gate of the first MOSFET. The other end of the sixth resistor is connected to the source of the fifth MOSFET. Wherein, in Figure 2 In the diagram, the first resistor is represented by R1, the sixth resistor by R6, and the first capacitor by C1.

[0025] like Figure 2 As shown, in one embodiment, the second delay circuit includes a second resistor, a fifth resistor, and a second capacitor. One end of the fifth resistor is connected to one plate of the fifth capacitor, and the other end of the fifth resistor is connected to one end of the second resistor, one plate of the second capacitor, and the gate of the fifth MOSFET. The other end of the second resistor is connected to the other plate of the second capacitor, the other plate of the fifth capacitor, and the drain of the fifth MOSFET. Wherein, in Figure 2 In the diagram, the second resistor is represented by R2, the fifth resistor by R5, and the second capacitor by C2.

[0026] like Figure 2 As shown, in one embodiment, the third delay circuit includes a third resistor, a seventh resistor, and a third capacitor. One end of the seventh resistor is connected to the drain of the first MOSFET and the drain of the third MOSFET, respectively. The other end of the seventh resistor is connected to the gate of the second MOSFET, one end of the third resistor, one plate of the third capacitor, and the gate of the fourth MOSFET, respectively. The other end of the third resistor is connected to the drain of the second MOSFET, the drain of the fourth MOSFET, and the other plate of the third capacitor, respectively. Wherein, in Figure 2 In the diagram, the third resistor is represented by R3, the seventh resistor by R7, and the third capacitor by C3.

[0027] like Figure 2 As shown, in one embodiment, the fourth delay circuit includes a fourth resistor, an eighth resistor, and a fourth capacitor. One end of the fourth resistor is connected to one plate of the fourth capacitor, the source of the third MOSFET, and an overvoltage / overcurrent protector, respectively. The other end of the fourth resistor is connected to the gate of the third MOSFET, the other plate of the fourth capacitor, and one end of the eighth resistor, respectively. The other end of the eighth resistor is connected to the source of the fourth MOSFET and grounded. Wherein, in Figure 2 In the diagram, the fourth resistor is represented by R4, the eighth resistor by R8, and the third capacitor by C3.

[0028] In one embodiment, the microprocessor is also connected to an LDO power supply, which is connected to one plate of the fifth capacitor or to the normal operating power supply, and the LDO power supply powers the microprocessor. During normal operation, a 3.3V power supply powers the microprocessor through the LDO power supply; when power is needed, a 28V power supply powers the microprocessor through the LDO power supply.

[0029] In one embodiment, the microprocessor's I2C interface is also connected to an isolator, which is electrically connected to the key to be destroyed. The isolator's function is to isolate the microprocessor from the key to be destroyed, preventing damage to the microprocessor after hard key destruction.

[0030] It should be noted that the key to be destroyed has a power supply pin (3.3V, in...) Figure 1 The power supply (represented as 3.3V_XH_FLASH) is, in actual destruction scenarios, the 28V_HY_IN power supply output from the front-end logic circuit passes through an overvoltage and overcurrent protector to the power supply pin (3.3V_XH_FLASH) of the key storage circuit. Simultaneously, it is cut off when the 28V rises above 4V. Figure 1 The switch in the circuit prevents the 28V_HY_IN power supply from short-circuiting the 3.3V_STBY power domain, which would prevent the 28V from reaching the voltage and energy required for the key storage circuit to be destroyed. The overvoltage and overcurrent protector adjusts the overcurrent point by controlling the resistor R. When two memories need to be destroyed simultaneously, if one memory has already completed the destruction process and the load is short-circuited, the overcurrent protection function is triggered in time to supply the 28V power for destruction to the other memory, thus achieving the purpose of destroying multiple memories simultaneously.

[0031] When the key body to be destroyed is working normally, the lightning protection circuit and the delay mode prevent external radar voltage from entering through the third interface and damaging the overvoltage and overcurrent protector, thus preventing the key destruction function from being realized. When it is necessary to destroy the key body to be destroyed, the lightning protection circuit and the delay mode prevent external lightning voltage from destroying the key body to be destroyed through the third interface before the soft key destruction is completed, thus directly performing hard key destruction and causing incomplete key destruction.

[0032] This device employs a fast key destruction circuit with special lightning protection, using both soft and hard key destruction to achieve a more comprehensive and thorough key destruction function with a short destruction time. Furthermore, it filters residual voltage from external lightning strikes through a lightning protection circuit and a delay module, preventing residual lightning voltage signals from falsely triggering the key destruction function or damaging the overvoltage and overcurrent protectors, thus preventing the key destruction function from being rendered ineffective.

[0033] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A fast key destruction circuit with special lightning protection function, characterized in that: The fast key destruction circuit with special lightning protection function is used to be electrically connected to the key body to be destroyed. The fast key destruction circuit with special lightning protection function includes a lightning protection circuit, a logic control circuit and a power switching circuit connected in sequence, and the power switching circuit is electrically connected to the key body to be destroyed. The logic control circuit includes a delay module and a microprocessor, both of which are connected to the lightning protection circuit. The microprocessor is provided with a first interface for detecting the power supply of the key to be destroyed, and a second interface electrically connected to the key body to be destroyed. The power switching circuit includes an overvoltage and overcurrent protector and a switch. The overvoltage and overcurrent protector is electrically connected to one input terminal of the delay module and the switch, respectively. The other input terminal of the switch is used to connect to the normal operating power supply. The output terminal of the switch is electrically connected to the key body to be destroyed.

2. The fast key destruction circuit with special lightning protection function as described in claim 1, characterized in that: The lightning protection circuit includes a third interface for inputting the key-destroying power supply, a fuse, a TVS diode, and a fifth capacitor. The third interface, fuse, and TVS diode are connected in sequence, with the end of the TVS diode furthest from the fuse grounded. The fifth capacitor is connected in parallel with the TVS diode.

3. The fast key destruction circuit with special lightning protection function as described in claim 2, characterized in that: The delay module includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a first delay circuit, a second delay circuit, a third delay circuit, and a fourth delay circuit. The first MOSFET, second MOSFET, third MOSFET, and fourth MOSFET are all PMOS transistors, and the fifth MOSFET is an NMOS transistor. One plate of the fifth capacitor is connected to the first delay circuit, the second delay circuit, and the source of the first MOSFET. The other plate of the fifth capacitor is connected to the second delay circuit, the drain of the fifth MOSFET, and the source of the second delay circuit. The first delay circuit is also connected to the gate of the first MOSFET and the source of the fifth MOSFET. The third delay circuit is connected to the drain of the first MOSFET, the drain of the second MOSFET, the gate of the second MOSFET, the drain of the third MOSFET, the drain of the fourth MOSFET, and the gate of the fourth MOSFET. The second delay circuit is connected to the source of the second MOSFET, the gate of the fifth MOSFET, and the drain of the fifth MOSFET. The fourth delay circuit is connected to the gate of the third MOSFET, the source of the third MOSFET, and the source of the fourth MOSFET, and is grounded. The fourth delay circuit is also connected to an overvoltage and overcurrent protector.

4. The fast key destruction circuit with special lightning protection function as described in claim 3, characterized in that: The first delay circuit includes a first resistor, a sixth resistor, and a first capacitor. One end of the first resistor is connected to one plate of the fifth capacitor, one plate of the first capacitor, and the source of the first MOS transistor. The other end of the first resistor is connected to one end of the sixth resistor, the other plate of the first capacitor, and the gate of the first MOS transistor. The other end of the sixth resistor is connected to the source of the fifth MOS transistor.

5. The fast key destruction circuit with special lightning protection function as described in claim 3, characterized in that: The second delay circuit includes a second resistor, a fifth resistor, and a second capacitor. One end of the fifth resistor is connected to one plate of the fifth capacitor, and the other end of the fifth resistor is connected to one end of the second resistor, one plate of the second capacitor, and the gate of the fifth MOS transistor. The other end of the second resistor is connected to the other plate of the second capacitor, the other plate of the fifth capacitor, and the drain of the fifth MOS transistor.

6. The fast key destruction circuit with special lightning protection function as described in claim 3, characterized in that: The third delay circuit includes a third resistor, a seventh resistor, and a third capacitor. One end of the seventh resistor is connected to the drain of the first MOSFET and the drain of the third MOSFET, respectively. The other end of the seventh resistor is connected to the gate of the second MOSFET, one end of the third resistor, one plate of the third capacitor, and the gate of the fourth MOSFET, respectively. The other end of the third resistor is connected to the drain of the second MOSFET, the drain of the fourth MOSFET, and the other plate of the third capacitor, respectively.

7. The fast key destruction circuit with special lightning protection function as described in claim 3, characterized in that: The fourth delay circuit includes a fourth resistor, an eighth resistor, and a fourth capacitor. One end of the fourth resistor is connected to one plate of the fourth capacitor, the source of the third MOSFET, and an overvoltage and overcurrent protector, respectively. The other end of the fourth resistor is connected to the gate of the third MOSFET, the other plate of the fourth capacitor, and one end of the eighth resistor, respectively. The other end of the eighth resistor is connected to the source of the fourth MOSFET and grounded.

8. The fast key destruction circuit with special lightning protection function as described in claim 1, characterized in that: The microprocessor is also connected to an LDO power supply, and the LDO power supply is connected to one plate of the fifth capacitor or to a normal operating power supply, and the LDO power supply powers the microprocessor.

9. The fast key destruction circuit with special lightning protection function as described in claim 1, characterized in that: The second interface of the microprocessor is also connected to an isolator, and the isolator is electrically connected to the key body to be destroyed.

10. The fast key destruction circuit with special lightning protection function as described in claim 1, characterized in that: The key to be destroyed is a memory that stores key information. The first interface is an ADC detection interface and the second interface is an I2C interface.

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