non-volatile memory

Abstract

The present disclosure provides a non-volatile memory, which comprises a peripheral array arranged around a memory cell array, and the peripheral array is sequentially provided with a sense amplifier, a Y-direction selector and a peripheral circuit outside; a peripheral state register array is arranged in the peripheral circuit; a target global bit line in the memory cell array extends to the peripheral circuit to be electrically connected with the peripheral state register array, so that the peripheral state register array shares the sense amplifier and the Y-direction selector with the memory cell array. The present disclosure greatly reduces the area occupied by the peripheral state register array, simplifies the structure and improves the utilization efficiency of hardware resources.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a non-volatile memory. Background Technology

[0002] The booming development of emerging fields such as automotive electronics, industrial control, and the Internet of Things (IoT) has created a vast market for Nor Flash (a non-volatile flash memory technology) due to their extremely high reliability requirements. Nor Flash is a non-volatile memory, meaning data is not lost when power is off. From the computer age to the mobile internet, and now to the 5G (fifth-generation mobile communication network), automotive, and IoT era, the future of Nor Flash remains vibrant.

[0003] The Status Register (SR) of Nor Flash is the core interface for status interaction between the host and the chip. Its core function is to monitor the chip's operating status in real time, provide feedback on operation results, and manage critical configurations. It uses status bits to implement asynchronous operation polling and waiting, uses suspend and resume flags to ensure the integrity of programming and erasing, and uses write-protection and other status bits to provide secure management of the storage area. It is a necessary hardware foundation for ensuring that Flash can correctly, efficiently, and securely complete read, write, and erase operations.

[0004] Currently, a separate array is typically used around the main memory array of Nor Flash as a peripheral status register array, which occupies a large chip area; or a separate dedicated memory area, different from the main memory array unit, is used as an SR array placed in the peripheral circuit. Although this architecture reduces the area overall, it requires the addition of a separate sense amplifier and Y-direction selector, and also increases the complexity of the operating logic. Utility Model Content

[0005] The technical problem to be solved by this disclosure is to overcome the defect that the peripheral status register array in the prior art requires a large chip area, and to provide a non-volatile memory.

[0006] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0007] This disclosure provides a non-volatile memory, which includes a peripheral array arranged around a memory cell array, and a sensing amplifier, a Y-direction selector and peripheral circuitry are sequentially arranged outside the peripheral array.

[0008] The peripheral circuit includes a peripheral status register array;

[0009] The target global bit line in the memory cell array extends into the peripheral circuitry to be electrically connected to the peripheral status register array, so that the peripheral status register array and the memory cell array share the sensing amplifier and the Y-direction selector.

[0010] Optionally, the distance between the peripheral status register array and the Y-direction selector is less than a preset value.

[0011] Optionally, the preset value is 100 μm (micrometer).

[0012] Optionally, the target global bit line extends vertically into the peripheral circuitry to be electrically connected to the peripheral status register array.

[0013] Optionally, the sensing amplifier includes a clamping transistor whose size is matched to the extension length of the target global bit line.

[0014] Optionally, the global bit line drive voltage of the non-volatile memory is greater than a preset standard value.

[0015] Optionally, the difference between the global bit line drive voltage and the preset standard value ranges from 0.1V to 0.2V.

[0016] Optionally, the non-volatile memory includes Nor Flash.

[0017] The positive improvements of this disclosure are as follows: by using a separate array as the peripheral status register array in the peripheral circuit, the area occupied by the peripheral status register array is greatly reduced, and it shares some global bit lines, sensing amplifiers and Y-direction selectors with the memory cells in the memory cell array, which simplifies the structure and improves the utilization efficiency of hardware resources. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the first architecture of an existing Nor Flash array;

[0019] Figure 2 This is a schematic diagram of the second architecture of an existing Nor Flash array;

[0020] Figure 3 This is a schematic diagram of the structure of the non-volatile memory disclosed in this paper. Detailed Implementation

[0021] The present disclosure will be explained more clearly and completely below with reference to a preferred embodiment and the accompanying drawings.

[0022] Non-volatile memory typically includes a memory cell array, a peripheral array, a peripheral status register array, a sense amplifier, a Y-direction selector, and peripheral circuitry.

[0023] The main array, or memory cell array, is the storage body of the Nor Flash, consisting of a massive number of memory cells arranged in a matrix. The outer array (OA) is the collective name for all the control and logic circuits surrounding the main array that support its operation. The outer array_SR (OA_SR) is a crucial component of the outer array, used to reflect the real-time operating status of the Nor Flash. The sense amplifier (SA) is a core component on the data read path, functioning similarly to an extremely sensitive current / voltage detector and amplifier. The Y-direction selector (YS) is a set of circuits that function as a column address decoder. The global bit line (GBL) is used to transmit data from the selected subarray to the peripheral readout amplifier. The peripheral circuit is a set of circuits that ensures reliable communication and normal operation between the Nor Flash and the main control chip.

[0024] like Figure 1 As shown, the architecture of existing Nor Flash arrays typically places the peripheral status register array as a complete array layer in the peripheral array area, allowing it to share the same operating logic with the memory cell array. However, while achieving logic sharing, this integration method increases the overall chip area, making it unsuitable for the development of smaller chip sizes.

[0025] like Figure 2 As shown, another architecture for Nor Flash arrays integrates the peripheral status register array, sense amplifier, and Y-direction selector into a separate dedicated memory region. This dedicated memory region has a different structure than the memory cell array. By using a separate dedicated memory region, the chip area is reduced to some extent. However, because this dedicated memory region has a different structure from the memory cell array, separate sense amplifiers, Y-direction selectors, and operating logic need to be equipped in both the peripheral array and the dedicated memory region to control the status register, which increases system complexity and resource overhead.

[0026] In view of this, this disclosure provides a control method and system for writing non-volatile memory and its status register, in order to solve the problem that existing peripheral status register arrays require a large chip area and have complex operation logic.

[0027] In one specific embodiment, a non-volatile memory (e.g., Nor Flash) is provided, such as Figure 3 As shown, the non-volatile memory includes a peripheral array 2 arranged around the memory cell array 1, and a sensing amplifier 3, a Y-direction selector 4 and peripheral circuit 5 are arranged sequentially on the outside of the peripheral array 2.

[0028] The peripheral circuit 5 includes a peripheral status register array 6;

[0029] The target global bit line in the memory cell array 1 extends into the peripheral circuit 5 to be electrically connected to the peripheral status register array 6, so that the peripheral status register array 6 and the memory cell array 1 share the sense amplifier 3 and the Y direction selector 4.

[0030] Specifically, in the Nor Flash memory cell array 1, in order to reduce the latency and power consumption of the entire memory cell array 1, the memory cell array 1 is usually divided into multiple sub-arrays. Each sub-array has a corresponding local bit line, which is connected to a metal line that runs through the entire width or length of the chip through a set of global bit line switches.

[0031] To reduce the area occupied by the peripheral status register array 6, the peripheral status register array 6, formed by arranging multiple status registers according to certain rules, is set in the peripheral circuit 5, forming an array architecture consisting of the memory cell array 1, the peripheral array 2, the sensing amplifier 3, the Y-direction selector 4, and the peripheral circuit 5 containing the peripheral status register array 6. The target global bit line in the memory cell array 1 is extended into the peripheral circuit 5 and electrically connected to the peripheral status register array 6. The peripheral status register array 6 and the memory cell array 1 share the sensing amplifier 3 and the Y-direction selector 4 through the target global bit line, realizing the multiplexing of the target global bit line.

[0032] Typically, six target global bit lines are required to be electrically connected to the peripheral status register array 6. Depending on the position of the peripheral status register array 6 in the peripheral circuit 5, six adjacent global bit lines can be selected as target global bit lines. For example, the xth global bit line GBLx to the (x+5th)th global bit line GBLx+5 can be selected as target global bit lines and extended into the peripheral circuit 5 to be electrically connected to the peripheral status register array 6.

[0033] This specific embodiment removes the peripheral status register array (OA_SR) layer between the peripheral array (OA) and the sense amplifier (SA) by placing the peripheral status register array 6 in the peripheral circuit 5. Furthermore, the peripheral status register array 6 does not exist as an independent array, but shares the sense amplifier 3 and Y-direction selector 4 with the memory cell array 1. There is no need to configure the sense amplifier 3 and Y-direction selector 4 for independent use by the peripheral status register array 6, which greatly reduces the area occupied by the peripheral status register array 6, thereby reducing the chip area. In addition, the utilization efficiency of hardware resources is improved by sharing the sense amplifier 3 and Y-direction selector 4.

[0034] In one specific embodiment, the distance between the peripheral status register array 6 and the Y-direction selector 4 is less than a preset value, for example, less than 100 μm. Preferably, the target global bit line extends vertically into the peripheral circuit 5 to be electrically connected to the peripheral status register array 6.

[0035] Specifically, in Nor Flash, such as Figure 1-2 As shown, in order to ensure the flatness of the global bit line, the global bit line usually only connects the memory cell array 1 area and the peripheral array 2 area, and does not cross with the peripheral circuit 5 area, so that the length and load of the global bit line are controllable, resulting in faster access speed.

[0036] like Figure 3 As shown, because the provided non-volatile memory extends the target global bit line and is electrically connected to the peripheral status register array 6 located in the peripheral circuit 5, although the chip area is reduced, it also leads to an increased load on the target global bit line and an increased resistance value. The increased load on the target global bit line slows down the precharge time and sensing time during operation, resulting in a slower chip read speed. The increased resistance value of the global bit line exacerbates the voltage drop on the chip's global bit line during programming, which in turn leads to a lower drain voltage of the memory cell on the extended target global bit line during programming, resulting in reduced programming efficiency.

[0037] Therefore, in this specific embodiment, by placing the peripheral status register array 6 in the peripheral circuit 5 at a distance of less than a preset value from the Y direction selector 4, the peripheral status register array 6 is kept as close as possible to the Y direction selector 4, so that the target global bit line does not extend too long. At the same time, the target global bit line that extends into the peripheral circuit 5 and is electrically connected to the peripheral status register array 6 is kept as vertical as possible and does not bend, so as to minimize the impact of increased load and increased resistance caused by the extension of the target global bit line.

[0038] In one embodiment, the sensing amplifier 3 includes a clamping transistor whose size is matched to the extension length of the target global bit line.

[0039] Specifically, in order to further reduce the impact of increased load and resistance caused by the extension of the target global bit line, the size of the clamping transistor in the sensing amplifier 3 can be increased proportionally to the increase in the length of the target global bit line extension, so as to ensure the sensing speed of the sensing amplifier 3 and adapt to the needs of high-speed reading.

[0040] In one specific implementation, the global bit line drive voltage of the non-volatile memory is greater than a preset standard value.

[0041] Specifically, to further reduce the impact of increased load and resistance caused by the extension of the target global bit line, the global bit line drive voltage during chip programming can be increased to compensate for the voltage of the target global bit line and increase the drain voltage of the memory cell on the target global bit line. The global bit line drive voltage can be provided by a charge pump connected to a voltage regulator, and the set voltage of the voltage regulator can be increased accordingly based on the extension length of the target global bit line; for example, the set voltage of the voltage regulator can be increased from 0.1V to 0.2V.

[0042] In a specific example, for non-volatile memory manufactured using 50nm / 55nm / 65nm process nodes, the preset standard value of its regulator is usually 4V. When the peripheral status register array is set in the peripheral circuit and the target global bit line in the memory cell array is extended to the peripheral circuit and electrically connected to the peripheral status register array, in order to reduce the impact of the increased load and resistance caused by the extension of the target global bit line, the set voltage value of the regulator can be adjusted to 4.1V~4.2V.

[0043] In this embodiment, a separate array is used as the peripheral status register array in the peripheral circuit, which greatly reduces the area occupied by the peripheral status register array. It also shares some global bit lines, sensing amplifiers and Y-direction selectors with the memory cells in the memory cell array, which simplifies the structure and improves the utilization efficiency of hardware resources.

[0044] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. A non-volatile memory, characterized in that, The non-volatile memory includes a peripheral array arranged around the memory cell array, and a sensing amplifier, a Y-direction selector and peripheral circuitry are arranged sequentially on the outside of the peripheral array; The peripheral circuit includes a peripheral status register array; The target global bit line in the memory cell array extends into the peripheral circuitry to be electrically connected to the peripheral status register array, so that the peripheral status register array and the memory cell array share the sensing amplifier and the Y-direction selector.

2. The non-volatile memory according to claim 1, characterized in that, The distance between the peripheral status register array and the Y-direction selector is less than a preset value.

3. The non-volatile memory according to claim 2, characterized in that, The preset value is 100um.

4. The non-volatile memory according to claim 1, characterized in that, The target global bit line extends vertically into the peripheral circuit to be electrically connected to the peripheral status register array.

5. The non-volatile memory according to claim 1, characterized in that, The sensing amplifier includes a clamping transistor whose size is matched to the extension length of the target global bit line.

6. The non-volatile memory according to claim 1, characterized in that, The global bit line drive voltage of the non-volatile memory is greater than a preset standard value.

7. The non-volatile memory according to claim 6, characterized in that, The difference between the global bit line drive voltage and the preset standard value ranges from 0.1V to 0.2V.

8. The non-volatile memory according to claim 1, characterized in that, The non-volatile memory includes NorFlash.

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