Chip read-write protection circuit and electronic device

Abstract

The application provides a chip read-write protection circuit and an electronic device. The chip read-write protection circuit comprises a voltage detection unit and a protection control unit. The voltage detection unit is connected with the chip and is used for detecting the voltage of a power supply pin of the chip and sending a protection action signal when the voltage of the power supply pin is lower than a preset voltage value. The protection control unit is connected with the voltage detection unit, the chip and a read-write controller, is used for forwarding the protection action signal to the read-write controller, and is used for outputting a protection signal to the chip according to the protection action signal and an enable signal from the read-write controller. The application outputs the protection action signal to the read-write controller when the voltage of the power supply pin of the chip changes to the preset voltage value, and outputs the protection signal according to the protection action signal and the enable signal of the read-write controller, so that the chip is protected by the protection signal, and the protection effect on the chip is improved.

Description

Technical Field

[0001] This application belongs to the field of chip protection technology, and in particular relates to a chip read / write protection circuit and electronic device. Background Technology

[0002] Ferroelectric RAM (FRAM) combines non-volatility and random access characteristics, but its normal operation requires high stability of the power supply pin voltage. Because data reading is destructive, a stable power supply is needed to support automatic rewriting and data recovery after reading and writing. Abnormal voltage can easily lead to data errors or loss.

[0003] In related technologies, electronic devices often encounter power outages, voltage drops, or power failures. At this time, the voltage of the power supply pin drops below the minimum operating voltage of the FRAM, and the chip cannot complete the data rewriting. It may also damage the data due to voltage timing disorder. If the FRAM is reading or writing when the power is off, the termination of the operation will disrupt the polarization of the storage cell and increase the risk of data loss. Summary of the Invention

[0004] The purpose of this application is to provide a chip read / write protection circuit and electronic device, which aims to solve the problem that chips are prone to data loss due to power failure in traditional technologies.

[0005] The first aspect of this application provides a chip read / write protection circuit, including: A voltage detection unit, connected to the chip, is used to detect the voltage of the chip's power supply pins, and sends a protection action signal when the voltage of the power supply pins is lower than a preset voltage value; The protection control unit is connected to the voltage detection unit, the chip, and the read / write controller. It is used to forward the protection action signal to the read / write controller and to output a protection signal to the chip based on the protection action signal and the enable signal from the read / write controller.

[0006] In some embodiments of this application, the voltage detection unit includes a comparator or a voltage monitoring chip. The comparator or the voltage monitoring chip includes a power supply input terminal connected to an external power supply, a detection voltage input terminal connected to the chip, and a protection action signal output terminal.

[0007] In some embodiments of this application, the protection control unit includes a logic gate circuit, a buffer and an inverter respectively connected to the logic gate circuit; the logic gate circuit includes a protection action signal input terminal connected to the voltage detection unit and an enable signal input terminal connected to the read / write controller; the buffer includes a WP protection signal output terminal connected to the chip; and the inverter includes a CS protection signal output terminal connected to the chip.

[0008] In some embodiments of this application, the voltage detection unit includes a first voltage detection unit and a second voltage detection unit. The first voltage detection unit is used to send a first protection action signal when the voltage of the power supply pin is lower than a first preset voltage value; the second voltage detection unit is used to send a second protection action signal when the voltage of the power supply pin is lower than a second preset voltage value; wherein, the first preset voltage value is greater than the second preset voltage value. When the protection control unit receives the first protection action signal, it forwards the first protection action signal to the read / write controller; and when the protection control unit receives the second protection action signal, it forwards the second protection action signal to the read / write controller, and outputs a first protection signal to the chip according to the second protection action signal and the enable signal from the read / write controller.

[0009] In some embodiments of this application, the first voltage detection unit includes a first comparator, which includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal is used to connect to the voltage of the power supply pin, the second input terminal is used to connect to the first preset voltage, the first preset voltage is used to characterize the first preset voltage value, and the first output terminal is used to output the first protection action signal. The second voltage detection unit includes a second comparator, which includes a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is used to connect to the power supply pin voltage, the fourth input terminal is used to connect to the second preset voltage, the second preset voltage is used to characterize the second preset voltage value, and the second output terminal is used to output the second protection action signal.

[0010] In some embodiments of this application, the protection control unit includes a first subunit and a second subunit. The first subunit includes a first buffer, which includes a first protection action signal input terminal connected to the first voltage detection unit and a signal forwarding output terminal connected to the read / write controller. The second sub-unit includes a first logic gate circuit, a second buffer connected to the first logic gate circuit, and a first inverter; the first logic gate circuit includes a second protection action signal input terminal connected to the second voltage detection unit and an enable signal input terminal connected to the read / write controller; the second buffer includes a WP protection signal output terminal connected to the chip; and the first inverter includes a CS protection signal output terminal connected to the chip.

[0011] In some embodiments of this application, the voltage detection unit further includes a third voltage detection unit, which is used to connect to the chip to obtain the power supply pin voltage of the chip. When the power supply pin voltage is lower than a third preset voltage value, a third protection action signal is output; the third preset voltage is less than the second preset voltage. When the protection control unit receives the third protection action signal, it forwards the third protection action signal to the read / write controller, and outputs a first protection signal to the chip according to the third protection action signal and the enable signal from the read / write controller.

[0012] In some embodiments of this application, the protection control unit includes a third subunit and a fourth subunit. The third subunit includes a third buffer, which includes a first protection action signal input terminal connected to the first voltage detection unit and a signal forwarding output terminal connected to the read / write controller. The fourth subunit includes a second logic gate circuit, a third logic gate circuit, a fourth buffer, and a second inverter, wherein the second logic gate circuit is connected to the third logic gate circuit and the fourth buffer respectively, and the third logic gate circuit is connected to the second inverter. The second logic gate circuit includes a second protection action signal input terminal connected to the second voltage detection unit and a first enable signal input terminal connected to the read / write controller; the third logic gate circuit includes a third protection action signal input terminal connected to the third voltage detection unit. The fourth buffer includes a WP protection signal output terminal connected to the chip, and the second inverter includes a CS protection signal output terminal connected to the chip.

[0013] In some embodiments of this application, the chip read / write protection circuit further includes an energy storage unit, which is used to supply power to the chip when the power supply drops to a set voltage; the energy storage unit includes an energy storage capacitor, one end of which is grounded and the other end is used to connect to the chip; the power supply is connected between the energy storage capacitor and the chip to charge the energy storage capacitor.

[0014] A second aspect of this application also provides an electronic device, the electronic device comprising the chip read / write protection circuit as described above, the chip, and the read / write controller; the read / write controller is configured to send a second protection signal to the chip when receiving the protection action signal, or to send an enable signal to the protection control unit when receiving the protection action signal; the chip is configured to stop reading / writing when receiving the first protection signal, or the first protection signal and the second protection signal, wherein the first protection signal is a hardware limit signal, and the second protection signal is a software stop signal.

[0015] The beneficial effects of this application are as follows: In the chip read / write protection circuit and electronic device of this application, the chip read / write protection circuit includes a voltage detection unit and a protection control unit. The voltage detection unit is connected to the chip and is used to detect the voltage of the chip's power supply pin. When the voltage of the power supply pin is lower than a preset voltage value, a protection action signal is sent. The protection control unit is connected to the voltage detection unit, the chip, and the read / write controller. It is used to forward the protection action signal to the read / write controller and to output a protection signal to the chip based on the protection action signal and the enable signal from the read / write controller. This application protects the chip by outputting a protection action signal to the read / write controller when the voltage of the chip's power supply pin changes to a preset voltage value, and outputting a protection signal based on the protection action signal and the enable signal from the read / write controller. This protection signal helps to improve the protection effect of the chip. Attached Figure Description

[0016] Figure 1 A schematic diagram of the framework structure of a chip read / write protection circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a comparator provided in an embodiment of this application; Figure 3 This is another schematic diagram of the comparator provided in one embodiment of the present application; Figure 4 This is a schematic diagram of the structure of a protection control unit provided in an embodiment of this application; Figure 5 A schematic diagram of the framework structure of a chip read / write protection circuit provided in an embodiment of this application; Figure 6 A schematic diagram of the circuit structure of a first voltage detection unit provided in an embodiment of this application; Figure 7 A schematic diagram of the circuit structure of the second voltage detection unit provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of the first subunit provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of the second subunit provided in an embodiment of this application; Figure 10 A schematic diagram of the framework structure of a chip read / write protection circuit provided in another embodiment of this application; Figure 11 This is a schematic diagram of the structure of the third subunit provided in an embodiment of this application; Figure 12 This is a schematic diagram of the structure of the fourth subunit provided in an embodiment of this application; Figure 13 A schematic diagram of the framework structure of a chip read / write protection circuit provided in another embodiment of this application; Figure 14 This is a schematic diagram of the circuit structure of a chip read / write protection circuit provided in an embodiment of this application.

[0017] Specific element symbol explanations: 10-Power supply, 20-Chip, 30-Chip read / write protection circuit, 100-Voltage detection unit, 110-First voltage detection unit, 120-Second voltage detection unit, 200-Read / write controller, 300-Protection control unit, 400-Third voltage detection unit, 500-Energy storage unit, C-Energy storage capacitor, 1-First input terminal, 2-Second input terminal, 3-First output terminal, 4-Third input terminal, 5-Fourth input terminal, 6-Second output terminal, R1-First voltage divider resistor, R 2 - Second voltage divider resistor, R3 - Third voltage divider resistor, R4 - Fourth voltage divider resistor, VDD - Power supply pin voltage, U - Logic gate circuit, U1 - First comparator, U2 - Second comparator, U3 - First logic gate circuit, U4 - Second logic gate circuit, U5 - Third logic gate circuit, BUF - Buffer, BUF1 - First buffer, BUF2 - Second buffer, BUF3 - Third buffer, BUF4 - Fourth buffer, INV - Inverter, INV1 - First inverter, INV2 - Second inverter. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] It's important to know that Ferroelectric RAM (FRAM) is a type of memory that combines non-volatility and random access characteristics. It utilizes the polarization properties of ferroelectric materials to achieve data storage and can be applied in computers, industrial control equipment, and smart terminals. The advantages of FRAM include fast data read / write speeds, long erase / write lifespan, and no need for an external backup power supply. However, the normal operation of an FRAM chip is highly dependent on the stability of the power supply pin voltage. Because reading data is destructive, the chip's internal circuitry must automatically rewrite and recover the data after each read / write operation. This process relies on a stable power supply pin voltage. Fluctuations or abnormalities in the power supply pin voltage can easily cause the automatic rewrite and recovery process to fail, leading to data errors or loss.

[0022] In practical applications, computers and various electronic devices often face abnormal situations such as momentary power outages, slow voltage drops, or sudden power failures. When a power supply fails, the voltage at the power supply pins will first drop rapidly below the minimum operating voltage threshold of the FRAM chip. At this time, the chip will not only be unable to automatically rewrite and recover the data, but may also cause internal circuit logic errors due to voltage timing disorder, resulting in permanent damage to the stored data. Secondly, if the FRAM chip is in the process of data read / write operation before the power failure, the sudden interruption of power supply will force the read / write operation to terminate. The unfinished operation may disrupt the polarization state of the chip's internal memory cells, further increasing the risk of data loss.

[0023] Based on this, this application improves the chip read / write protection circuit, chip, and electronic device in the related technology.

[0024] Please see Figure 1 , Figure 1A schematic diagram of the framework structure of the chip read / write protection circuit 30 provided in this application embodiment is shown. The chip read / write protection circuit in this application embodiment includes a voltage detection unit 100 and a protection control unit 300. The voltage detection unit 100 is connected to the chip 20 and is used to detect the power supply pin voltage VDD of the chip 20. When the power supply pin voltage VDD is lower than a preset voltage value, a protection action signal is sent. The protection control unit 300 is connected to the voltage detection unit 100, the chip 20 and the read / write controller 200. It is used to forward the protection action signal to the read / write controller 200 and to output a protection signal to the chip 20 according to the protection action signal and the enable signal from the read / write controller 200.

[0025] It should be explained that the chip read / write protection circuit 30 is an electronic circuit used to monitor the power supply status of chip 20 and trigger protection actions when the power supply is abnormal, preventing chip 20 from being damaged or malfunctioning due to power supply abnormalities (such as undervoltage or overvoltage). The voltage detection unit 100 is a functional unit responsible for monitoring the power supply voltage of chip 20, and can collect the voltage signal of the power supply pins of chip 20 in real time. The protection control unit 300 can transmit the protection action signal output by the voltage detection unit 100 to the read / write controller 200, and simultaneously combine it with the enable signal of the read / write controller 200 to generate a protection signal that meets the interface requirements of chip 20. The read / write controller 200 is a control module that performs read / write operations on chip 20, typically an MCU, CPU, or dedicated control chip 20. It can receive the protection action signal forwarded by the protection control unit 300, stop sending read / write commands to chip 20, and simultaneously output an enable signal to the protection control unit 300.

[0026] The protection action signal is an electrical signal output by the voltage detection unit 100 when it detects that the supply voltage of chip 20 is lower than a preset value. It is used to inform the protection control unit 300 and the read / write controller 200 that the current power supply is abnormal and the protection process needs to be initiated. The signal form can be high / low level, pulse signal, etc. The protection signal is an instruction signal generated by the protection control unit 300 based on the protection action signal and the enable signal of the read / write controller 200. It directly acts on key pins of chip 20, such as chip select and write protection, to restrict the read / write function of chip 20 at the hardware level, avoiding invalid read / write operations when the power supply is abnormal.

[0027] It is understood that the voltage detection unit 100 in this application is directly connected to the power supply pin of chip 20, which can capture voltage fluctuations in real time. The protection control unit 300 processes the signal and outputs protection commands through hardware logic, without relying on the execution delay of the software program. This is beneficial for quickly blocking abnormal read and write operations and avoiding data loss due to automatic rewriting failure of chip 20 when the power supply voltage drops suddenly. Specifically, once the voltage detection unit 100 detects that the voltage is lower than the preset value, it can quickly output a protection action signal. The protection control unit 300 directly generates a protection signal through logic gate circuits and acts on the chip select and write protection pins of chip 20, immediately restricting read and write at the hardware level. If a power supply short circuit causes the power supply of chip 20 to drop rapidly, the voltage detection unit 100 quickly triggers protection, and the protection control unit 300 synchronously outputs a protection signal to prevent the FRAM from performing automatic rewriting when the voltage is close to the minimum operating voltage.

[0028] In some embodiments of this application, please refer to Figure 2 and Figure 3 , Figure 2 A schematic diagram of the comparator provided in this embodiment is shown. Figure 3 Another structural schematic diagram of the comparator provided in this embodiment is shown; the voltage detection unit 100 of this embodiment includes a comparator or voltage monitoring chip 20, the comparator or voltage monitoring chip 20 includes a power supply input terminal connected to an external power supply 10, a detection voltage input terminal connected to the chip 20, and a protection action signal output terminal.

[0029] In some embodiments of this application, please refer to Figure 4 , Figure 4 A schematic diagram of the protection control unit provided in this embodiment is shown. The protection control unit 300 in this embodiment includes a logic gate circuit U, and a buffer BUF and an inverter INV respectively connected to the logic gate circuit U. The logic gate circuit U includes a protection action signal input terminal connected to the voltage detection unit 100 and an enable signal input terminal connected to the read / write controller 200. The buffer BUF includes a WP protection signal output terminal connected to the chip 20, and the inverter INV includes a CS protection signal output terminal connected to the chip 20.

[0030] In some embodiments of this application, please refer to Figure 5 , Figure 5A schematic diagram of the chip read / write protection circuit provided in this embodiment is shown. The voltage detection unit 100 in this embodiment includes a first voltage detection unit 110 and a second voltage detection unit 120. The first voltage detection unit 110 is used to send a first protection action signal when the power supply pin voltage VDD is lower than a first preset voltage value. The second voltage detection unit 120 is used to send a second protection action signal when the power supply pin voltage VDD is lower than a second preset voltage value. The first preset voltage value is greater than the second preset voltage value. When the protection control unit 300 receives the first protection action signal, it forwards the first protection action signal to the read / write controller 200. When the protection control unit 300 receives the second protection action signal, it forwards the second protection action signal to the read / write controller 200, and outputs a first protection signal to the chip 20 according to the second protection action signal and the enable signal from the read / write controller 200.

[0031] It should be explained that the first voltage detection unit 110 is a functional module in the chip read / write protection circuit 30 used for preliminary monitoring of the power supply pin voltage VDD. It obtains the real-time power supply pin voltage VDD by connecting to the power supply 10. When the voltage is lower than a first preset voltage value (a higher undervoltage threshold), it outputs a first protection action signal, which is a key sensing component for triggering the primary protection of the chip 20. The second voltage detection unit 120 is a voltage monitoring module that works in conjunction with the first voltage detection unit 110. It is also connected to the power supply 10 to obtain the power supply pin voltage VDD. When the voltage is lower than a lower second preset voltage value (a deeper undervoltage threshold), it outputs a second protection action signal to trigger a higher level of protection for the chip 20.

[0032] The first preset voltage value is the undervoltage judgment threshold set by the first voltage detection unit 110. This voltage value is close to the lower limit of the normal operating voltage of chip 20. When the power supply pin voltage VDD drops below this value, it indicates that the power supply is abnormal and primary protection needs to be activated to prevent the performance of chip 20 from being affected. The second preset voltage value is the deep undervoltage judgment threshold set by the second voltage detection unit 120. When the power supply pin voltage VDD drops below this value, it indicates that the power supply is severely abnormal and more stringent protection needs to be activated to avoid hardware damage to chip 20. The protection action triggered by the first protection action signal provides weak protection for chip 20 and is usually used to adjust the operating state of chip 20 to deal with minor undervoltage. The first protection signal is a deep protection command output by the protection control unit 300 based on the second protection action signal. It provides strong protection for chip 20 and is usually used to suspend unnecessary operation of chip 20 to avoid hardware damage caused by deep undervoltage.

[0033] It is understandable that the dual voltage detection unit and graded protection signals in this embodiment are beneficial for dealing with the dynamic changes in the power supply pin voltage VDD during power-on and power-off, and avoid damage to chip 20 caused by timing abnormalities. During the power-on phase of chip 20, the voltage of the power supply 10 gradually increases from low to high. If the voltage does not reach the threshold required for chip 20 to start but a working command is triggered, timing disorder is likely to occur. During the power-off phase, the voltage decreases from high to low. If the voltage drops to the critical value and chip 20 is still operating at full load, internal circuit timing errors are likely to occur. However, in this embodiment, the first voltage detection unit 110 outputs a first protection action signal when the voltage is lower than the first preset voltage value (close to the normal operating lower limit), avoiding timing deviations caused by voltage instability in the early stage of power-on or slight undervoltage in the early stage of power-off. When the voltage further drops to the second preset voltage value (close to the functional critical value), the second detection unit triggers the first protection signal (such as pausing data read / write or locking the memory unit) to prevent timing disorder under deep undervoltage.

[0034] Specifically, the internal storage units (such as caches and registers) of the computer chip 20 have extremely high requirements for the stability of the power supply pin voltage VDD. Slight undervoltage may lead to data read / write errors, while deep undervoltage may directly erase the stored data. In this embodiment, the first protection signal prevents data loss due to storage circuit malfunctions caused by deep undervoltage by locking the storage unit and stopping data update operations. For example, during a computer power outage, when the power supply pin voltage VDD drops to a second preset voltage, the first protection signal locks the storage unit read / write interface to prevent voltage fluctuations at the moment of power failure from rewriting or erasing data, effectively reducing the risk of data loss during power-on and power-off processes and ensuring computer data security.

[0035] In some embodiments, the power supply pins of chip 20 are powered by the power supply 10. The power supply 10 is a power module that provides operating power to chip 20 and can output a stable DC voltage. The voltage VDD of its output power supply pins must be maintained within the allowable operating voltage range of chip 20; otherwise, it may cause abnormal performance of chip 20 or hardware damage.

[0036] In some embodiments of this application, the first voltage detection unit 110 includes a first comparator U1 or a first voltage monitoring chip 20.

[0037] In some embodiments, the second voltage detection unit 120 includes a second comparator U2 or a second voltage monitoring chip 20.

[0038] In some embodiments of this application, please refer to Figure 6 , Figure 6A schematic diagram of the circuit structure of the first voltage detection unit 110 provided in this embodiment is shown. The first voltage detection unit 110 in this embodiment includes a first comparator U1, which includes a first input terminal 1, a second input terminal 2 and a first output terminal 3. The first input terminal 1 is used to connect to the power supply pin voltage VDD, the second input terminal 2 is used to connect to a first preset voltage, the first preset voltage is used to characterize the first preset voltage value, and the first output terminal 3 is used to output a first protection action signal.

[0039] Understandably, the first comparator U1, through direct comparison of the voltages at its two input terminals, can accurately determine whether the power supply pin voltage VDD is lower than the first preset voltage value, avoiding false or missed protection triggers due to detection deviations. During power-up and power-down processes, the power supply pin voltage VDD of chip 20 needs to be maintained within a stable range to ensure the safety of internal data storage. The first input terminal 1 of the first comparator U1 is directly connected to the power supply pin voltage VDD, enabling it to capture minute voltage changes in real time; the second input terminal 2 is connected to a fixed first preset voltage, forming a stable judgment benchmark. When the power supply pin voltage VDD is normal (higher than the first preset voltage value), the output terminal of the first comparator U1 maintains its initial level and does not trigger protection; when the power supply pin voltage VDD drops below the first preset voltage value due to power-up / down timing fluctuations or power supply abnormalities, the first comparator U1 immediately outputs a first protection action signal through a level transition, accurately identifying power supply abnormalities.

[0040] Please refer to the embodiments described in this application. Figure 6 The first voltage detection unit 110 in this embodiment includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series. The first voltage divider resistor R1 is used to connect to the power supply pin voltage VDD, and the second voltage divider resistor R2 is used to ground. The first input terminal 1 is connected between the first voltage divider resistor R1 and the second voltage divider resistor R2.

[0041] Understandably, the series voltage divider setup can reduce the power supply pin voltage VDD to the compatible input range of the first comparator U1, preventing damage to the first comparator U1 due to excessively high power supply pin voltage VDD, while simultaneously meeting detection requirements. Specifically, the first voltage divider resistor R1 and the second voltage divider resistor R2 form a series voltage divider circuit. By adjusting the resistance ratio of the two resistors (e.g., the resistance of the first voltage divider resistor R1 is greater than that of the second voltage divider resistor R2), the high power supply pin voltage VDD (e.g., 12V) can be proportionally reduced to the low voltage range (e.g., 3.3V, 5V) compatible with the first comparator U1. This ensures that the first comparator U1 can safely receive voltage signals and also allows the actual power supply pin voltage VDD to be calculated in reverse using the voltage divider ratio, enabling indirect monitoring of the power supply pin voltage VDD. This solves the problem of mismatch between the power supply pin voltage VDD and the comparator input range, meeting the monitoring requirements of different power supply specifications 10 in the adaptation document.

[0042] In some embodiments of this application, please refer to Figure 7 , Figure 7 A schematic diagram of the circuit structure of the second voltage detection unit 120 provided in this embodiment is shown. The second voltage detection unit 120 in this embodiment includes a second comparator U2, which includes a third input terminal 4, a fourth input terminal 5, and a second output terminal 6. The third input terminal 4 is used to connect to the power supply pin voltage VDD, the fourth input terminal 5 is used to connect to a second preset voltage, the second preset voltage is used to characterize the second preset voltage value, and the second output terminal 6 is used to output a second protection action signal.

[0043] Understandably, in the event of a power outage, the power supply pin voltage VDD gradually decreases from its normal level. When the voltage drops below the first preset voltage, primary protection is triggered. If the voltage continues to drop to the second preset voltage, deep undervoltage protection is triggered. The third input terminal 4 of the second comparator U2 is directly connected to the power supply pin voltage VDD, which can capture subtle voltage drop trends in real time. The fourth input terminal 5 is connected to a fixed second preset voltage, forming a stable deep undervoltage judgment benchmark, unaffected by power supply fluctuations or circuit interference.

[0044] Please refer to the embodiments described in this application. Figure 7 The second voltage detection unit 120 includes a third voltage divider resistor R3 and a fourth voltage divider resistor R4 connected in series. The third voltage divider resistor R3 is used to connect to the power supply pin voltage VDD, and the fourth voltage divider resistor R4 is used to ground. The second input terminal 2 is connected between the third voltage divider resistor R3 and the fourth voltage divider resistor R4.

[0045] In some embodiments of this application, please refer to Figure 8 and Figure 9 , Figure 8 This diagram illustrates the structure of the first subunit provided in this embodiment. Figure 9 A schematic diagram of the structure of the second subunit provided in this embodiment is shown. The protection control unit 300 of this embodiment includes a first subunit and a second subunit. The first subunit includes a first buffer BUF1, which includes a first protection action signal input terminal connected to the first voltage detection unit 110 and a signal forwarding output terminal connected to the read / write controller 200. The second subunit includes a first logic gate circuit U3, a second buffer BUF2 connected to the first logic gate circuit U3, and a first inverter INV1. The first logic gate circuit U3 includes a second protection action signal input terminal connected to the second voltage detection unit 120 and an enable signal input terminal connected to the read / write controller 200. The second buffer BUF2 includes a WP protection signal output terminal connected to the chip 20, and the first inverter INV1 includes a CS protection signal output terminal connected to the chip 20.

[0046] In some embodiments of this application, the read / write controller 200 is used to control the software to stop reading and writing the chip 20 based on a first protection action signal. The first protection signal is used to shut down the first pin and / or the second pin of the chip 20. The first pin is the pin for writing data to the chip 20, and the second pin is the pin for reading data from the chip 20.

[0047] It should be explained that "software stop reading / writing to chip 20" refers to a triggered software-level operation, such as pausing the read / write enable signals of the internal data storage modules (e.g., cache, registers) of chip 20, or interrupting communication on the data transmission bus. This ensures that when the power supply pin voltage VDD is lower than a first preset voltage but not severely undervoltage, chip 20 will not perform new data writing or reading, preventing read / write failures caused by unstable power supply. The first pin can be the WP (write) pin, and the second pin can be the CS (read) pin.

[0048] It is understandable that in this embodiment, by pausing data read / write instructions and interrupting bus communication, the core power supply and basic functions of chip 20 are not affected, thus preventing read / write timing deviations caused by unstable power supply (such as data writing misalignment or read value error). This avoids functional interruption caused by hardware shutdown directly triggered by initial slight undervoltage. When the power supply pin voltage VDD further drops to the second preset voltage (deep undervoltage), the first protection signal directly shuts down the first and second pins, cutting off the physical path of data read / write at the hardware level. Even if there is a delay or abnormality in software control, data transmission can be completely blocked by shutting down the pins, preventing internal data tampering or loss caused by hardware circuit disorder of chip 20 under deep undervoltage.

[0049] In some embodiments of this application, please refer to Figure 10 , Figure 10 A schematic diagram of the framework structure of the chip read / write protection circuit 30 provided in this embodiment is shown. The voltage detection unit 100 in this embodiment also includes a third voltage detection unit 400. The third voltage detection unit 400 is used to connect to the chip 20 to obtain the power supply pin voltage VDD of the chip 20. When the power supply pin voltage VDD is lower than a third preset voltage value, a third protection action signal is output. The third preset voltage is less than a second preset voltage. When the protection control unit 300 receives the third protection action signal, it forwards the third protection action signal to the read / write controller 200, and outputs a first protection signal to the chip 20 according to the third protection action signal and the enable signal from the read / write controller 200.

[0050] It should be explained that the third voltage detection unit 400 works in conjunction with the first voltage detection unit 110 and the second voltage detection unit 120. The third preset voltage value is the undervoltage judgment threshold set by the third voltage detection unit 400. The third protection action signal is the undervoltage judgment signal output by the third voltage detection unit 400, which is generated when the power supply pin voltage VDD is lower than the third preset voltage value.

[0051] Understandably, during a power outage, the power supply pin voltage VDD may gradually decrease from the normal level to the first preset voltage value, the second preset voltage value, and the third preset voltage value. The third voltage detection unit 400, by monitoring the even lower third preset voltage value, can accurately capture this extreme state and output a third protection action signal, ensuring that the protection control unit 300 promptly activates a higher level of protection. The setting of the second protection signal enables the chip 20 to form a complete ladder of "primary protection - intermediate protection - advanced protection," allowing for the matching of the most suitable protection measures according to the degree of power supply anomaly, avoiding over-protection or under-protection.

[0052] In some embodiments of this application, please refer to Figure 11 and Figure 12 , Figure 11 This embodiment shows a schematic diagram of the structure of the third subunit. Figure 12 A schematic diagram of the structure of the fourth subunit provided in this embodiment is shown. The protection control unit 300 of this embodiment includes a third subunit and a fourth subunit. The third subunit includes a third buffer BUF3, which includes a first protection action signal input terminal connected to the first voltage detection unit 110 and a signal forwarding output terminal connected to the read / write controller 200. The fourth subunit includes a second logic gate circuit U4, a third logic gate circuit U5, a fourth buffer BUF4, and a second inverter INV2. The second logic gate circuit U4 is connected to both the third logic gate circuit U5 and the fourth buffer BUF4, and the third logic gate circuit U5 is connected to the second inverter INV2. The second logic gate circuit U4 includes a second protection action signal input terminal connected to the second voltage detection unit 120 and a first enable signal input terminal connected to the read / write controller 200. The third logic gate circuit U5 includes a third protection action signal input terminal connected to the third voltage detection unit 400. The fourth buffer BUF4 includes a WP protection signal output terminal connected to the chip 20, and the second inverter INV2 includes a CS protection signal output terminal connected to the chip 20.

[0053] In some embodiments of this application, the read / write controller 200 is used to control the software to stop reading and writing the chip 20 based on a first protection action signal. The first protection signal is used to shut down the first pin, or to shut down the first pin and the second pin of the chip 20.

[0054] It is understandable that the power supply pin voltage VDD may fluctuate slightly due to the instability of the power module startup (below the first preset voltage value). Reading and writing are stopped by software to avoid data errors caused by timing deviations without affecting the basic power supply of chip 20. As the power supply drops further (below the second preset voltage value), the first protection signal shuts down the first pin, blocking data writing at the hardware level to prevent external modules from forcibly writing erroneous data. When the power supply is extremely abnormal (below the third preset voltage value), the first protection signal shuts down both pins at the same time, completely cutting off the data interaction path and preventing chip 20 from internal data corruption due to circuit disorder.

[0055] In some embodiments of this application, please refer to Figure 13 , Figure 13 A schematic diagram of the framework structure of the chip read / write protection circuit 30 provided in this embodiment is shown. The chip read / write protection circuit 30 in this embodiment also includes an energy storage unit 500, which is used to supply power to the chip 20 when the power supply 10 drops to a set voltage.

[0056] It should be explained that the energy storage unit 500 is a functional module in the chip read / write protection circuit 30 used for temporary energy storage. It is typically composed of components such as the energy storage capacitor C. When the power supply 10 loses power and the voltage drops to a set voltage, the energy storage capacitor C can replace the power supply 10 to provide short-term, stable power to the chip 20, preventing data loss or hardware damage to the chip 20 due to sudden power failure. The set voltage is the trigger threshold voltage for the energy storage unit 500 to start supplying power. This voltage value must be higher than the critical voltage at which the chip 20 cannot maintain its basic functions, but lower than the normal output voltage of the power supply 10. When the power supply 10 loses power and the voltage drops to this value, the energy storage unit 500 automatically switches to become the power source for the chip 20, ensuring uninterrupted power supply switching.

[0057] Understandably, when the power supply 10 drops to a set voltage, the energy storage unit 500 can immediately supply power to the chip 20, ensuring that the chip 20 can still maintain the normal operation of its core functions (such as data read / write pause and pin shutdown) after power failure. For example, when the computer's main power supply suddenly fails and the power supply pin voltage VDD drops rapidly from 12V to a set voltage (such as 8V), the energy storage unit 500 immediately starts to provide continuous power to the chip 20, preventing the data storage circuit of the chip 20 from becoming disordered due to power loss.

[0058] In some embodiments of this application, please refer to Figure 14 , Figure 14A schematic diagram of the circuit structure of the chip read / write protection circuit 30 provided in this embodiment is shown. The energy storage unit 500 in this embodiment includes an energy storage capacitor C, one end of which is grounded and the other end is used to connect to the chip 20. The power supply 10 is connected between the energy storage capacitor C and the chip 20 to charge the energy storage capacitor C.

[0059] Understandably, after the computer is powered on, the power supply 10 needs to supply power to both the chip 20 and the energy storage capacitor C. In this embodiment, part of the electrical energy output by the power supply 10 is directly supplied to the chip 20 to maintain normal operation, and the other part flows to the energy storage capacitor C to complete charging. When the power supply 10 loses power, the voltage of the power supply 10 will drop rapidly, and since the energy storage capacitor C is directly connected to the chip 20, it can supply power to the chip 20 through the discharge circuit at the moment the power supply 10 loses power; the electric field energy stored in the energy storage capacitor C is quickly converted into electrical energy and output through the end connected to the chip 20, ensuring uninterrupted power supply to the core circuit of the chip 20.

[0060] In some embodiments, the inverter main control board experienced a problem of missing parameters of the FRAM chip 20 during laboratory testing and some field use. The actual power supply provided by the power supply board is 5V, which is stepped down to 3.3V after passing through the LDO chip 20 to power the MCU and other controllers, the FRAM chip 20, and other peripheral circuits.

[0061] This application embodiment adds monitoring of the 3.3V voltage and read / write protection function for the FRAM chip 20 based on the above solution. When the 3.3V voltage is lower than 3V (such as the preset voltage), a protection signal is triggered. After receiving the protection signal, the external protection circuit processes it through the logic gate circuit and pulls the CS pin and WP pin of the FRAM chip 20 to the protection state respectively to avoid reading and writing to the chip 20 when the power is off. In actual testing, after adding the above circuit, no parameter loss occurred again after about 2500 power cycles.

[0062] Based on the above scheme, this embodiment increases the voltage detection from a single level to a multi-level level. For example, the first level of protection is set when the voltage is below 3.2V. The signal is transmitted to the controller such as the MCU, and the protection is triggered by the software to stop reading and writing to the FRAM. At this time, the external hardware protection circuit does not operate. When the voltage continues to drop and falls below 3V, the external hardware protection circuit is triggered to avoid the problem of FRAM parameter loss in the event of software failure.

[0063] Furthermore, in order to better implement the chip read / write protection circuit in any of the above embodiments, based on the above chip read / write protection circuit, this application also provides an electronic device, which includes the chip 20 read / write protection circuit as described above, as well as chip 20 and read / write controller 200; the read / write controller 200 is used to send a second protection signal to chip 20 when a protection action signal is received, or to send an enable signal to protection control unit 300 when a protection action signal is received; chip 20 is used to stop reading and writing when a first protection signal, or a first protection signal and a second protection signal are received, wherein the first protection signal is a hardware limit signal, the second protection signal is a software stop signal, and the read / write controller 200 is a controller such as an MCU, and chip 20 is an FRAM chip.

[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0065] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0066] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0067] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0068] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A chip read / write protection circuit, characterized in that, include: A voltage detection unit, connected to the chip, is used to detect the voltage of the chip's power supply pins, and sends a protection action signal when the voltage of the power supply pins is lower than a preset voltage value; The protection control unit is connected to the voltage detection unit, the chip, and the read / write controller. It is used to forward the protection action signal to the read / write controller and to output a protection signal to the chip based on the protection action signal and the enable signal from the read / write controller.

2. The chip read / write protection circuit according to claim 1, characterized in that, The voltage detection unit includes a comparator or a voltage monitoring chip. The comparator or the voltage monitoring chip includes a power input terminal connected to an external power supply, a detection voltage input terminal connected to the chip, and a protection action signal output terminal.

3. The chip read / write protection circuit according to claim 2, characterized in that, The protection control unit includes logic gate circuits, and buffers and inverters respectively connected to the logic gate circuits; the logic gate circuits include a protection action signal input terminal connected to the voltage detection unit and an enable signal input terminal connected to the read / write controller; the buffers include a WP protection signal output terminal connected to the chip; and the inverters include a CS protection signal output terminal connected to the chip.

4. The chip read / write protection circuit according to claim 1, characterized in that, The voltage detection unit includes a first voltage detection unit and a second voltage detection unit. The first voltage detection unit is used to send a first protection action signal when the voltage of the power supply pin is lower than a first preset voltage value. The second voltage detection unit is used to send a second protection action signal when the voltage of the power supply pin is lower than a second preset voltage value. The first preset voltage value is greater than the second preset voltage value. When the protection control unit receives the first protection action signal, it forwards the first protection action signal to the read / write controller; and when the protection control unit receives the second protection action signal, it forwards the second protection action signal to the read / write controller, and outputs a first protection signal to the chip according to the second protection action signal and the enable signal from the read / write controller.

5. The chip read / write protection circuit according to claim 4, characterized in that, The first voltage detection unit includes a first comparator, which includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal is used to connect to the voltage of the power supply pin, the second input terminal is used to connect to the first preset voltage, the first preset voltage is used to characterize the first preset voltage value, and the first output terminal is used to output the first protection action signal. The second voltage detection unit includes a second comparator, which includes a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is used to connect to the power supply pin voltage, the fourth input terminal is used to connect to the second preset voltage, the second preset voltage is used to characterize the second preset voltage value, and the second output terminal is used to output the second protection action signal.

6. The chip read / write protection circuit according to claim 5, characterized in that, The protection control unit includes a first subunit and a second subunit. The first subunit includes a first buffer, which includes a first protection action signal input terminal connected to the first voltage detection unit and a signal forwarding output terminal connected to the read / write controller. The second sub-unit includes a first logic gate circuit, a second buffer connected to the first logic gate circuit, and a first inverter; the first logic gate circuit includes a second protection action signal input terminal connected to the second voltage detection unit and an enable signal input terminal connected to the read / write controller; the second buffer includes a WP protection signal output terminal connected to the chip; and the first inverter includes a CS protection signal output terminal connected to the chip.

7. The chip read / write protection circuit according to claim 4, characterized in that, The voltage detection unit further includes a third voltage detection unit, which is used to connect to the chip to obtain the power supply pin voltage of the chip. When the power supply pin voltage is lower than a third preset voltage value, a third protection action signal is output; the third preset voltage is less than the second preset voltage. When the protection control unit receives the third protection action signal, it forwards the third protection action signal to the read / write controller, and outputs a first protection signal to the chip according to the third protection action signal and the enable signal from the read / write controller.

8. The chip read / write protection circuit according to claim 7, characterized in that, The protection control unit includes a third subunit and a fourth subunit. The third subunit includes a third buffer, which includes a first protection action signal input terminal connected to the first voltage detection unit and a signal forwarding output terminal connected to the read / write controller. The fourth subunit includes a second logic gate circuit, a third logic gate circuit, a fourth buffer, and a second inverter, wherein the second logic gate circuit is connected to the third logic gate circuit and the fourth buffer respectively, and the third logic gate circuit is connected to the second inverter. The second logic gate circuit includes a second protection action signal input terminal connected to the second voltage detection unit and a first enable signal input terminal connected to the read / write controller; the third logic gate circuit includes a third protection action signal input terminal connected to the third voltage detection unit. The fourth buffer includes a WP protection signal output terminal connected to the chip, and the second inverter includes a CS protection signal output terminal connected to the chip.

9. The chip read / write protection circuit according to claim 1, characterized in that, The chip read / write protection circuit also includes an energy storage unit, which is used to supply power to the chip when the power supply drops to a set voltage; the energy storage unit includes an energy storage capacitor, one end of which is grounded and the other end is used to connect to the chip; The power supply is connected between the energy storage capacitor and the chip to charge the energy storage capacitor.

10. An electronic device, characterized in that, The electronic device includes a chip read / write protection circuit as described in any one of claims 1-9, the chip, and the read / write controller; the read / write controller is configured to send a second protection signal to the chip when it receives the protection action signal, or to send an enable signal to the protection control unit when it receives the protection action signal; the chip is configured to stop reading / writing when it receives the first protection signal, or the first protection signal and the second protection signal, wherein the first protection signal is a hardware limit signal, and the second protection signal is a software stop signal.

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