Solid state disk test circuit and test device thereof

Abstract

The application relates to a solid state disk test circuit and a test device, which comprises an interface connector array, a power supply module and a control module. The interface connector array is arranged in a positive and negative staggered and high and low staggered manner and is used for connecting a plurality of solid state disks; the power supply module is provided with a first voltage reducer and a plurality of independent second voltage reducers, and short circuit protection is realized through a recoverable fuse; the control module coordinates a main controller, a power supply control chip and a state indication chip based on an I2C bus protocol, realizes parallel power supply management, test signal issuing and state monitoring of the plurality of solid state disks, and provides visual fault indication through a light emitting diode. The application has the effect of improving test parallelism to realize efficient batch testing.

Description

Technical Field

[0001] This application relates to the field of electronic circuit testing, and in particular to a solid-state drive testing circuit and testing device thereof. Background Technology

[0002] Solid-state drives (SSDs), as storage devices based on flash memory technology, are widely used in computer storage due to their advantages such as fast read / write speeds, high reliability, and low power consumption. In the SSD manufacturing process, the test board, as a core tool for SSD testing, is mainly used to connect the SSD to the test system to perform performance testing and functional verification. The test board provides a stable hardware platform and, through specific interface and circuit design, achieves electrical connections and signal transmission to the SSD, thereby completing various testing tasks.

[0003] Currently, solid-state drive (SSD) testing circuits in related technologies typically only support the connection and testing of a single or a few SSDs, and their interface layout and power supply structure limit the improvement of parallel testing capabilities. Although some designs attempt to increase the number of interfaces to improve test throughput, the limited interface arrangement makes it impossible to achieve truly high-parallelism and high-reliability testing.

[0004] The aforementioned technologies suffer from low parallelism in solid-state drive (SSD) testing. Utility Model Content

[0005] To overcome the drawback of low parallelism in solid-state drive (SSD) testing, this application provides a SSD testing circuit and testing device.

[0006] On the one hand, the solid-state drive testing circuit provided in this application adopts the following technical solution: A solid-state drive (SSD) testing circuit includes: An interface connector array for connecting to multiple solid-state drives includes multiple interface connectors, each of which has a power interface and a data interface; The power supply module, connected to the power interface and control module, includes a first step-down converter and multiple second step-down converters. The first step-down converter is connected to the multiple second step-down converters, and each second step-down converter is connected to the power interface. A control module, connected to the second buck converter and the data interface, includes a main controller, an I2C bus, and a power control module. Multiple SATA ports of the main controller are connected to the data interface. The SDA pin of the main controller is connected to the SDA line of the I2C bus, and the SCL pin of the main controller is connected to the SCL line of the I2C bus. The power control module includes a power control chip. The SDA pin of the power control chip is connected to the SDA line of the I2C bus, and the SCL pin of the power control chip is connected to the SCL line of the I2C bus. The GPIO port of the power control chip is connected to the enable pin of the second buck converter. When the solid-state drive is inserted into the interface connector, the main controller sends an enable signal to the power control chip via the I2C bus. The power control chip receives the enable signal and pulls multiple enable pins of the second buck converter high.

[0007] By adopting the above technical solution, by setting independent second buck converters for multiple solid-state drives, and by having the main controller independently control the enable pin of each second buck converter via the I2C bus and the power control chip, parallel power supply management for multiple solid-state drives is achieved, thereby improving the parallelism of solid-state drive testing.

[0008] Optionally, the interface connector is a SATA interface connector.

[0009] By adopting the above technical solution and using the SATA interface connector, it is compatible with existing solid-state drive devices, thus improving the versatility of testing.

[0010] Optionally, the control module further includes a status indication module, which includes a status indication chip and a light-emitting diode (LED). The SDA pin of the status indication chip is connected to the SDA line of the I2C bus, the SCL pin of the status indication chip is connected to the SCL line of the I2C bus, the GPIO ports of the status indication chip are respectively connected to the data interface and the anode of the LED, and the cathode of the LED is grounded.

[0011] By adopting the above technical solution, the test status of multiple solid-state drives is intuitively indicated by adding the status indicator module to the control module and controlling the on / off state of the light-emitting diodes, thereby improving the visualization of the test process.

[0012] Optionally, when the solid-state drive is inserted into the interface connector, the interface connector generates an in-situ signal and sends it to the status indicator chip. The main controller sends a read command to the status indicator chip via the I2C bus to confirm that the solid-state drive has been inserted.

[0013] By adopting the above technical solution, the presence signal generated by the interface connector and the read command of the main controller are used to confirm whether multiple solid-state drives are inserted, thus ensuring the reliability of the test.

[0014] Optionally, when the solid-state drive fails the test, the main controller generates a fault indication signal and sends it to the status indication chip via the I2C bus. The status indication chip receives the fault signal and sets its GPIO port to a high level to light up the LED.

[0015] By adopting the above technical solution, the fault indication signal generated by the main controller and the response of the status indication chip can promptly detect and indicate faults in the solid-state drive testing process, making it easier for operators to quickly locate and solve problems, thus improving the efficiency and accuracy of testing.

[0016] Optionally, the power supply module further includes a fuse located between the second buck converter and the power interface.

[0017] By adopting the above technical solution, short-circuit and overcurrent protection is achieved by setting the fuse between the second step-down converter and the power interface, thereby improving the safety and reliability of the testing device.

[0018] Optionally, the fuse is a resettable fuse.

[0019] By adopting the above technical solution and using a resettable fuse, power supply can be automatically restored after the power abnormality is resolved, without the need to replace the fuse, thus reducing maintenance costs.

[0020] Optionally, the power supply module further includes a filter circuit connected to the output terminal of the second step-down circuit, and the filter circuit includes a capacitor and an inductor.

[0021] By adopting the above technical solution, and connecting the filter circuit to the output terminal of the second step-down circuit, noise and interference in the power supply can be effectively filtered out, further improving the stability of the power supply, ensuring that the solid-state drive can work stably during the test, and improving the accuracy of the test results.

[0022] On the other hand, this application also provides a solid-state drive testing device, which adopts the following technical solution: A solid-state drive (SSD) testing device integrates the SSD testing circuitry into the device itself.

[0023] By adopting the above technical solution, the solid-state drive testing circuit is integrated into the solid-state drive testing device, thereby achieving a high degree of integration and modularity of the testing system.

[0024] Optionally, the solid-state drive testing device further includes a PCB board, and the solid-state drive testing circuit is disposed on the PCB board.

[0025] By adopting the above technical solution and integrating the test circuit onto the PCB board, the circuit layout and signal integrity are further optimized, and the mechanical stability and heat dissipation performance of the system are enhanced.

[0026] In summary, this application includes at least one of the following beneficial technical effects: 1. By setting independent second buck converters for multiple solid-state drives, the main controller independently controls the enable pin of each second buck converter via the I2C bus and the power control chip, thereby realizing parallel power supply management for multiple solid-state drives and improving the parallelism of solid-state drive testing; 2. By adding the status indicator module to the control module and controlling the on / off state of the light-emitting diodes to intuitively indicate the test status of the multiple solid-state drives, the visualization of the test process is improved. Attached Figure Description

[0027] Figure 1 This is a circuit diagram of the solid-state drive test circuit according to an embodiment of this application.

[0028] Figure 2 yes Figure 1 A schematic diagram of the power supply module.

[0029] Figure 3 yes Figure 2 The circuit schematic of the first buck converter in the diagram.

[0030] Figure 4 yes Figure 2 The circuit diagram of the second buck converter in the circuit.

[0031] Figure 5 yes Figure 1 A schematic diagram of the control module in the diagram.

[0032] Figure 6 yes Figure 5 The circuit diagram of the main controller in the system.

[0033] Figure 7 yes Figure 5 The circuit diagram of the power control chip in the middle.

[0034] Figure 8 yes Figure 5 The circuit schematic of the status indicator chip.

[0035] Figure 9 yes Figure 1 A schematic diagram of the interface connector array.

[0036] Figure 10 yes Figure 9 Circuit diagram of the interface connector in Explanation of reference numerals in the attached figures: 100, power supply module; 110, first buck converter; 120, second buck converter; 200, control module; 210, main controller; 220, I2C bus; 230, power control module; 231, power control chip; 240, status indicator module; 241, status indicator chip; 300, interface connector array; 310, interface connector; 311, power interface; 312, data interface. Detailed Implementation

[0037] The following is in conjunction with the appendix Figure 1-7 This application will be described in further detail.

[0038] Example 1 Embodiment 1 of this application discloses a solid-state drive (SSD) testing circuit. (Refer to...) Figure 1 The solid-state drive (SSD) test circuit includes a power supply module 100, a control module 200, and an interface connector array 300. The power supply module 100 includes a first buck converter 110 and a second buck converter 120. The output of the second buck converter 120 supplies power to the SSD via a power interface 311. The main controller 210 of the control module 200 is connected to a power control module 230 and a status indicator module 240. The power control module 230 controls the enable state of the second buck converter 120, and the status indicator module 240 displays the test status of the corresponding SSD. The interface connector array 300 has multiple high-speed data interfaces 312, and each interface connector 310 has both a data interface 312 and a power interface 311.

[0039] Reference Figures 2 to 4The power supply module 100 includes a first buck converter 110 and a second buck converter 120 connected to each power interface 311. The input terminal of the first buck converter 110 is connected to the input voltage, and the output terminal of the first buck converter 110 outputs a stable first power supply, which is used to power external circuits. The first buck converter 110 uses a buck-type DC-DC converter chip, which has the characteristics of high efficiency and low power consumption. It can also use a switching power supply chip or a linear regulator chip. The power interface 311 of each interface connector 310 is independently connected to the second buck converter 120. The first power supply is input from the input terminal of the second buck converter 120 and outputs the second power supply through the second buck converter 120. The output terminal of the second buck converter 120 is connected to the power interface 311. The second power supply powers the solid-state drive through the power interface 311 and also powers the control module 200. The second buck converter 120 also uses a buck-type DC-DC (Direct Current to Direct Current Converter) converter chip, and can also use a switching power supply chip or a linear regulator chip. The power supply module 100 also includes a fuse, which is connected in series in the power supply branch between the second buck converter 120 and the power interface 311. The fuse is a resettable fuse. When the solid-state drive experiences a short circuit or abnormally high current, the fuse will quickly cut off the power supply circuit, while the power supply and testing process of the other interface connectors 310 will not be affected. The resettable fuse can automatically regain conduction after the fault is cleared. Each output terminal of the second buck converter 120 is equipped with a filter circuit, which includes components such as capacitors and inductors, to suppress high-frequency noise and ripple in the output voltage.

[0040] Reference Figures 5 to 8The control module 200 includes a main controller 210, an I2C (Inter-Integrated Circuit) bus, a power control module 230, and a status indicator module 240. The main controller 210 may employ a high-performance microprocessor with an integrated SATA (Serial ATA) host controller and I2C functionality. The main controller 210 is connected to the power control module 230 and the status indicator module 240 via the I2C bus 220. The SDA pin of the main controller 210 is connected to the SDA line of the I2C bus 220, and the SCL pin of the main controller 210 is connected to the SCL line of the I2C bus 220. The power control module 230 includes at least two power control chips 231. Each power control chip 231 is a 16-bit I / O expansion chip with an I2C interface. The SDA line of the I2C bus 220 is connected to the SDA pin of the power control chip 231, and the SCL line of the I2C bus 220 is connected to the SCL pin of the power control chip 231. The GPIO ports of the power control chip 231 are used for power management of multiple solid-state drives. Each GPIO port of the power control chip 231 is connected to the enable pin of each second buck converter 120 in the power supply module 100. The operating state of the second buck converter 120 is controlled by controlling the level of the enable pin of the second buck converter 120. The status module includes at least two status indicator chips 241 and light-emitting diodes (LEDs). The status indicator chips 241 also use 16-bit I / O expansion chips with an I2C interface. The SDA line of the I2C bus 220 is connected to the SDA pin of the status indicator chip 241, the SCL line of the I2C bus 220 is connected to the SCL pin of the status indicator chip 241, the GPIO port of the status indicator chip 241 is connected to the data interface 312, and the GPIO port of the status indicator chip 241 is also connected to the anode of the light-emitting diode, the cathode of the light-emitting diode is grounded, and each light-emitting diode corresponds to an interface converter to provide visual fault indication.

[0041] Reference Figure 9 and Figure 10 The interface connector array 300 includes multiple interface connectors 310 (e.g., 24). The interface connectors 310 may be SATA interface connectors. Each interface connector 310 has a power interface 311 and a data interface 312. The power interface 311 is located between the power supply module 100 and the solid-state drive (SSD), and the power supply module 100 provides stable power to the SSD through the power interface 311. The data interface 312 is located between the SSD and the control module 200, and is used to expand the input or output channels for test signals.

[0042] The main controller 210 detects the power control module 230 and the status indicator module 240 via the I2C bus 220 to confirm that the power control chip 231 and the status indicator chip 241 are working properly. When multiple solid-state drives (SSDs) are inserted into the interface connector 310, the interface connector 310 generates an presence signal and sends it to the status indicator chip 241. The main controller 210 sends a read command to the status indicator chip 241 via the I2C bus 220 to confirm that the interface connector 310 has been inserted into the SSDs. The main controller 210 sends an enable signal to the power control chip 231 via the I2C bus 221. The power control chip 231 receives the enable signal and pulls the enable pins of multiple second buck converters 120 high. The second buck converters 120 supply power to the multiple SSDs through the power interface 311. The main controller 210 performs enumeration and initialization operations on multiple solid-state drives (SSDs) through the data interface 312. The main controller 210 sends enumeration commands to the powered-on SSDs through the data interface 312 to identify the SSD model, capacity, and connection status. After successful enumeration, the main controller 210 sends initialization configuration parameters to the SSDs through the data interface 312 according to a predefined test protocol. The initialization configuration parameters include logical block addressing configuration, communication protocol negotiation, and test mode selection. The SSDs complete their own configuration according to the received initialization configuration parameters and return a ready signal to the main controller 210. After that, the main controller 210 begins to send test signals.

[0043] The main controller 210 generates test signals and transmits them to the solid-state drives (SSDs) via the data interface 312. Multiple SSDs receive the test signals and execute the test items. When a test fails for an SSD, the main controller 210 generates a fault indication signal and sends it to the status indicator chip 241 via the I2C bus 220. The status indicator chip 241 receives the fault signal and sets its GPIO port to a high level to indicate that the SSD test has failed.

[0044] The implementation principle of a solid-state drive test circuit in Embodiment 1 of this application is as follows: Each solid-state drive is provided with an independent power path through an independently configured second buck converter 120, and a resettable fuse is connected in series in each power path to achieve short circuit and overcurrent protection. The output terminal of each second buck converter 120 is also configured with a filter circuit to suppress high-frequency noise and ripple. The control module 200 is based on a high-performance main controller 210 and coordinates the power control chip 231 and the status indicator chip 241 through the I2C bus 220 to realize power supply management and status monitoring, realize parallel power supply management, test signal transmission and status monitoring of multiple solid-state drives, and provide visual fault indication through light-emitting diodes.

[0045] Example 2 Embodiment 2 of this application discloses a solid-state drive testing device, including the solid-state drive testing circuit and PCB in Embodiment 1 above, with the solid-state drive circuit disposed on the PCB.

[0046] The implementation principle of the solid-state drive testing device in Embodiment 2 of this application is as follows: the solid-state drive testing circuit in Embodiment 1 above is integrated on the PCB board, and the testing circuit is realized through physical support and electrical connection at the circuit board level, thereby further improving the stability of the testing device and the efficiency of batch testing.

[0047] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application are covered within the scope of protection of this application.

Claims

1. A solid-state drive testing circuit, characterized in that, include: An interface connector array (300) for connecting to multiple solid-state drives includes multiple interface connectors (310), each of which has a power interface (311) and a data interface (312). The power supply module (100) is connected to the power interface (311) and the control module (200), and includes a first step-down converter (110) and a plurality of second step-down converters (120). The first step-down converter (110) is connected to the plurality of second step-down converters (120), and each second step-down converter (120) is connected to the power interface (311). A control module (200), connected to the second buck converter (120) and the data interface (312), includes a main controller (210), an I2C bus (220), and a power control module (230); multiple SATA ports of the main controller (210) are connected to the data interface (312), the SDA pin of the main controller (210) is connected to the SDA line of the I2C bus (220), and the SCL pin of the main controller (210) is connected to the SCL line of the I2C bus (220); the power control module (230) includes a power control chip (231), and the SDA pin of the power control chip (231) is connected to the SCL line of the I2C bus (220). Pin A is connected to the SDA line of the I2C bus (220), the SCL pin of the power control chip (231) is connected to the SCL line of the I2C bus (220), and the GPIO port of the power control chip (231) is connected to the enable pin of the second buck converter (120). When the solid-state drive is inserted into the interface connector (310), the main controller (210) sends an enable signal to the power control chip (231) through the I2C bus (220). The power control chip (231) receives the enable signal and pulls the enable pins of multiple second buck converters (120) high.

2. The solid-state drive testing circuit according to claim 1, characterized in that, The interface connector (310) is a SATA interface connector.

3. The solid-state drive testing circuit according to claim 1, characterized in that, The control module (200) further includes a status indicator module (240), which includes a status indicator chip (241) and a light-emitting diode. The SDA pin of the status indicator chip (241) is connected to the SDA line of the I2C bus (220), the SCL pin of the status indicator chip (241) is connected to the SCL line of the I2C bus (220), the GPIO ports of the status indicator chip (241) are respectively connected to the data interface (312) and the anode of the light-emitting diode, and the cathode of the light-emitting diode is grounded.

4. The solid-state drive testing circuit according to claim 3, characterized in that, When the solid-state drive is inserted into the interface connector (310), the interface connector (310) generates an in-place signal and sends it to the status indicator chip (241). The main controller (210) sends a read command to the status indicator chip (241) through the I2C bus (220) to confirm that the solid-state drive has been inserted.

5. The solid-state drive testing circuit according to claim 3, characterized in that, When the solid-state drive fails to pass the test, the main controller (210) generates a fault indication signal and sends it to the status indication chip (241) via the I2C bus (220). The status indication chip (241) receives the fault indication signal and sets its GPIO port to a high level to light up the LED.

6. The solid-state drive testing circuit according to claim 1, characterized in that, The power supply module (100) also includes a fuse located between the second step-down converter (120) and the power interface (311).

7. The solid-state drive testing circuit according to claim 6, characterized in that, The fuse is a resettable fuse.

8. The solid-state drive testing circuit according to claim 1, characterized in that, The power supply module (100) also includes a filter circuit connected to the output terminal of the second step-down converter (120), and the filter circuit includes a capacitor and an inductor.

9. A solid-state drive testing device, characterized in that, Includes the solid-state drive test circuit as described in any one of claims 1 to 8.

10. The solid-state drive testing apparatus according to claim 9, characterized in that, It also includes a PCB board, on which the solid-state drive test circuit is located.

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