A fast current protection circuit

Abstract

The utility model discloses a kind of fast current protection circuit, including double D flip-flop, first comparator and second comparator, the output interface of first comparator and second comparator output interface are connected with the 11 pin of the double D flip-flop after parallel connection, the 11 pin of the double D flip-flop is connected with 9 pin in series, resistance R0 and sliding rheostat RP0 are connected in series in the negative pole of first comparator, the positive pole of first comparator and the negative pole of second comparator are connected in series, the positive pole of second comparator is connected with resistance R3 and sliding rheostat RP1 in series.The utility model comparator response time≤1.3us, diode conduction time≤8ns, double D flip-flop response time≤150ns, from overcurrent to output double D flip-flop output protection signal time≤1.5us, response is fast, and overcurrent protection can also be locked, avoid circuit between normal and fault state repeatedly cut.

Description

Technical Field

[0001] This utility model relates to the field of circuit protection technology, and in particular to a fast current protection circuit. Background Technology

[0002] In motor control, solenoid valve drive, and power output circuits, overcurrent protection is a crucial function for ensuring the safe and stable operation of the system. Software overcurrent protection typically involves a microcontroller (MCU) sampling the current signal in real time, processing it using an algorithm, and then executing the protection action. This requires multiple processing steps, including current signal sampling, AD conversion, digital filtering, threshold comparison, and logical judgment. In motor control systems, the ADC conversion time is approximately 1-2 μs, and data processing and algorithm execution require 5-8 μs. The instruction cycle and execution delay further increase the response time, resulting in software overcurrent protection times typically exceeding 10 μs, which is too slow. Traditional hardware protection circuits are designed for instantaneous action, generating a protection signal immediately when the current exceeds a threshold. However, this signal is usually immediately deactivated as the fault current disappears, failing to create a memory effect. Basic comparator circuits immediately return to normal operation when the input signal falls below the reference voltage, lacking state retention capability. This is particularly dangerous in intermittent overcurrent faults, as the circuit repeatedly switches between normal and fault states. Utility Model Content

[0003] To solve the above problems, the technical solution adopted by this utility model is as follows:

[0004] A fast current protection circuit includes a dual D flip-flop, a first comparator, and a second comparator. The output interfaces of the first and second comparators are connected in parallel and then connected to pin 11 of the dual D flip-flop. Pin 11 of the dual D flip-flop is connected in series with pin 9. A resistor R0 and a variable resistor RP0 are connected in series with the negative terminal of the first comparator. The positive terminal of the first comparator is connected in series with the negative terminal of the second comparator. A resistor R3 and a variable resistor RP1 are connected in series with the positive terminal of the second comparator.

[0005] Furthermore, resistors R1 and R2 are connected in series between the positive terminal of the first comparator and the negative terminal of the second comparator.

[0006] Furthermore, the output interface of the first comparator is connected in series with diode D0, and the output interface of the second comparator is connected in series with diode D1, wherein diode D0 and diode D1 are connected in parallel.

[0007] Furthermore, a resistor R4 is connected in parallel between the output interface of the first comparator and the diode D0, and the resistor R4 is connected to the negative terminal of the first comparator. A resistor R5 is connected in parallel between the output interface of the second comparator and the diode D1.

[0008] Furthermore, a resistor R6 is connected in series between pin 11 of the dual D flip-flop and the parallel diodes D0 and D1.

[0009] Furthermore, a diode D2 is connected in parallel between the resistor R4 and pin 11 of the dual D flip-flop, and the diode D2 is grounded.

[0010] The beneficial effects of this utility model are as follows: the response time of the first comparator and the second comparator is ≤1.3us, the conduction time of the diode is ≤8ns (0.008us), and the response time of the dual D flip-flop is ≤150ns (0.15us). Therefore, the time from the occurrence of overcurrent to the output protection signal of the dual D flip-flop is ≤1.5us, which can effectively improve the response time. In addition, the dual D flip-flop can also lock the overcurrent protection, avoiding the circuit from repeatedly switching between normal and fault states in intermittent overcurrent faults. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the invention.

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the circuit structure. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0015] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0016] refer to Figure 1 As shown, one embodiment of this utility model is as follows:

[0017] A fast current protection circuit includes a dual D flip-flop, a first comparator, and a second comparator. The output interfaces of the first and second comparators are connected in parallel and then connected to pin 11 of the dual D flip-flop. Pin 11 of the dual D flip-flop is connected in series with pin 9. A resistor R0 and a variable resistor RP0 are connected in series with the negative terminal of the first comparator. The positive terminal of the first comparator is connected in series with the negative terminal of the second comparator. A resistor R3 and a variable resistor RP1 are connected in series with the positive terminal of the second comparator.

[0018] In this invention, the dual D flip-flop is model CD4013. Its pin 9 (D2 terminal) and pin 11 (CLDCK2 terminal) are connected in parallel, i.e., shorted together. This allows it to lock the overcurrent signal output by the first or second comparator. When the dual D flip-flop receives an overcurrent signal, pin 13 (Q2 terminal) outputs high. Even when the output of the first or second comparator changes from high to low, the output of pin 13 of the dual D flip-flop remains high, achieving overcurrent lockout protection. Furthermore, pin 13 of the dual D flip-flop can also receive a control enable signal, which can cut off the controller's power output when an overcurrent occurs.

[0019] In this invention, pin 10 (RESET2 terminal) of the dual D flip-flop is used to receive a reset signal. After power-on, the controller must input a high pulse signal to pin 10 of the dual D flip-flop to ensure that the initial state of the dual D flip-flop is low.

[0020] In this invention, both the first and second comparators are LM393. The first comparator sets the upper limit of the current, and the second comparator sets the lower limit. Specifically, the first comparator is set by adjusting the resistance of the sliding rheostat RP0, and the second comparator is set by adjusting the resistance of the sliding rheostat RP1. The upper and lower limits are compared with the real-time current signal. When the real-time current exceeds the upper limit, the first comparator outputs high; when the real-time current is between the upper and lower limits, both the first and second comparators output low; and when the real-time current is below the lower limit, the second comparator outputs high. Furthermore, resistors R0 and R3 are both 10KΩ. Resistor R0 is used for voltage division protection of the sliding resistor RP0, and resistor R3 is used for voltage division protection of the sliding resistor RP1, preventing excessive voltage when RP0 or RP1 slides to 0Ω.

[0021] Specifically, resistors R1 and R2 are connected in series between the positive terminal of the first comparator and the negative terminal of the second comparator. Both resistors R1 and R2 are 10K, forming a voltage divider circuit to provide a reference voltage for the first and second comparators. When a voltage is applied across R1 and R2 in series, an intermediate voltage is generated at the connection point of R1 and R2 according to the voltage divider principle. This intermediate voltage serves as the threshold voltage of the comparator.

[0022] Specifically, diode D0 is connected in series with the output interface of the first comparator, and diode D1 is connected in series with the output interface of the second comparator. Diodes D0 and D1 are connected in parallel. Diodes D0 and D1 are used to achieve unidirectional signal conduction and isolation, ensuring that the overcurrent detection signals of the first and second comparators independently trigger the protection logic and avoid mutual interference. When the first or second comparator outputs a high level (overcurrent detection triggered), the anode voltage of diode D0 or D1 is higher than that of its cathode, resulting in forward conduction. This transmits the high-level signal to the dual D flip-flop, causing the overcurrent protection signal to output a high level. When the comparator outputs a low level, the diode is reverse-biased and cut off, not affecting subsequent circuitry.

[0023] Specifically, a resistor R4 is connected in parallel between the output interface of the first comparator and the diode D0, and resistor R4 is connected to the negative terminal of the first comparator. A resistor R5 is connected in parallel between the output interface of the second comparator and the diode D1. Resistors R4 and R5 are both 3KΩ, used to provide negative feedback for the corresponding first or second comparator, stabilizing the output state and providing current limiting protection. When the first or second comparator outputs a high level, current flows through R4 or R5 to the negative terminal of the first or second comparator, forming negative feedback, stabilizing the output state and preventing false flips caused by small fluctuations in the input signal; at the same time, it limits the current flowing into the negative terminal of the comparator, preventing excessive current from damaging the comparator. When the first or second comparator outputs a low level, diode D0 or D1 is forward-biased, and R4 and R5 have minimal impact on signal transmission, ensuring that the low-level signal is effectively transmitted to subsequent circuits.

[0024] Specifically, a resistor R6 is connected in series between pin 11 of the dual D flip-flop and the parallel diodes D0 and D1. Resistor R6 is used for current limiting, voltage division, and noise suppression. When diode D0 or D1 is forward-biased, R6 limits the current flowing through the diode, protecting the comparator output stage and the flip-flop input stage. Simultaneously, by dividing the voltage, it stabilizes the low-level signal at the RESET2 terminal within the effective trigger threshold, preventing false triggering. Furthermore, the impedance characteristics of R6 suppress high-frequency noise, reducing the impact of interference on the flip-flop input signal.

[0025] Specifically, a diode D2 is connected in parallel between the resistor R4 and pin 11 of the dual D flip-flop, and diode D2 is grounded. D2 is used to prevent excessively low negative voltage input to the dual D flip-flop, avoiding damage or malfunction of the dual D flip-flop due to abnormal input voltage.

[0026] In this invention, the response time of the first comparator and the second comparator is ≤1.3us, the conduction time of the diode is ≤8ns (0.008us), and the response time of the dual D flip-flop is ≤150ns (0.15us). Therefore, the time from the occurrence of overcurrent to the output protection signal of the dual D flip-flop is ≤1.5us, which can effectively improve the response time. In addition, the dual D flip-flop can also lock the overcurrent protection, avoiding the circuit from repeatedly switching between normal and fault states in intermittent overcurrent faults.

[0027] The following points need to be explained:

[0028] (1) Unless otherwise defined, the same reference numerals in the embodiments and drawings of this disclosure have the same meaning.

[0029] (2) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0030] (3) For clarity, components or areas are enlarged in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be an intermediate element.

[0031] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A fast current protection circuit, characterized in that: It includes a dual D flip-flop, a first comparator, and a second comparator. The output interfaces of the first and second comparators are connected in parallel and then connected to pin 11 of the dual D flip-flop. Pin 11 of the dual D flip-flop is connected in series with pin 9. The negative terminal of the first comparator is connected in series with a resistor R0 and a variable resistor RP0. The positive terminal of the first comparator is connected in series with the negative terminal of the second comparator. The positive terminal of the second comparator is connected in series with a resistor R3 and a variable resistor RP1.

2. The fast current protection circuit according to claim 1, characterized in that: A resistor R1 and a resistor R2 are connected in series between the positive terminal of the first comparator and the negative terminal of the second comparator.

3. The fast current protection circuit according to claim 2, characterized in that: The output interface of the first comparator is connected in series with diode D0, and the output interface of the second comparator is connected in series with diode D1. Diode D0 and diode D1 are connected in parallel.

4. A fast current protection circuit according to claim 3, characterized in that: A resistor R4 is connected in parallel between the output interface of the first comparator and the diode D0, and the resistor R4 is connected to the negative terminal of the first comparator. A resistor R5 is connected in parallel between the output interface of the second comparator and the diode D1.

5. A fast current protection circuit according to claim 4, characterized in that: A resistor R6 is connected in series between pin 11 of the dual D flip-flop and the parallel diodes D0 and D1.

6. A fast current protection circuit according to claim 5, characterized in that: A diode D2 is connected in parallel between the resistor R4 and pin 11 of the dual D flip-flop, and the diode D2 is grounded.

Images