Self-triggering self-restoring protection circuit

Abstract

The utility model relates to the field of protection circuit, concretely is a kind of self-triggering self-recovery protection circuit. Including the conflict monitoring unit of receiving high side switch original control signal PWM_H and low side switch original control signal PWM_L, conflict monitoring unit output conflict detection signal PWM_Z. Two signal conditioning units, receive PWM_H and PWM_Z, PWM_L and PWM_Z respectively, output new high side switch control signal PWM_H_Out and new low side switch control signal PWM_L_Out. The self-triggering self-recovery protection circuit of the utility model directly monitors the conflict state of high-low side switch original control signal from control signal in real time through XOR gate, compared with traditional current detection scheme, without waiting for current to rise to threshold value, it can be front-end identified straight-through risk, response speed completely matches the logic change of control signal, completely eliminates the possibility of straight-through current generation from source.

Description

Technical Field

[0001] This utility model relates to the field of protection circuits, specifically a self-triggering and self-recovering protection circuit. Background Technology

[0002] In power electronic systems such as motor drive systems, switching power supplies, and photovoltaic inverters, half-bridge or full-bridge topologies are essential for power conversion and transmission, and their operational reliability directly impacts the safety of the entire system. However, when the control signals of the high-side and low-side switches are simultaneously at a high level due to program malfunctions, communication interference, or electromagnetic compatibility issues, the upper and lower switches of the bridge arm will conduct simultaneously, creating a transient shoot-through current through a low-impedance path. This current can far exceed the rated current capacity of the switching devices, causing overheating, burnout, or even damage to the drive circuit. It can also lead to a sudden drop in system voltage or abnormal load, such as sudden changes in motor torque, seriously threatening equipment lifespan and operational stability.

[0003] To address these issues, existing technologies typically employ two approaches: First, they detect transient currents using current sensors and trigger shutdown. However, the response time of current detection often exceeds the drive control cycle, and threshold settings require a trade-off between "avoiding false triggers" and "timely protection," making it difficult to fully cover all abnormal scenarios. Second, they utilize driver integrated circuits with built-in interlocking functions. However, after enabling protection, an external reset signal is required to restore normal output, and the reset time is usually much longer than the control cycle, easily causing system control interruptions or decreased stability. Therefore, constructing a protection mechanism that does not rely on current detection or external reset operations, can detect control signal conflicts in real time and quickly block bridge arm shoot-through, and automatically restores normal control after the anomaly is resolved has become a technical challenge for improving the reliability of power electronic systems. Utility Model Content

[0004] This disclosure proposes a self-triggering and self-recovering protection circuit, which aims to overcome at least one of the defects existing in the prior art.

[0005] To achieve the above objectives, the technical solution disclosed in this utility model is as follows: According to one aspect of this disclosure, a self-triggering and self-recovering protection circuit is provided, comprising a conflict monitoring unit that receives a high-side switch original control signal PWM_H and a low-side switch original control signal PWM_L, the conflict monitoring unit outputting a conflict detection signal PWM_Z; two signal conditioning units that respectively receive PWM_H and PWM_Z, and PWM_L and PWM_Z, and output a new high-side switch control signal PWM_H_Out and a new low-side switch control signal PWM_L_Out; the conflict monitoring unit is an XOR gate used to detect whether PWM_H and PWM_L are simultaneously high; the signal conditioning units are AND gates used to turn off the high-level outputs of PWM_H_Out and PWM_L_Out when PWM_H and PWM_L are simultaneously high, to prevent the high and low side switches from being turned on simultaneously.

[0006] Furthermore, the first input terminal of the XOR gate is electrically connected to the PWM_H, the second input terminal is electrically connected to the PWM_L, and the output terminal is electrically connected to the first input terminal of the two AND gates, so as to transmit the collision detection signal PWM_Z to the two AND gates.

[0007] Furthermore, one of the AND gates is a high-side signal conditioning AND gate, with its second input terminal electrically connected to the PWM_H and its output terminal electrically connected to the driving terminal of the high-side switch, for outputting the new high-side switch control signal PWM_H_Out; the other AND gate is a low-side signal conditioning AND gate, with its second input terminal electrically connected to the PWM_L and its output terminal electrically connected to the driving terminal of the low-side switch, for outputting the new low-side switch control signal PWM_L_Out.

[0008] Furthermore, when both PWM_H and PWM_L are high, the PWM_Z output by the XOR gate is low, and the outputs of both AND gates output low levels PWM_H_Out and PWM_L_Out to forcibly turn off the high and low side switches.

[0009] Furthermore, the protection circuit is applied to the high-side and low-side switch control of the half-bridge or full-bridge circuit. The PWM_H_Out is electrically connected to the gate drive terminal of the high-side switch in the half-bridge or full-bridge circuit, and the PWM_L_Out is electrically connected to the gate drive terminal of the low-side switch in the half-bridge or full-bridge circuit.

[0010] Furthermore, the high-side switch and the low-side switch are metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors.

[0011] Furthermore, when the simultaneous high-level state of PWM_H and PWM_L is released, the PWM_Z output by the XOR gate recovers to a level that is logically matched with PWM_H and PWM_L, and the PWM_H_Out and PWM_L_Out output by the two AND gates automatically recover to signals consistent with PWM_H and PWM_L, which are used to control the self-recovery of the output.

[0012] The beneficial effects of this utility model are: This invention's self-triggering and self-recovering protection circuit directly monitors the conflict state of the original control signals of the high and low side switches in real time through an XOR gate. Compared with traditional current detection schemes, it can identify shoot-through risks in advance without waiting for the current to rise to the threshold. The response speed perfectly matches the logical changes of the control signal, eliminating the possibility of shoot-through current generation from the source. At the same time, it uses an AND gate to condition the control signal and immediately shuts off the effective control output of the high and low side switches when a conflict occurs. The entire process does not require additional reset operations, avoiding system stability problems caused by reset of the built-in interlocking driver integrated circuit.

[0013] Once the abnormal state of the control signal is resolved, the XOR gate output automatically recovers to the level that matches the logic of the original control signal. The AND gate then restores the conditioned control signal to an output consistent with the original signal, achieving self-recovery of the control output and ensuring that the system quickly returns to normal operation after the fault is cleared.

[0014] The entire circuit consists of only XOR gates and AND gates, making it extremely simple in structure and low in cost. It not only solves the shortcomings of existing solutions such as slow response and reliance on external operation, but also achieves full-process protection of "real-time monitoring-automatic blocking-abnormal recovery" through pure hardware logic. This improves the reliability and anti-interference capability of power electronic systems under abnormal control signal scenarios, and provides a more efficient and stable technical solution for shoot-through protection of half-bridge and full-bridge circuits.

[0015] The above description is only an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, the preferred embodiments of this utility model are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a logic block diagram of a self-triggering and self-recovering protection circuit in one embodiment of the present invention; Figure 2 This is a schematic diagram of the bridge arm switch circuit used in the protection circuit of one embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention.

[0018] The present invention provides the following preferred embodiments: In power electronic systems such as motor drives, switching power supplies, and photovoltaic inverters, the shoot-through problem of bridge arms in half-bridge / full-bridge topologies is a core risk threatening system reliability. Existing technologies, through current sensing or integrated interlocking ICs, either suffer from response delays or rely on external resets, making it difficult to meet the high reliability requirements of "real-time protection + intervention-free recovery." This invention proposes a self-triggering and self-recovering protection circuit that achieves closed-loop protection of "control signal conflict monitoring - abnormal output blocking - normal state self-recovery" using a pure hardware logic architecture. The core design concept is to use XOR gates to sense logical conflicts between high and low-side control signals in real time, and AND gates to dynamically condition the output signals, eliminating the possibility of bridge arm shoot-through at the source, while avoiding the impact of external reset operations on system stability. This implementation will comprehensively explain the implementation details of the technical solution, combining circuit architecture, signal logic, application scenarios, and reliability design.

[0019] The core of this protection circuit consists of one collision detection unit (XOR gate) and two signal conditioning units (AND gate). The circuit topology and signal flow are as follows: Figure 1 As shown: Conflict Detection Unit: XOR Gate (Gate1) The conflict monitoring unit's function is to detect in real time whether the original control signal of the high-side switch (PWM_H) and the original control signal of the low-side switch (PWM_L) are both high. Its hardware implementation is an XOR gate (models such as 74HC86 and CD4030 industrial-grade logic gates are available). The pin connections of the XOR gate strictly correspond to the signal logic: First input terminal (Pin1): Electrically connected to the high-side original control signal PWM_H (PWM output from controllers such as MCU and DSP); Second input terminal (Pin2): Electrically connected to the low-side original control signal PWM_L (same as another PWM output of the controller); Output (Pin3): Outputs the collision detection signal PWM_Z, which serves as the enable signal for subsequent signal conditioning units.

[0020] Signal conditioning unit: dual AND gates (Gate2, Gate3) The signal conditioning unit dynamically adjusts the control signal output to the high- and low-side switches based on the collision detection signal PWM_Z, ensuring forced shutdown in case of an anomaly and restoration of the original logic in case of normal operation. The two AND gates are implemented using the same type of logic gate (such as 74HC08 or CD4081), and their pin connections are as follows: High-side signal conditioning AND gate (Gate2): First input terminal (Pin1): Electrically connected to the output signal PWM_Z of the XOR gate (as the enable terminal); Second input terminal (Pin2): Electrically connected to the high-side original control signal PWM_H; Output terminal (Pin3): Outputs a new high-side switch control signal PWM_H_Out, which is directly connected to the gate drive terminal of the high-side switch (such as the gate driver input of a MOSFET or the gate driver input of an IGBT).

[0021] Low-side signal conditioning AND gate (Gate3): First input terminal (Pin1): Electrically connected to the output signal PWM_Z of the XOR gate (shares the enable signal with Gate2); Second input terminal (Pin2): Electrically connected to the low-side original control signal PWM_L; Output terminal (Pin3): Outputs a new low-side switch control signal PWM_L_Out, which is directly connected to the gate drive terminal of the low-side switch.

[0022] Circuit signal flow direction: The complete link from raw control signal → conflict detection → signal conditioning → switch drive is as follows: PWM_H, PWM_L → XOR gate Gate1 → PWM_Z → AND gate Gate2 (combined with PWM_H) → PWM_H_Out → High-side switch gate drive; PWM_H, PWM_L → XOR gate Gate1 → PWM_Z → AND gate Gate3 (combined with PWM_L) → PWM_L_Out → Low-side switch gate drive.

[0023] The protection function of this circuit relies on the logical combination of XOR gates and AND gates. It needs to be analyzed from two dimensions: conflict detection and signal conditioning, and the correctness of the logic should be verified by combining the signal status table.

[0024] The logic function of an XOR gate is:

[0025] Where A is PWM_H, B is PWM_L, and Y is PWM_Z. Its core logic is: when the input signals are different, the output is high (1); when the input signals are the same, the output is low (0).

[0026] Based on the requirements for bridge arm protection, the hazardous state to be monitored is "PWM_H and PWM_L are both high," in which case both high and low side switches are turned on simultaneously, while "both low" (dead time) is the safe state designed for the system. The logic characteristics of XOR gates perfectly match this requirement: When PWM_H=1 and PWM_L=1 (dangerous state): same input logic → PWM_Z=0; When PWM_H=0 and PWM_L=0 (safety dead zone): same input logic → PWM_Z=0; When PWM_H ≠ PWM_L (normal operating state, such as high side on, low side off, or vice versa): different input logic → PWM_Z = 1.

[0027] As can be seen, the output PWM_Z of the XOR gate maps both "dangerous signal collisions" and "safe dead-time states" to a low level, while mapping "normal working state" to a high level, providing a clear enable signal for the subsequent signal conditioning unit.

[0028] Furthermore, the logical function of an AND gate is: Where A is the collision detection signal PWM_Z, B is the original control signal (PWM_H or PWM_L), and Y is the conditioned output signal (PWM_H_Out or PWM_L_Out). Its core logic is: output a high level only when both inputs are high; otherwise, output a low level.

[0029] Combining the output PWM_Z of the XOR gate, the conditioning function of the AND gate can be divided into two scenarios: abnormal blocking and normal restoration. Abnormal scenario: Both PWM_H and PWM_L are high simultaneously (dangerous state) When PWM_H=1 and PWM_L=1, the XOR gate outputs PWM_Z=0. At this time: The inputs to the high-side AND gate Gate2 are PWM_Z=0 (enable input) and PWM_H=1 (original signal) → the output is PWM_H_Out=0·1=0; The inputs to the low-side AND gate Gate3 are PWM_Z=0 (enable input) and PWM_L=1 (original signal) → the output is PWM_L_Out=0·1=0.

[0030] After conditioning, the output signals PWM_H_Out and PWM_L_Out are both low, which directly turns off the gate drive signals of the high and low side switches. Voltage-controlled switches such as MOSFETs and IGBTs need to be turned on at a high level, thus preventing bridge arm shoot-through from the source.

[0031] Normal Scenario 1: High-side on, low-side off (PWM_H=1, PWM_L=0) When the system is in normal operating condition (such as the forward rotation phase of a motor drive), PWM_H=1, PWM_L=0, and the XOR gate outputs PWM_Z=1 (the input logic is different). At this time: The inputs to the high-side AND gate Gate2 are PWM_Z=1 and PWM_H=1 → the output PWM_H_Out=1·1=1 (high level turns on the high-side switch); The inputs to the low-side AND gate Gate3 are PWM_Z=1 and PWM_L=0 → the output is PWM_L_Out=1·0=0 (low level turns off the low-side switch).

[0032] The conditioned output is completely consistent with the original control signal and does not affect the normal control logic of the system.

[0033] Normal Scenario 2: Low-side on, high-side off (PWM_H=0, PWM_L=1) When the system is in reverse operation (e.g., motor reversing), PWM_H=0, PWM_L=1, and the XOR gate outputs PWM_Z=1. At this time: The inputs to the high-side AND gate Gate2 are PWM_Z=1 and PWM_H=0, resulting in an output PWM_H_Out=0. The inputs to the low-side AND gate Gate3 are PWM_Z=1 and PWM_L=1, and the output is PWM_L_Out=1.

[0034] The output signal remains consistent with the original logic, ensuring the system operates normally.

[0035] Normal Scenario 3: Dead Time (PWM_H=0, PWM_L=0) Dead time is a "double-off" state set in the system design to prevent the switching transistor's body diode from conducting. In this state, PWM_H=0, PWM_L=0, and the XOR gate output PWM_Z=0. The output after AND gate conditioning is: PWM_H_Out=0·0=0; PWM_L_Out=0·0=0.

[0036] The output signal is perfectly matched to the dead-time design requirements and will not interfere with the normal dead-time control of the system.

[0037] To further verify the correctness of the circuit logic, refer to the signal state relationships shown in Table 1: Table 1 Signal State Relationship Table

[0038] The data in the table shows that all dangerous states were forcibly shut down, all normal states were accurately restored, and the circuit logic fully meets the requirements for bridge arm protection.

[0039] Furthermore, the mechanism of this utility model's "self-triggered + self-recovering" technical solution, which requires in-depth analysis in conjunction with circuit logic and system operation scenarios, is as follows: "Self-triggered" means that when a conflict occurs in the control signals, the circuit automatically activates its protection mechanism without external instructions. Its implementation relies on the hardware logic of XOR gates and AND gates. When PWM_H and PWM_L are both high (such as due to program crash or communication interference), the output PWM_Z of the XOR gate immediately jumps from 1 to 0 (the delay is only the propagation delay of the logic gate, about 10ns~50ns). When one of the inputs to the AND gate becomes 0, the output immediately jumps to 0 (with a delay of 10ns~50ns). The gate drive signals of the high-side and low-side switches synchronously become low, and the switching transistors are turned off within tens of ns (the turn-off time of a MOSFET is approximately 100ns to 500ns).

[0040] The total delay of the entire protection process is less than 1μs, which is much faster than the response time of the current detection scheme (usually 1μs~10μs), completely avoiding the generation of shoot-through current - because the turn-off speed of the switching transistor is much faster than the current rise speed (the rise time of transient current is about 1μs~10μs).

[0041] Furthermore, "self-recovery" means that once the conflict in the control signal is resolved, the circuit automatically resumes normal control output without external reset. Its implementation also relies on the adaptability of the hardware logic: When the conflict between PWM_H and PWM_L is resolved (such as when the program returns to normal or the interference disappears), the input logic of the XOR gate returns to "different" or "both are low"; If it returns to "different" (normal working state): PWM_Z=1, the output of the AND gate is restored to be consistent with the original signal (e.g., PWM_H=1→PWM_H_Out=1, PWM_L=0→PWML_Out=0). If we return to "simultaneously low" (dead time): PWM_Z=0, the AND gate output remains low, which conforms to the dead time design.

[0042] For example, if the program crashes and causes PWM_H and PWM_L to be high at the same time, after the system's watchdog is reset, the PWM signal returns to normal logic (such as PWM_H=1, PWM_L=0), the output PWM_Z of the XOR gate immediately becomes 1, and the output of the XOR gate is synchronously restored to PWM_H_Out=1, PWM_L_Out=0, and the system can continue to run without manual intervention.

[0043] This protection circuit is highly versatile and can be directly applied to the protection of the bridge arms of half-bridge and full-bridge circuits. The specific connection method is explained below with reference to typical scenarios: 1. Application of half-bridge circuit The half-bridge circuit is the most commonly used topology in power electronic systems. It consists of a high-side switch Q1 (such as an N-channel MOSFET), a low-side switch Q2 (such as an N-channel MOSFET), and a midpoint capacitor. Figure 2 As shown. The connection method of this protection circuit is as follows: PWM_H_Out: Connects to the gate drive circuit input of the high-side switch Q1 (such as the HIN pin of the gate driver IR2110). PWM_L_Out: Connects to the gate drive circuit input of the low-side switch Q2 (such as the LIN pin of IR2110). The drain of Q1 is connected to the positive terminal of the DC power supply (Vcc), and the source is connected to the midpoint (Node). Q2's drain is connected to the neutral point (Node), and its source is grounded (GND). The midpoint (Node) is connected to the load (such as motor windings or transformer primary side).

[0044] When PWM_H and PWM_L are both high, PWM_H_Out and PWM_L_Out are both 0, the HIN and LIN pins of IR2110 are both low, the gate drive voltage of Q1 and Q2 is 0, the switching transistors are turned off, and shoot-through is avoided.

[0045] 2. Application of full-bridge circuit The full-bridge circuit consists of two half-bridges (bridge arm 1: Q1, Q2; bridge arm 2: Q3, Q4) and is used to achieve bidirectional power conversion (such as motor forward and reverse rotation, bidirectional DC-DC conversion). This protection circuit is applied by configuring an independent protection circuit for each bridge arm. The PWM_H1 (original control signal of Q1) and PWM_L1 (original control signal of Q2) of bridge arm 1 are connected to the first set of protection circuits, and output PWM_H1_Out (Q1 drive) and PWM_L1_Out (Q2 drive). The PWM_H2 (original control signal of Q3) and PWM_L2 (original control signal of Q4) of bridge arm 2 are connected to the second set of protection circuits, and output PWM_H2_Out (Q3 drive) and PWM_L2_Out (Q4 drive).

[0046] This configuration ensures that the up and down switches of each bridge arm are independently protected, so that even if the control signal of one bridge arm conflicts, the other bridge arm can still work normally (if the system allows), further improving the reliability of the system.

[0047] 3. Adaptation of switching devices This protection circuit is compatible with voltage-controlled switching devices (MOSFETs, IGBTs) because their turn-on condition is a high level applied to the gate (or terminal block) and their turn-off condition is a low level, which perfectly matches the output logic of this circuit. MOSFET: Gate (G) connected to PWM_H_Out (high level to turn on, low level to turn off); IGBT: Gate (G) connected to PWM_H_Out (high level to turn on, low level to turn off).

[0048] For current-controlled devices (such as bipolar junction transistors, BJTs), an additional inverting circuit (such as a NOT gate) is required to reverse the output logic of this circuit. However, since BJTs are rarely used in power electronic systems, they will not be discussed here.

[0049] To highlight the advantages of this utility model, it is compared with two mainstream existing technologies, as shown in Table 2: Table 2 Comparison of Technical Indicators

[0050] Furthermore, as can be seen from the table, this invention is superior to the prior art in terms of response speed, self-recovery capability, cost and compatibility, and is especially suitable for critical systems that cannot be shut down, such as medical equipment, industrial robots and new energy power generation systems.

[0051] Although the present invention has been specifically described above with reference to preferred embodiments, it should be understood that the present invention is not limited to the embodiments described above. Rather, various modifications and variations can be made by those skilled in the art without departing from the essence of the present invention, and such modifications and variations should fall within the scope defined by the appended claims and their equivalents.

Claims

1. A self-triggering and self-recovering protection circuit, characterized in that, The system includes a conflict monitoring unit that receives the original control signal PWM_H from the high-side switch and the original control signal PWM_L from the low-side switch, and outputs a conflict detection signal PWM_Z; two signal conditioning units that respectively receive the PWM_H and PWM_Z, and the PWM_L and PWM_Z, and output a new high-side switch control signal PWM_H_Out and a new low-side switch control signal PWM_L_Out; the conflict monitoring unit is an XOR gate used to detect whether the PWM_H and PWM_L are simultaneously high; the signal conditioning unit is an AND gate used to turn off the high-level output of the PWM_H_Out and PWM_L_Out when the PWM_H and PWM_L are simultaneously high, to prevent the high and low-side switches from being turned on simultaneously; the first input terminal of the XOR gate is electrically connected to the PWM_H, the second input terminal is electrically connected to the PWM_L, and the output terminal is electrically connected to the first input terminal of the two AND gates to transmit the conflict detection signal PWM_Z to the two AND gates.

2. The self-triggering and self-recovering protection circuit as described in claim 1, characterized in that, One of the AND gates is a high-side signal conditioning AND gate, whose second input is electrically connected to the PWM_H and whose output is electrically connected to the driver terminal of the high-side switch, for outputting the new high-side switch control signal PWM_H_Out; the other AND gate is a low-side signal conditioning AND gate, whose second input is electrically connected to the PWM_L and whose output is electrically connected to the driver terminal of the low-side switch, for outputting the new low-side switch control signal PWM_L_Out.

3. The self-triggering and self-recovering protection circuit as described in claim 1, characterized in that, When PWM_H and PWM_L are both high, the PWM_Z output by the XOR gate is low, and the outputs of both AND gates output low levels PWM_H_Out and PWM_L_Out to forcibly turn off the high and low side switches.

4. The self-triggering and self-recovering protection circuit as described in claim 1, characterized in that, The protection circuit is applied to the high-side and low-side switch control of a half-bridge or full-bridge circuit. The PWM_H_Out is electrically connected to the gate drive terminal of the high-side switch in the half-bridge or full-bridge circuit, and the PWM_L_Out is electrically connected to the gate drive terminal of the low-side switch in the half-bridge or full-bridge circuit.

5. The self-triggering and self-recovering protection circuit as described in claim 4, characterized in that, The high-side switch and the low-side switch are metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors.

6. The self-triggering and self-recovering protection circuit as described in claim 1, characterized in that, When the simultaneous high-level state of PWM_H and PWM_L is released, the PWM_Z output by the XOR gate recovers to the level that is logically matched with PWM_H and PWM_L, and the PWM_H_Out and PWM_L_Out output by the two AND gates automatically recover to signals consistent with PWM_H and PWM_L, which are used to control the self-recovery of the output.

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