A mode switching circuit, a mainboard and an electronic device

Abstract

The utility model embodiment provides a kind of mode switching circuit, mainboard and electronic equipment, it is related to electronic equipment technical field, including first resistance and first switch module, since in the mode control end of master control chip is the case of first level, master control chip is switched to scanning function mode, and in the power management enable end of master control chip is the case of first level, the power management function of master control chip is closed, then in the case where first level is low level, pass through the first switch module conduction of debugger control, the mode control end and power management enable end of master control chip are all pulled low to low level, so that master control chip is switched to scanning function mode and the power management function of master control chip is closed, and then the chip level test to mainboard can be implemented, compared with the mode of realization of manual jumper and the change of circuit in related art, work efficiency is improved.

Description

Technical Field

[0001] This utility model relates to the field of electronic equipment technology, and in particular to a mode switching circuit, a motherboard, and an electronic device. Background Technology

[0002] When performing chip-level testing on the motherboard of an electronic device, the main control chip of the motherboard needs to be switched from debug mode to scan mode. In addition, the advanced configuration and power interface (ACPI) function of the main control chip needs to be disabled to avoid accidentally triggering the ACPI function to control the motherboard to power down or restart during chip-level testing, which would cause the chip-level test of the motherboard to fail.

[0003] In related technologies, in order to perform chip-level testing on the motherboard, staff need to disassemble the electronic equipment and then manually switch the main control chip from debug mode to scan mode and disable the main control chip's ACPI function by manually setting jumpers and changing circuits, resulting in low work efficiency. Utility Model Content

[0004] This invention provides a mode switching circuit, a motherboard, and an electronic device to at least solve the problem in related technologies where workers need to disassemble the electronic device and manually switch the main control chip from debug mode to scan mode and disable the ACPI function of the main control chip by means of jumpers and circuit modifications, resulting in low work efficiency.

[0005] In a first aspect, the present invention provides a mode switching circuit, comprising: a first resistor and a first switch module; The first end of the first resistor is connected to the power supply, the second end of the first resistor is connected to the first end of the first switch module, and the second end of the first resistor is used to connect to the mode control terminal and the power management enable terminal of the main control chip of the motherboard, respectively. The first terminal of the first switch module is used to connect to the mode control terminal and the power management enable terminal of the main control chip respectively; the control terminal of the first switch module is used to connect to the debugger; and the second terminal of the first switch module is grounded. Specifically, when the mode control terminal of the main control chip is at the first level, the main control chip switches to the scanning function mode; when the power management enable terminal of the main control chip is at the first level, the power management function of the main control chip is turned off.

[0006] Optionally, the first switch module includes a first switch device and a second resistor; the first terminal of the first switch device is used to connect to the mode control terminal and the power management enable terminal of the main control chip respectively, the control terminal of the first switch device is used to connect to the debugger, and the second terminal of the first switch device is grounded; the first terminal of the second resistor is connected to the control terminal of the first switch device, and the second terminal of the second resistor is grounded.

[0007] Optionally, the mode switching circuit further includes multiple second switch modules; the second switch modules correspond to the power management terminal of the main control chip and the voltage conversion chip of the motherboard; the first terminal of the second switch module is connected to the power management terminal of the main control chip corresponding to the second switch module, the second terminal of the second switch module is connected to the enable terminal of the voltage conversion chip corresponding to the second switch module, and the control terminal of the second switch module is connected to the second terminal of the first resistor and the first terminal of the first switch module respectively; wherein, when the first switch module is turned on, the second switch module causes the power management function of the main control chip to stop controlling the enable terminal of the voltage conversion chip corresponding to the second switch module.

[0008] Optionally, the second switching module includes a second switching device, a third switching device, and a third resistor; in the second switching module, the first terminal of the second switching device is connected to the control terminal of the third switching device, the second terminal of the second switching device is grounded, and the control terminal of the second switching device is connected to the power management terminal of the main control chip corresponding to the second switching module; the first terminal of the third resistor is connected to the power supply, and the second terminal of the third resistor is connected to the first terminal of the third switching device and the enable terminal of the voltage conversion chip corresponding to the second switching module; the first terminal of the third switching device is connected to the enable terminal of the voltage conversion chip corresponding to the second switching module, the control terminal of the third switching device is connected to the second terminal of the first resistor and the first terminal of the first switching module, and the second terminal of the third switching device is grounded.

[0009] Optionally, the second switching module further includes a first diode; the positive terminal of the first diode is connected to the first terminal of the second switching device, and the negative terminal of the first diode is connected to the second terminal of the first resistor, the mode control terminal of the main control chip, and the power management enable terminal, respectively.

[0010] Optionally, the mode switching circuit further includes a third switch module; the first end of the third switch module is used to connect to the reset circuit of the motherboard, the control end of the third switch module is connected to the second end of the first resistor and the first end of the first switch module respectively, and the second end of the third switch module is connected to the reset end of the main control chip; wherein, when the first switch module is turned on, the third switch module causes the reset circuit to stop controlling the reset end of the main control chip.

[0011] Optionally, the third switching module includes a fourth switching device, a fifth switching device, and a fourth resistor; the first terminal of the fourth switching device is connected to the control terminal of the fifth switching device, the control terminal of the fourth switching device is used to connect to the reset circuit, and the second terminal of the fourth switching device is grounded; the first terminal of the fourth resistor is connected to the power supply, and the second terminal of the fourth resistor is connected to the first terminal of the fifth switching device and the reset terminal of the main control chip respectively; the first terminal of the fifth switching device is connected to the reset terminal of the main control chip, the control terminal of the fifth switching device is connected to the second terminal of the first resistor and the first terminal of the first switching module respectively, and the second terminal of the fifth switching device is grounded.

[0012] Optionally, the third switching module further includes a second diode; the positive terminal of the second diode is connected to the first terminal of the fourth switching device, and the negative terminal of the second diode is connected to the second terminal of the first resistor, the mode control terminal of the main control chip, and the power management enable terminal, respectively.

[0013] Secondly, this utility model embodiment also provides a motherboard, including the mode switching circuit as described in the first aspect.

[0014] Thirdly, embodiments of the present invention also provide an electronic device, including the mode switching circuit as described in the first aspect, or the motherboard as described in the second aspect.

[0015] In this embodiment of the invention, since the first end of the first resistor is connected to the power supply, the second end of the first resistor is connected to the first end of the first switch module, the second end of the first resistor is connected to the mode control terminal and the power management enable terminal of the main control chip on the motherboard, and the first end of the first switch module is connected to the mode control terminal and the power management enable terminal of the main control chip, the control terminal of the first switch module is connected to the debugger, and the second end of the first switch module is grounded, when the debugger controls the first switch module to be off, the first resistor can pull up the mode control terminal and the power management enable terminal of the main control chip to a high level. When the debugger controls the first switch module to be on, the first switch module can pull up the mode control terminal and the power management enable terminal of the main control chip to a high level. The power management enable pins are all pulled low. Since the main control chip switches to scan mode when its mode control pin is at the first level, and its power management function is disabled when its power management enable pin is at the first level, the debugger controls the first switch module to turn on when the first level is low. This pulls both the main control chip's mode control pin and power management enable pin low, causing the main control chip to switch to scan mode and disable its power management function. This allows for chip-level testing of the motherboard, significantly improving work efficiency compared to related technologies where workers need to disassemble electronic devices and manually adjust jumpers and circuits. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a mode switching circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another mode switching circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the specific structure of a mode switching circuit provided in an embodiment of the present invention.

[0018] Figure label: 10-First switch module; 20-Main control chip; 30-Debugger; 40-Second switch module; 50-Voltage conversion chip; 60-Third switch module; 70-Reset circuit; 80-Main board; 81-Debug interface; 90-Host computer; R1-First resistor; R2-Second resistor; R3-Third resistor; R4-Fourth resistor; R5-Fifth resistor; R6-Sixth resistor; Q1-First switch device; Q2-Second switch device; Q3-Third switch device; Q4-Fourth switch device; Q5-Fifth switch device; D1-First diode; D2-Second diode. Detailed Implementation

[0019] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Reference Figure 1 This utility model embodiment provides a mode switching circuit, including: a first resistor R1 and a first switch module 10; a first end of the first resistor R1 is connected to a power supply, a second end of the first resistor R1 is connected to a first end of the first switch module 10, and the second end of the first resistor R1 is used to connect to the mode control terminal and the power management enable terminal of the main control chip 20 of the motherboard 80 respectively; a first end of the first switch module 10 is used to connect to the mode control terminal and the power management enable terminal of the main control chip 20 respectively, the control terminal of the first switch module 10 is used to connect to a debugger 30, and the second end of the first switch module 10 is grounded; wherein, when the mode control terminal of the main control chip 20 is at a first level, the main control chip 20 switches to a scanning function mode; when the power management enable terminal of the main control chip 20 is at a first level, the power management function of the main control chip 20 is turned off.

[0021] In some embodiments, the power management function of the main control chip 20 includes the ACPI function of the main control chip 20. When the power management function of the main control chip 20 is turned off, the ACPI function of the main control chip 20 is turned off; when the power management function of the main control chip 20 is turned on, the ACPI function of the main control chip 20 is turned on.

[0022] In some embodiments, when it is necessary to debug the motherboard 80 of an electronic device, such as when it is necessary to update the software of the motherboard 80 of the electronic device, troubleshoot (debug) debugging, etc., it is necessary to switch the main control chip 20 of the motherboard 80 to the debugging function mode.

[0023] In some embodiments, the main control chip 20 switches to scanning mode, that is, the motherboard 80 switches to scanning mode; the main control chip 20 switches to debugging mode, that is, the motherboard 80 switches to debugging mode.

[0024] In some embodiments, when the mode control terminal of the main control chip 20 is at the second level, the main control chip 20 switches to the debugging function mode; the second level is the opposite of the first level.

[0025] In some embodiments, when the power management enable pin of the main control chip 20 is at the second level, the power management function of the main control chip 20 is enabled.

[0026] In some embodiments, the main control chip 20 may be a system-on-chip (SoC), a central processing unit (CPU), or other types of chips.

[0027] In some embodiments, the first switch module 10 is connected to the debugging interface 81, which is used to connect to the debugger 30, and the debugger 30 is used to connect to the host computer 90; the debugging interface 81 is located on the motherboard 80 of the electronic device.

[0028] In some embodiments, the operator performs a first operation on the host computer 90, causing the host computer 90 to send a first mode switching signal to the first switch module 10 through the debugger 30. The first switch module 10 is turned on, pulling both the mode control terminal and the power management enable terminal of the main control chip 20 low. The operator then performs a second operation on the host computer 90, causing the host computer 90 to send a second mode switching signal to the first switch module 10 through the debugger 30. The first switch module 10 is turned off, pulling both the mode control terminal and the power management enable terminal of the main control chip 20 high through the first resistor R1.

[0029] In some embodiments, the first mode switching signal is high and the second mode switching signal is low.

[0030] In some embodiments, debugger 30 is also referred to as emulator or downloader.

[0031] In some embodiments, debug interface 81 is a Joint Test Action Group (JTAG) debug interface, and debugger 30 is a JTAG debugger.

[0032] In some embodiments, the debugging function mode of the main control chip 20 is the JTAG debugging function mode, and the scanning function mode of the main control chip 20 is the JTAG scanning function mode.

[0033] In some embodiments, the main control chip 20 has multiple mode control terminals, for example, the main control chip 20 has two mode control terminals, and the second terminal of the first resistor R1 is connected to each mode control terminal of the main control chip 20.

[0034] In some embodiments, the main control chip 20 has two mode control terminals. When the first mode control terminal of the main control chip 20 is at a first level, the main control chip 20 switches to scanning mode; when the first mode control terminal of the main control chip 20 is at a second level, the main control chip 20 switches to debugging mode; when the second mode control terminal of the main control chip 20 is at a first level, the main control chip 20 switches to test mode; when the second mode control terminal of the main control chip 20 is at a second level, the main control chip 20 switches to normal operation mode. When the main control chip 20 is in test mode, the main control chip 20 allows the debugging mode to be enabled; when the main control chip 20 is in normal operation mode, the main control chip 20 disables the debugging mode. Therefore, when both mode control terminals of the main control chip 20 are at a first level, the scanning mode of the main control chip 20 is enabled.

[0035] In some embodiments, the mode switching circuit is located on the motherboard 80.

[0036] In some embodiments, when the first switch module 10 is turned on, the first end and the second end of the first switch module 10 are connected; when the first switch module 10 is turned off, the first end and the second end of the first switch module 10 are disconnected.

[0037] In this embodiment of the invention, since the first end of the first resistor R1 is connected to the power supply, the second end of the first resistor R1 is connected to the first end of the first switch module 10, the second end of the first resistor R1 is connected to the mode control terminal and the power management enable terminal of the main control chip 20 of the motherboard 80, and the first end of the first switch module 10 is connected to the mode control terminal and the power management enable terminal of the main control chip 20, the control terminal of the first switch module 10 is connected to the debugger 30, and the second end of the first switch module 10 is grounded, when the debugger 30 controls the first switch module 10 to be disconnected, the first resistor R1 can pull up the mode control terminal and the power management enable terminal of the main control chip 20 to a high level. When the debugger 30 controls the first switch module 10 to be turned on, the first switch module 10 can control the main control chip 20 to be turned on. Both the mode control terminal and the power management enable terminal of the main control chip 20 are pulled low. Since the main control chip 20 switches to the scanning function mode when the mode control terminal of the main control chip 20 is at the first level, and the power management function of the main control chip 20 is turned off when the power management enable terminal of the main control chip 20 is at the first level, when the first level is low, the debugger 30 controls the first switch module 10 to conduct, pulling both the mode control terminal and the power management enable terminal of the main control chip 20 low, so that the main control chip 20 switches to the scanning function mode and the power management function of the main control chip 20 is turned off. This enables chip-level testing of the motherboard 80, which improves work efficiency compared to the method in related technologies where staff need to disassemble electronic devices and then manually jumper and modify circuits. Furthermore, since the main control chip 20 switches to debug mode when the mode control terminal of the main control chip 20 is at the second level, and the power management function of the main control chip 20 is enabled when the power management enable terminal of the main control chip 20 is at the second level, and the first resistor R1 is a pull-up resistor, when the second level is high, the debugger 30 controls the first switch module 10 to open, and the first resistor R1 pulls both the mode control terminal and the power management enable terminal of the main control chip 20 to high level, so that the main control chip 20 switches to debug mode and the power management function of the main control chip 20 is enabled. Thus, when the first switch module 10 is open, the main control chip 20 switches to debug mode.

[0038] In other embodiments, the first level is high. Since the main control chip 20 switches to scanning mode when the mode control terminal of the main control chip 20 is at the first level, and the power management enable terminal of the main control chip 20 is at the first level, the power management function of the main control chip 20 is turned off. Then, the debugger 30 controls the first switch module 10 to open, and the first resistor R1 pulls both the mode control terminal and the power management enable terminal of the main control chip 20 to high level, so that the main control chip 20 switches to scanning mode and the power management function of the main control chip 20 is turned off. This enables chip-level testing of the motherboard 80, which improves work efficiency compared to the method in related technologies where workers need to disassemble electronic devices and then manually jumper and modify circuits. Furthermore, since the main control chip 20 switches to debug mode when the mode control terminal of the main control chip 20 is at the second level, and the power management function of the main control chip 20 is enabled when the power management enable terminal of the main control chip 20 is at the second level, when the second level is low, the debugger 30 controls the first switch module 10 to be turned on, pulling both the mode control terminal and the power management enable terminal of the main control chip 20 low. Thus, when the first switch module 10 is turned off, the main control chip 20 switches to debug mode.

[0039] Optionally, in some embodiments, the first switch module 10 includes a first switch device Q1 and a second resistor R2; the first terminal of the first switch device Q1 is used to connect to the mode control terminal and the power management enable terminal of the main control chip 20 respectively, the control terminal of the first switch device Q1 is used to connect to the debugger 30, and the second terminal of the first switch device Q1 is grounded; the first terminal of the second resistor R2 is connected to the control terminal of the first switch device Q1, and the second terminal of the second resistor R2 is grounded.

[0040] In some embodiments, the first switching device Q1 may be a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor), a bipolar transistor, or other types of switching devices. For example, the first switching device Q1 may be an NMOS transistor (Negative channel Metal-Oxide-Semiconductor). The first terminal of the first switching device Q1 is the drain of the first switching device Q1, the second terminal of the first switching device Q1 is the source of the first switching device Q1, and the control terminal of the first switching device Q1 is the gate of the first switching device Q1.

[0041] In some embodiments, the control terminal of the first switching device Q1 is connected to the debugging interface 81.

[0042] In this embodiment of the present invention, the second resistor R2 is a bias resistor. The debugger 30 can control the first switching device Q1 to be turned on. For example, the debugger 30 controls the control terminal of the first switching device Q1 to be at a high level, so that the first switching device Q1 is turned on. The debugger 30 can also control the first switching device Q1 to be turned off. For example, the debugger 30 controls the control terminal of the first switching device Q1 to be at a low level, so that the first switching device Q1 is turned off.

[0043] Optional, refer to Figure 2 In some embodiments, the mode switching circuit further includes a plurality of second switch modules 40; the second switch module 40 corresponds to the power management terminal of the main control chip 20 and the voltage conversion chip 50 of the motherboard 80; the first terminal of the second switch module 40 is connected to the power management terminal of the main control chip 20 corresponding to the second switch module 40, the second terminal of the second switch module 40 is connected to the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40, and the control terminal of the second switch module 40 is connected to the second terminal of the first resistor R1 and the first terminal of the first switch module 10 respectively; wherein, when the first switch module 10 is turned on, the second switch module 40 causes the power management function of the main control chip 20 to stop controlling the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40.

[0044] In some embodiments, the main control chip 20 has multiple power management terminals, and one second switch module 40 corresponds to one power management terminal of the main control chip 20.

[0045] In some embodiments, the motherboard 80 has multiple voltage conversion chips 50, with one second switch module 40 corresponding to one voltage conversion chip 50.

[0046] For example, the main control chip 20 has three power management terminals, the motherboard 80 has three voltage conversion chips 50, and the mode switching circuit also includes three second switch modules 40. The first terminal of the first second switch module 40 is connected to the first power management terminal of the main control chip 20, and the second terminal of the first second switch module 40 is connected to the enable terminal of the first voltage conversion chip 50. The first terminal of the second second switch module 40 is connected to the second power management terminal of the main control chip 20, and the second terminal of the second second switch module 40 is connected to the enable terminal of the second voltage conversion chip 50. The first terminal of the third second switch module 40 is connected to the third power management terminal of the main control chip 20, and the second terminal of the third second switch module 40 is connected to the enable terminal of the third voltage conversion chip 50.

[0047] In some embodiments, the voltage conversion chip 50 is used to connect to the power supply and the power-consuming devices of the motherboard 80 respectively, and converts the voltage of the power supply signal of the power supply and outputs it to the power-consuming devices of the motherboard 80 to supply power to the power-consuming devices of the motherboard 80. When the enable terminal of the voltage conversion chip 50 is at the first level, the voltage conversion chip 50 stops voltage conversion and output, and the power-consuming devices of the motherboard 80 are de-energized; when the enable terminal of the voltage conversion chip 50 is at the second level, the voltage conversion chip 50 converts the voltage of the power supply signal of the power supply and outputs it to the power-consuming devices of the motherboard 80, and the power-consuming devices of the motherboard 80 are energized.

[0048] In some embodiments, when the first switch module 10 is disconnected, the main control chip 20 controls the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40 through the second switch module 40 to realize the power management function of the main control chip 20. That is, when the power management terminal of the main control chip 20 corresponding to the second switch module 40 is at the first level, the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40 is at the first level; when the power management terminal of the main control chip 20 corresponding to the second switch module 40 is at the second level, the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40 is at the second level.

[0049] In this embodiment of the invention, the second switch module 40 causes the power management function of the main control chip 20 to stop controlling the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40. This is redundant with the power management function of the main control chip 20 being turned off through the power management enable terminal. In the event that the power management function of the main control chip 20 is turned off through the power management enable terminal, the debugger 30 controls the first switch module 10 to turn on, and the second switch module 40 causes the power management function of the main control chip 20 to stop controlling the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40. This avoids the power management function being accidentally triggered to control the motherboard 80 to power down or restart during chip-level testing of the motherboard 80, which would cause the chip-level test of the motherboard 80 to fail.

[0050] Optional, refer to Figure 3In some embodiments, the second switch module 40 includes a second switch device Q2, a third switch device Q3, and a third resistor R3. In the second switch module 40, the first terminal of the second switch device Q2 is connected to the control terminal of the third switch device Q3, the second terminal of the second switch device Q2 is grounded, and the control terminal of the second switch device Q2 is connected to the power management terminal of the main control chip 20 corresponding to the second switch module 40. The first terminal of the third resistor R3 is connected to the power supply, and the second terminal of the third resistor R3 is connected to the first terminal of the third switch device Q3 and the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40. The first terminal of the third switch device Q3 is connected to the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40, the control terminal of the third switch device Q3 is connected to the second terminal of the first resistor R1 and the first terminal of the first switch module 10, and the second terminal of the third switch device Q3 is grounded.

[0051] In some embodiments, the type of the second switching device Q2 includes a MOS transistor, a bipolar transistor, or other types of switching devices. For example, the type of the second switching device Q2 is an NMOS transistor. The first terminal of the second switching device Q2 is the drain of the second switching device Q2, the second terminal of the second switching device Q2 is the source of the second switching device Q2, and the control terminal of the second switching device Q2 is the gate of the second switching device Q2.

[0052] In some embodiments, the third switching device Q3 may be a MOS transistor, a triode, or other types of switching devices. For example, the third switching device Q3 may be an NMOS transistor. The first terminal of the third switching device Q3 is the drain of the third switching device Q3, the second terminal of the third switching device Q3 is the source of the third switching device Q3, and the control terminal of the third switching device Q3 is the gate of the third switching device Q3.

[0053] In some embodiments, the second switch module 40 further includes a fifth resistor R5, the first end of which is connected to the power supply, and the second end of which is connected to the first end of the second switch device Q2 and the control end of the third switch device Q3, respectively. The fifth resistor R5 is a pull-up resistor.

[0054] In this embodiment of the invention, the third resistor R3 is a pull-up resistor. The debugger 30 controls the first switch module 10 to conduct, pulling the control terminal of the third switch device Q3 low. When the third switch device Q3 is deactivated, the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40 is pulled high by the third resistor R3. The voltage conversion chip 50 converts the power supply signal voltage and outputs it to the power-consuming components of the motherboard 80, energizing the power-consuming components of the motherboard 80. When the debugger 30 controls the first switch module 10 to deactivate, and the power management terminal of the main control chip 20 corresponding to the second switch module 40 is high, the second switch device Q2 conducts, pulling the control terminal of the third switch device Q3 low. When the first switch module 10 is disconnected, the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40 is pulled up to a high level by the third resistor R3. The voltage conversion chip 50 converts the voltage of the power supply signal and outputs it to the power-consuming devices on the motherboard 80, thus powering on the power-consuming devices on the motherboard 80. When the first switch module 10 is disconnected by the debugger 30, and the power management terminal of the main control chip 20 corresponding to the second switch module 40 is at a low level, the second switch device Q2 is disconnected. The control terminal of the third switch device Q3 is pulled up to a high level by the fifth resistor R5, and the third switch device Q3 is turned on. This causes the enable terminal of the voltage conversion chip 50 corresponding to the second switch module 40 to be pulled down to a low level, and the voltage conversion chip 50 stops voltage conversion and output, thus powering off the power-consuming devices on the motherboard 80.

[0055] Optionally, in some embodiments, the second switching module 40 further includes a first diode D1; the positive terminal of the first diode D1 is connected to the first terminal of the second switching device Q2, and the negative terminal of the first diode D1 is connected to the second terminal of the first resistor R1, the mode control terminal and the power management enable terminal of the main control chip 20, respectively.

[0056] In this embodiment of the present invention, since the positive terminal of the first diode D1 is connected to the first terminal of the second switching device Q2, and the negative terminal of the first diode D1 is connected to the second terminal of the first resistor R1, the mode control terminal and the power management enable terminal of the main control chip 20 respectively, when the second switching device Q2 is turned on, the mode control terminal and the power management enable terminal of the main control chip 20 can be prevented from being pulled low, thereby preventing the main control chip 20 from being incorrectly switched to the scanning function mode and the power management function of the main control chip 20 from being incorrectly turned off.

[0057] Optionally, in some embodiments, the mode switching circuit further includes a third switch module 60; the first terminal of the third switch module 60 is connected to the reset circuit 70 of the motherboard 80, the control terminal of the third switch module 60 is connected to the second terminal of the first resistor R1 and the first terminal of the first switch module 10 respectively, and the second terminal of the third switch module 60 is connected to the reset terminal of the main control chip 20; wherein, when the first switch module 10 is turned on, the third switch module 60 causes the reset circuit 70 to stop controlling the reset terminal of the main control chip 20.

[0058] In some embodiments, the output terminal of the reset circuit 70 is connected to the first terminal of the third switch module 60, and the reset circuit 70 sends a reset control signal to the third switch module 60.

[0059] In some embodiments, when the first switch module 10 is disconnected, the reset circuit 70 controls the reset terminal of the main control chip 20 through the third switch module 60. That is, when the reset control signal is high, the reset terminal of the main control chip 20 is high and the main control chip 20 works normally; when the reset control signal is low, the reset terminal of the main control chip 20 is low and the main control chip 20 is reset.

[0060] In this embodiment of the present invention, when the first level is low, the debugger 30 controls the first switch module 10 to be turned on, pulling both the mode control terminal and the power management enable terminal of the main control chip 20 to low level, and the main control chip 20 switches to the scanning function mode. Since the third switch module 60 causes the reset circuit 70 to stop controlling the reset terminal of the main control chip 20 when the first switch module 10 is turned on, that is, when the main control chip 20 switches to the scanning function mode, the reset circuit 70 stops controlling the reset terminal of the main control chip 20, thereby avoiding the reset circuit 70 from erroneously resetting the main control chip 20 when the main control chip 20 switches to the scanning function mode.

[0061] In some embodiments, the second end of the third switch module 60 is also connected to other devices besides the main control chip 20 of the motherboard 80. The ACPI function includes control of resetting the motherboard 80. The main control chip 20 is connected to the reset circuit 70. The main control chip 20 resets the motherboard 80 through the reset circuit 70. That is, when the first switch module 10 is off, the main control chip 20 sends a reset control signal to the third switch module 60 through the reset circuit 70. When the reset control signal is high, the main control chip 20 and other devices of the motherboard 80 work normally. When the reset control signal is low, the main control chip 20 and other devices of the motherboard 80 are reset even though they are working normally. In addition, when the first switch module 10 is on, the third switch module 60 causes the reset circuit 70 to stop the reset control, thereby avoiding the reset circuit 70 from erroneously resetting the main control chip 20 and other devices of the motherboard 80 when the main control chip 20 switches to the scanning function mode.

[0062] Optionally, in some embodiments, the third switch module 60 includes a fourth switch device Q4, a fifth switch device Q5, and a fourth resistor R4; the first terminal of the fourth switch device Q4 is connected to the control terminal of the fifth switch device Q5, the control terminal of the fourth switch device Q4 is used to connect to the reset circuit 70, and the second terminal of the fourth switch device Q4 is grounded; the first terminal of the fourth resistor R4 is connected to the power supply, and the second terminal of the fourth resistor R4 is connected to the first terminal of the fifth switch device Q5 and the reset terminal of the main control chip 20 respectively; the first terminal of the fifth switch device Q5 is connected to the reset terminal of the main control chip 20, the control terminal of the fifth switch device Q5 is connected to the second terminal of the first resistor R1 and the first terminal of the first switch module 10 respectively, and the second terminal of the fifth switch device Q5 is grounded.

[0063] In some embodiments, the fourth switching device Q4 may be a MOSFET, a transistor, or other types of switching devices. For example, the fourth switching device Q4 may be an NMOS transistor. The first terminal of the fourth switching device Q4 is the drain of the fourth switching device Q4, the second terminal of the fourth switching device Q4 is the source of the fourth switching device Q4, and the control terminal of the fourth switching device Q4 is the gate of the fourth switching device Q4.

[0064] In some embodiments, the fifth switching device Q5 may be a MOSFET, a transistor, or other types of switching devices. For example, the fifth switching device Q5 may be an NMOS transistor. The first terminal of the fifth switching device Q5 is the drain of the fifth switching device Q5, the second terminal of the fifth switching device Q5 is the source of the fifth switching device Q5, and the control terminal of the fifth switching device Q5 is the gate of the fifth switching device Q5.

[0065] In some embodiments, the third switch module 60 further includes a sixth resistor R6, the first end of which is connected to the power supply, and the second end of which is connected to the first end of the fourth switch device Q4 and the control terminal of the fifth switch device Q5, respectively. The sixth resistor R6 is a pull-up resistor.

[0066] In this embodiment of the invention, the fourth resistor R4 is a pull-up resistor. The debugger 30 controls the first switch module 10 to conduct, pulling the control terminal of the fifth switch device Q5 low. When the fifth switch device Q5 is disconnected, the reset terminal of the main control chip 20 is pulled high by the fourth resistor R4, and the main control chip 20 operates normally. Alternatively, the debugger 30 controls the first switch module 10 to disconnect. When the reset control signal is high, the fourth switch device Q4 conducts, pulling the control terminal of the fifth switch device Q5 low. When the fifth switch device Q5 is disconnected, the reset terminal of the main control chip 20 is pulled high by the fourth resistor R4, and the main control chip 20 operates normally. Finally, the debugger 30 controls the first switch module 10 to disconnect. When the reset control signal is low, the fourth switch device Q4 is disconnected. The sixth resistor R6 pulls the control terminal of the fifth switch device Q5 high, turning it on and pulling the reset terminal of the main control chip 20 low, thus resetting the main control chip 20.

[0067] In some embodiments, the reset terminals of devices other than the main control chip 20 of the motherboard 80 are connected to the second terminal of the fourth resistor R4 and the first terminal of the fifth switch device Q5, respectively. The debugger 30 controls the first switch module 10 to conduct, pulling the control terminal of the fifth switch device Q5 low. When the fifth switch device Q5 is deactivated, the reset terminals of other devices on the motherboard 80 are pulled high by the fourth resistor R4, allowing the other devices on the motherboard 80 to operate normally. When the debugger 30 controls the first switch module 10 to deactivate, and the reset control signal is high, the fourth switch device Q5... When resistor Q4 is turned on, the control terminal of the fifth switch device Q5 is pulled down to a low level. When the fifth switch device Q5 is turned off, the reset terminal of other devices on the main board 80 is pulled up to a high level by the fourth resistor R4, and the other devices on the main board 80 work normally. When the first switch module 10 is turned off by the debugger 30, and the reset control signal is low, the fourth switch device Q4 is turned off. When the reset control signal is low, the control terminal of the fifth switch device Q5 is pulled up to a high level by the sixth resistor R6, and the fifth switch device Q5 is turned on. This pulls the reset terminal of other devices on the main board 80 down to a low level, and the other devices on the main board 80 are reset.

[0068] Optionally, in some embodiments, the third switch module 60 further includes a second diode D2; the positive terminal of the second diode D2 is connected to the first terminal of the fourth switch device Q4, and the negative terminal of the second diode D2 is connected to the second terminal of the first resistor R1, the mode control terminal and the power management enable terminal of the main control chip 20, respectively.

[0069] In this embodiment of the invention, since the positive terminal of the second diode D2 is connected to the first terminal of the fourth switching device Q4, and the negative terminal of the second diode D2 is connected to the second terminal of the first resistor R1, the mode control terminal and the power management enable terminal of the main control chip 20 respectively, when the fourth switching device Q4 is turned on, it can avoid erroneously pulling down the mode control terminal and the power management enable terminal of the main control chip 20, thereby avoiding the main control chip 20 from erroneously switching to the scanning function mode and the power management function of the main control chip 20 from being erroneously turned off.

[0070] In some embodiments, the mode switching process of the motherboard 80 includes: (1) the JTAG debugger and the host computer 90 are connected and powered on normally; (2) the motherboard 80 is running normally and is in the JTAG debugging function mode by default; (3) the JTAG debugger is connected to the JTAG debugging interface of the motherboard 80 of the electronic device; (4) when the motherboard 80 needs to enter the JTAG debugging function mode, the host computer 90 software enters the JTAG debugging function mode and sends a second mode switching signal to the JTAG debugging interface through the JTAG debugger, triggering the mode switching function of the mode switching circuit, so that the motherboard 80 enters the JTAG debugging function mode; (5) when the motherboard 80 needs to enter the JTAG scanning function mode, the host computer 90 software enters the JTAG scanning function mode and sends a first mode switching signal to the JTAG debugging interface through the JTAG debugger, triggering the mode switching function of the mode switching circuit, so that the motherboard 80 enters the JTAG scanning function mode.

[0071] This utility model embodiment also provides a motherboard 80, including the mode switching circuit as described above. The specific implementation process is similar to that described above, and will not be repeated here.

[0072] This utility model embodiment also provides an electronic device, including the mode switching circuit as described above, or the motherboard 80 as described above. The specific implementation process is similar to that described above, and will not be repeated here.

[0073] In related technologies, to perform chip-level testing on the motherboard, staff need to manually switch the JTAG mode. This involves disassembling the electronic device and manually switching the main control chip from JTAG debugging mode to JTAG scanning mode and disabling the main control chip's ACPI function by manually setting jumpers and modifying circuits. This increases the complexity of the operation. Furthermore, after a fault occurs, manually switching the JTAG mode again requires powering off the motherboard and manually modifying its circuitry, which destroys the fault scene and requires reproducing the fault, increasing time costs. This also makes it impossible to capture fault log information in a timely and effective manner through JTAG, affecting problem localization and analysis.

[0074] In this embodiment of the invention, when the first level is low, the debugger 30 controls the first switch module 10 to be turned on, pulling both the mode control terminal and the power management enable terminal of the main control chip 20 low. Since the main control chip 20 switches to JTAG scanning mode when the mode control terminal is at the first level, and the power management function of the main control chip 20 is turned off when the power management enable terminal is at the first level, chip-level testing of the motherboard 80 can be achieved when the first switch module 10 is turned on, without the need for manual JTAG mode switching by the staff, reducing the operational complexity of JTAG function mode switching, avoiding damage to the fault scene, facilitating timely capture of on-site fault log information, and accelerating problem location and analysis.

[0075] In summary, since the first end of the first resistor R1 is connected to the power supply, the second end of the first resistor R1 is connected to the first end of the first switch module 10, the second end of the first resistor R1 is connected to the mode control terminal and the power management enable terminal of the main control chip 20 of the motherboard 80, and the first end of the first switch module 10 is connected to the mode control terminal and the power management enable terminal of the main control chip 20, the control terminal of the first switch module 10 is connected to the debugger 30, and the second end of the first switch module 10 is grounded, when the debugger 30 controls the first switch module 10 to be off, the first resistor R1 can pull up the mode control terminal and the power management enable terminal of the main control chip 20 to a high level. When the debugger 30 controls the first switch module 10 to be on, the first switch module 10 can control the mode control terminal and the power management enable terminal of the main control chip 20 to a high level. Both the mode control terminal and the power management enable terminal are pulled low. Since the main control chip 20 switches to scan mode when the mode control terminal is at the first level, and the power management function of the main control chip 20 is disabled when the power management enable terminal is at the first level, when the first level is low, the debugger 30 controls the first switch module 10 to conduct, pulling both the mode control terminal and the power management enable terminal of the main control chip 20 low. This causes the main control chip 20 to switch to scan mode and disable its power management function, thereby enabling chip-level testing of the motherboard 80. Compared with related technologies where workers need to disassemble electronic devices and manually jumper and modify circuits, this improves work efficiency.

[0076] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device.

[0077] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

[0078] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A mode switching circuit, characterized in that, include: First resistor (R1) and first switch module (10); The first end of the first resistor (R1) is connected to the power supply, the second end of the first resistor (R1) is connected to the first end of the first switch module (10), and the second end of the first resistor (R1) is used to connect to the mode control terminal and the power management enable terminal of the main control chip (20) of the motherboard (80) respectively. The first terminal of the first switch module (10) is used to connect to the mode control terminal and the power management enable terminal of the main control chip (20) respectively. The control terminal of the first switch module (10) is used to connect to the debugger (30). The second terminal of the first switch module (10) is grounded. When the mode control terminal of the main control chip (20) is at the first level, the main control chip (20) switches to the scanning function mode; when the power management enable terminal of the main control chip (20) is at the first level, the power management function of the main control chip (20) is turned off.

2. The mode switching circuit according to claim 1, characterized in that, The first switching module (10) includes a first switching device (Q1) and a second resistor (R2); The first terminal of the first switching device (Q1) is used to connect to the mode control terminal and the power management enable terminal of the main control chip (20) respectively, the control terminal of the first switching device (Q1) is used to connect to the debugger (30), and the second terminal of the first switching device (Q1) is grounded. The first end of the second resistor (R2) is connected to the control terminal of the first switching device (Q1), and the second end of the second resistor (R2) is grounded.

3. The mode switching circuit according to claim 1, characterized in that, The mode switching circuit also includes multiple second switch modules (40); the second switch module (40) corresponds to the power management terminal of the main control chip (20), and the second switch module (40) corresponds to the voltage conversion chip (50) of the motherboard (80); The first end of the second switch module (40) is connected to the power management terminal of the main control chip (20) corresponding to the second switch module (40), the second end of the second switch module (40) is connected to the enable terminal of the voltage conversion chip (50) corresponding to the second switch module (40), and the control terminal of the second switch module (40) is connected to the second end of the first resistor (R1) and the first end of the first switch module (10) respectively. When the first switch module (10) is turned on, the second switch module (40) causes the power management function of the main control chip (20) to stop controlling the enable terminal of the voltage conversion chip (50) corresponding to the second switch module (40).

4. The mode switching circuit according to claim 3, characterized in that, The second switching module (40) includes a second switching device (Q2), a third switching device (Q3), and a third resistor (R3); In the second switch module (40), the first end of the second switch device (Q2) is connected to the control end of the third switch device (Q3), the second end of the second switch device (Q2) is grounded, and the control end of the second switch device (Q2) is connected to the power management end of the main control chip (20) corresponding to the second switch module (40). The first end of the third resistor (R3) is connected to the power supply, and the second end of the third resistor (R3) is connected to the first end of the third switching device (Q3) and the enable end of the voltage conversion chip (50) corresponding to the second switching module (40), respectively. The first terminal of the third switching device (Q3) is connected to the enable terminal of the voltage conversion chip (50) corresponding to the second switching module (40). The control terminal of the third switching device (Q3) is connected to the second terminal of the first resistor (R1) and the first terminal of the first switching module (10) respectively. The second terminal of the third switching device (Q3) is grounded.

5. The mode switching circuit according to claim 4, characterized in that, The second switching module (40) also includes a first diode (D1); The positive terminal of the first diode (D1) is connected to the first terminal of the second switching device (Q2), and the negative terminal of the first diode (D1) is connected to the second terminal of the first resistor (R1), the mode control terminal and the power management enable terminal of the main control chip (20).

6. The mode switching circuit according to claim 1, characterized in that, The mode switching circuit also includes a third switch module (60). The first end of the third switch module (60) is used to connect to the reset circuit (70) of the motherboard (80), the control end of the third switch module (60) is connected to the second end of the first resistor (R1) and the first end of the first switch module (10) respectively, and the second end of the third switch module (60) is connected to the reset end of the main control chip (20). When the first switch module (10) is turned on, the third switch module (60) causes the reset circuit (70) to stop controlling the reset terminal of the main control chip (20).

7. The mode switching circuit according to claim 6, characterized in that, The third switch module (60) includes a fourth switch device (Q4), a fifth switch device (Q5), and a fourth resistor (R4). The first terminal of the fourth switching device (Q4) is connected to the control terminal of the fifth switching device (Q5), the control terminal of the fourth switching device (Q4) is used to connect to the reset circuit (70), and the second terminal of the fourth switching device (Q4) is grounded; The first end of the fourth resistor (R4) is connected to the power supply, and the second end of the fourth resistor (R4) is connected to the first end of the fifth switching device (Q5) and the reset end of the main control chip (20), respectively. The first terminal of the fifth switching device (Q5) is connected to the reset terminal of the main control chip (20), the control terminal of the fifth switching device (Q5) is connected to the second terminal of the first resistor (R1) and the first terminal of the first switching module (10) respectively, and the second terminal of the fifth switching device (Q5) is grounded.

8. The mode switching circuit according to claim 7, characterized in that, The third switching module (60) also includes a second diode (D2); The positive terminal of the second diode (D2) is connected to the first terminal of the fourth switching device (Q4), and the negative terminal of the second diode (D2) is connected to the second terminal of the first resistor (R1), the mode control terminal and the power management enable terminal of the main control chip (20).

9. A motherboard (80), characterized in that, Includes the mode switching circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the mode switching circuit as described in any one of claims 1 to 8, or the motherboard (80) as described in claim 9.

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