A dead-time protection circuit of H-bridge drive

Abstract

The utility model discloses a kind of dead zone protection circuits of H bridge drive, including drive chip, the 2 pin of drive chip is connected in series with the 6 pin of first logic chip, the 3 pin of drive chip is connected in series with the 8 pin of second logic chip, the 4 pin of first logic chip is connected in series with the 4 pin of first shift register, the 10 pin of second logic chip is connected in series with the 12 pin of second shift register, the 5 pin of first logic chip is connected in series with the 9 pin of second logic chip, the 7 pin of first shift register is connected in series with the 14 pin of second shift register, the 9 pin of first shift register is connected in series with the 1 pin of second shift register, the 6 pin of first shift register is connected in series with the 15 pin of second shift register, the 7 pin of first shift register is equipped with third logic chip with 6 pin. By changing the frequency of clock signal, adjust shift delay, and then control the time interval of upper and lower bridge arm, realize the flexible setting of dead zone time.

Description

Technical Field

[0001] This utility model relates to the field of circuit protection technology, and in particular to a dead-time protection circuit driven by an H-bridge. Background Technology

[0002] In motor control and solenoid valve control, dead-time protection in H-bridge drive circuits is used to prevent direct short circuits between the upper and lower bridge arms. In existing technologies, dead-time protection is implemented using a microcontroller. However, integrated microcontrollers require software settings, and the dead time is typically set by configuring specific registers of the timer. Precise calculations of the system clock, division factor, and register configuration parameters are necessary; any calculation errors can lead to improper dead-time settings. Furthermore, when the motor load, power supply voltage, or power device model changes, the software code must be modified and the microcontroller reprogrammed, making dynamic adaptive adjustment impossible. Utility Model Content

[0003] To solve the above problems, the technical solution adopted by this utility model is as follows:

[0004] A dead-time protection circuit for an H-bridge driver includes a driver chip, a first logic chip, a first shift register, a second logic chip, and a second shift register. Pin 2 of the driver chip is connected in series with pin 6 of the first logic chip, pin 3 of the driver chip is connected in series with pin 8 of the second logic chip, pin 4 of the first logic chip is connected in series with pin 4 of the first shift register, pin 10 of the second logic chip is connected in series with pin 12 of the second shift register, pin 5 of the first logic chip is connected in series with pin 9 of the second logic chip, pin 7 of the first shift register is connected in series with pin 14 of the second shift register, pin 9 of the first shift register is connected in series with pin 1 of the second shift register, pin 6 of the first shift register is connected in series with pin 15 of the second shift register, and a third logic chip is connected in parallel between pins 7 and 6 of the first shift register.

[0005] Furthermore, pins 6, 7, and 8 of the driver chip are connected in parallel and then connected in series with pin 1 of the driver chip, and pin 1 of the driver chip is also connected in series with diode D0.

[0006] Furthermore, the upper bridge arm power transistor Q0 is connected in series to pin 7 of the driver chip, and the lower bridge arm power transistor Q1 is connected in series to pin 4 of the driver chip via pin 5.

[0007] Furthermore, the upper arm power transistor Q0 is connected to the lower arm power transistor Q1.

[0008] The beneficial effects of this invention are: by changing the frequency (or period) of the 1M clock signal, the shift delay of the shift register can be adjusted, thereby controlling the time interval between the upper and lower bridge arms being turned on / off, realizing flexible setting of the dead time, and avoiding common-mode conduction of the power transistor. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the invention.

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the circuit structure;

[0012] Figure 2 This is the signal output logic diagram. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0014] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0015] refer to Figure 1 and Figure 2 As shown, one embodiment of this utility model is as follows:

[0016] A dead-time protection circuit for an H-bridge driver includes a driver chip, a first logic chip, a first shift register, a second logic chip, and a second shift register. Pin 2 of the driver chip is connected in series with pin 6 of the first logic chip, pin 3 of the driver chip is connected in series with pin 8 of the second logic chip, pin 4 of the first logic chip is connected in series with pin 4 of the first shift register, pin 10 of the second logic chip is connected in series with pin 12 of the second shift register, pin 5 of the first logic chip is connected in series with pin 9 of the second logic chip, pin 7 of the first shift register is connected in series with pin 14 of the second shift register, pin 9 of the first shift register is connected in series with pin 1 of the second shift register, pin 6 of the first shift register is connected in series with pin 15 of the second shift register, and a third logic chip is connected in parallel between pins 7 and 6 of the first shift register.

[0017] Specifically, pins 6, 7, and 8 of the driver chip are connected in parallel and then connected in series with pin 1 of the driver chip, and a diode D0 is also connected in series with pin 1 of the driver chip.

[0018] Specifically, the upper bridge arm power transistor Q0 is connected in series to pin 7 of the driver chip, and the lower bridge arm power transistor Q1 is connected in series to pin 4 of the driver chip after being connected in series to pin 5 of the driver chip.

[0019] Specifically, the upper arm power transistor Q0 is connected to the lower arm power transistor Q1.

[0020] In this utility model, the driver chip is model IRS2007, the first shift register and the second shift register are both model CD4015, the first logic chip and the second logic chip are both model 74LS08, and the third logic chip is model 74HC4049.

[0021] The third logic chip is used to convert the input TTL drive signal into an inverted TTL signal, providing data input for the second shift register and reset logic for the first shift register. The TTL drive signal is converted into an inverted TTL signal by the third logic chip and sent to the serial data input terminal (pin 15) of the second shift register. The reset terminal (pin 6) of the first shift register is directly connected to the TTL signal, and the reset terminal (pin 14) of the second shift register is connected to the TTL signal. Both are high-level reset.

[0022] The serial data input terminal (pin 7) of the first shift register is always connected to a high level (V5). The clock signal is a TTL drive signal. When the TTL signal changes, the first shift register shifts at the clock edge. The output pin Q1 (pin 4) responds to the input logic after a 1μs delay. The reset terminal (pin 6) is a TTL signal. When it is high, all outputs (Q0~Q3=0) are immediately reset.

[0023] The serial data input (pin 15) of the second shift register is connected to an inverted TTL signal, with a 1MHz clock signal. The reset input (pin 14) is a TTL signal; a high level immediately resets all outputs. The inverted TTL signal serves as the data input and is output from Q1 (pin 12) after a 1μs delay triggered by the clock.

[0024] The first and second logic chips receive signals from pin 4 (upper bridge arm signal) of the first shift register and pin 12 (lower bridge arm signal) of the second shift register, respectively, and control their outputs via an enable signal (active high). The AND gate output signals of the first and second logic chips are connected to HIN (pin 2 upper bridge arm input) and LIN (pin 3 lower bridge arm input) of the driver chip. After being amplified by the driver circuit inside the driver chip, they drive the upper bridge arm power transistor Q0 and the lower bridge arm power transistor Q1 through HO (pin 7 high-side gate output) and LO (pin 5 low-side gate output).

[0025] When the TTL drive signal changes from low (0) to high (1), the upper bridge arm is turned on. When the TTL signal is 0, the reset terminal (R=0) of the first shift register and pin 4 of the first shift register are initially 0. When the TTL signal changes to 1, the reset terminal (R=1) of the first shift register is invalid. The clock signal triggers the shift, and pin 4 changes from 0 to 1 (upper bridge arm drive signal) after a 1μs delay. The first logic chip of the AND gate outputs a high level to the HIN of the driver chip, and the HO of the driver chip outputs the drive voltage, turning on the upper bridge arm power transistor Q0. When the lower bridge arm is turned off, when the TTL signal changes to 1, the reset terminal (R=1) of the second shift register is immediately reset, and pin 12 is 0. At the same time, the inverted TTL signal is 0, the data input of the second shift register is 0, the lower bridge arm drive signal remains 0, the LO of the driver chip outputs a low level, and the lower bridge arm power transistor Q1 is turned off. The time difference between the upper bridge arm’s turn-on delay (1μs) and the lower bridge arm’s immediate turn-off creates a dead zone, preventing the upper and lower bridge arms from conducting simultaneously.

[0026] When the TTL drive signal changes from high (1) to low (0), the upper bridge arm is turned off. When the TTL signal becomes 0, the reset terminal (R=0) of the first shift register is invalid, but the inverted TTL signal is 1, and the data input of the first shift register is 1. Under the clock trigger, the upper bridge arm power transistor Q0 should be turned on after a delay, but at this time the reset terminal (R=TTL=0) of the first shift register is not actually reset. It needs to be corrected in conjunction with the reset logic. That is, when TTL becomes 0, R=0 of the first shift register (reset is invalid), but the inverted TTL signal = 1 is input to pin 7 of the first shift register. After clock shift, Q1 outputs 0, and the upper bridge arm power transistor Q0 is turned off. When the lower bridge arm is turned on and the TTL becomes 0, the inverted TTL=1 input is sent to pin 15 of the first shift register. The reset input of the first shift register (R=TTL=0) is invalid. After a 1μs delay, the clock trigger pin 12 changes from low to high (lower bridge arm drive signal). The second logic chip outputs a high level to the LIN of the driver chip, and the LO of the driver chip outputs the drive voltage, turning on the lower bridge arm power transistor Q1. The time difference between the lower bridge arm turn-on delay (1μs) and the immediate turn-off of the upper bridge arm constitutes the reverse dead time. By changing the frequency (or period) of the 1M clock signal, the shift delay of the shift register can be adjusted (currently 1μs), thereby controlling the time interval between the turn-on / turn-off of the upper and lower bridge arms, achieving flexible setting of the dead time, and avoiding common-mode conduction of the power transistor.

[0027] The following points need to be explained:

[0028] (1) Unless otherwise defined, the same reference numerals in the embodiments and drawings of this disclosure have the same meaning.

[0029] (2) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0030] (3) For clarity, components or areas are enlarged in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be an intermediate element.

[0031] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A dead-time protection circuit for H-bridge drive, characterized in that: The system includes a driver chip, a first logic chip, a first shift register, a second logic chip, and a second shift register. Pin 2 of the driver chip is connected in series with pin 6 of the first logic chip, pin 3 of the driver chip is connected in series with pin 8 of the second logic chip, pin 4 of the first logic chip is connected in series with pin 4 of the first shift register, pin 10 of the second logic chip is connected in series with pin 12 of the second shift register, pin 5 of the first logic chip is connected in series with pin 9 of the second logic chip, pin 7 of the first shift register is connected in series with pin 14 of the second shift register, pin 9 of the first shift register is connected in series with pin 1 of the second shift register, pin 6 of the first shift register is connected in series with pin 15 of the second shift register, and a third logic chip is connected in parallel between pins 7 and 6 of the first shift register.

2. The dead-time protection circuit for H-bridge drive according to claim 1, characterized in that: Pins 6, 7, and 8 of the driver chip are connected in parallel and then connected in series with pin 1 of the driver chip. A diode D0 is also connected in series with pin 1 of the driver chip.

3. The dead-time protection circuit for H-bridge drive according to claim 2, characterized in that: The driver chip has an upper bridge arm power transistor Q0 connected in series at pin 7, and a lower bridge arm power transistor Q1 connected in series at pin 5 and then connected to pin 4 of the driver chip.

4. The dead-time protection circuit for H-bridge drive according to claim 3, characterized in that: The upper arm power transistor Q0 is connected to the lower arm power transistor Q1.

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