Single-bridge-arm integrated three-level boost inverter for building photovoltaic systems and control circuit thereof
Patent Information
- Application Number
- CN202522328791.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-03
- Publication Date
- 2026-10-30
- Estimated Expiration
- 2035-11-03
AI Technical Summary
[0006]然而，一体化光伏系统的安装空间有限，对设备的紧凑性和高效性的要求也极为严格
(1)将传统的两级式半桥三电平逆变器（Boost变换器+半桥三电平逆变器）的输出端负极从直流母线单元的中点O点接入到Boost变换器中两个开关管的连接点，使两个开关管形成升压桥臂，进而实现了从两级式半桥三电平逆变器到单级式升压逆变器，减少了能量流动的级数，且只需传统的输出端电压电流双闭环控制即可实现自均压。
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Figure CN224923647U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of electrical technology, specifically relating to a single-bridge integrated three-level boost inverter and its control circuit for building photovoltaic systems. Background Technology
[0002] In industrial parks, the application of photovoltaic-storage-DC-flexible power systems (PV + energy storage + DC power distribution + flexible power consumption) is becoming an important solution for achieving efficient energy use and sustainable development. As concentrated energy consumption areas, industrial parks have extremely high demands for stable, economical, and environmentally friendly power supply. By integrating photovoltaic power generation, energy storage technology, and intelligent energy management, PV-storage-DC-flexible power systems can not only provide clean and renewable electricity to industrial parks but also effectively reduce electricity costs, decrease dependence on traditional power grids, and help industrial parks achieve a green and low-carbon transformation.
[0003] In a photovoltaic-storage-direct-current-flexible system, the importance of building-integrated photovoltaics (BIPV) is self-evident. As the core energy supply unit of the system, BIPV not only provides a clean and renewable source of electricity for the park, but also achieves a deep integration of energy production and building function through innovative building integration methods. First, BIPV fully utilizes building surface space, integrating photovoltaic modules into the roof and other parts, saving land resources and improving the aesthetics and functionality of the building. Furthermore, BIPV can be combined with energy storage technology to effectively solve the intermittency problem of photovoltaic power generation, ensuring the stability and reliability of energy supply. With the support of flexible power utilization technology, BIPV can also dynamically adjust energy distribution according to the actual needs of the building, achieving optimized energy utilization. Therefore, BIPV is not only the core of energy production in a photovoltaic-storage-direct-current-flexible system, but also a key technological guarantee for achieving efficient, stable, and sustainable energy utilization.
[0004] However, the DC voltage generated by photovoltaic (PV) modules in integrated PV systems is typically low, and direct inversion cannot meet the voltage requirements of AC loads within the park or for grid connection. Therefore, inverters with boost converter capabilities are needed to raise the output voltage of the PV modules to a suitable level and convert it to AC power, ensuring efficient energy utilization and stable output. In integrated PV systems, the boost inverter is not only the core equipment for energy conversion but also a key technological guarantee for achieving efficient and stable system operation. Through boost inverters, PV-energy storage systems can better adapt to the diverse energy demands of buildings, providing strong technical support for achieving green building and sustainable development goals.
[0005] The application of three-level boost inverters is becoming an important technological choice for improving system performance. Compared with two-level inverters, three-level boost inverters have lower harmonic distortion and better electromagnetic compatibility, which can significantly improve the power generation quality and stability of photovoltaic systems. In building-integrated photovoltaic (BIPV) systems, three-level boost inverters can better adapt to complex building environments and diverse energy demands, while reducing energy loss and extending equipment life.
[0006] However, integrated photovoltaic systems have limited installation space and extremely stringent requirements for equipment compactness and efficiency. Traditional three-level boost inverters often employ a two-stage structure to achieve boost inversion. This structure adds an extra boost circuit before the inverter, which not only increases the cost and control complexity of the integrated photovoltaic system and increases its size, but also reduces energy transfer efficiency. Utility Model Content
[0007] In view of this, the present invention provides a single-bridge integrated three-level boost inverter and its control circuit for building photovoltaic systems.
[0008] To achieve the above objectives, the technical solution provided by this utility model embodiment is as follows: Input capacitor C in Input inductance L in Anti-reverse diode D1, DC bus unit, output filter inductor L f Output filter capacitor C f Boost bridge arm and three-level inverter bridge arm; The booster arm includes an upper switch S1 and a lower switch S2; The three-level inverter bridge arm includes an upper switch S3, a lower switch S6, a clamping switch S4, and a clamping switch S5 connected in reverse series with the clamping switch S4. The DC bus unit includes a first DC bus capacitor C. dc1 Second DC bus capacitor C dc2 ; Input capacitor C in The first terminal is connected to the input inductor L in The first end is connected and serves as the positive terminal of the input. Input inductance L in The second terminal is connected to the anode of the anti-reverse diode D1; The cathode of the anti-reverse diode D1 is at the midpoint of the boost bridge arm, and the output filter capacitor C. f The first terminal is connected and serves as the negative terminal of the output. Output filter capacitor C f The second terminal is connected to the output filter inductor L fThe first end is connected and serves as the positive terminal of the output. Output filter inductor L f The second end is connected to the midpoint of the three-level inverter bridge arm; The first end of the DC bus unit is connected to the collectors of the upper switching transistors S1 and S3, and the midpoint is connected to the collector of the clamping switching transistor S4. The second end is connected to the emitter of the lower switching transistors S2 and S6, and the input capacitor C. in The second end is connected to serve as the negative terminal of the input.
[0009] In some embodiments of this utility model, the input inductance L in The inductance value L must satisfy:
[0010] In the formula, U dc U is the average terminal voltage of the DC bus unit. pv P is the average value of the input voltage. o,max f is the maximum power at the output terminal. s1,min This is the minimum switching frequency of the boost bridge arm.
[0011] This utility model also provides a control circuit for the single-bridge integrated three-level boost inverter, including: A DC bus voltage sensor, connected in parallel with the DC bus unit, is used to acquire the terminal voltage u of the DC bus unit. dc ; The output voltage sensor, and its output filter capacitor C f Parallel connection, used to acquire the voltage u at the output terminal. o ; An output current sensor, connected in series with the load of the single-bridge integrated three-level boost inverter, is used to collect the output current i. o ; The main control unit, connected to the DC bus voltage sensor, the output voltage sensor, and the output current sensor, is used to analyze the terminal voltage u of the acquired DC bus unit. dc Output voltage u o and the output current i o The signals are processed to obtain the drive signals for each switching transistor; A driving circuit, which is connected to the main control unit, is used to drive the switching transistors according to the driving signals of each switching transistor output by the main control unit.
[0012] The main control unit includes a boost bridge arm switch drive signal generation unit; The boost bridge arm switch drive signal generation unit includes a DC bus voltage error calculation module, a DC bus voltage controller module, a frequency limiting module, and a pulse frequency modulation module connected in sequence. The DC bus voltage error calculation module is used to calculate the terminal voltage u of the DC bus unit. dc Compared with the benchmark value u dc,ref The difference is calculated to obtain the DC bus voltage error signal e1; The DC bus voltage controller module is used to generate a DC bus voltage frequency modulation signal c1 based on the received DC bus voltage error signal e1. The frequency limiting module is used to limit the frequency signal f1 by upper and lower amplitude based on the received DC bus voltage frequency modulation signal c1; A pulse frequency modulation module is used to generate drive signals for all the switching transistors of the boost bridge arm based on the received frequency signal f1. The main control unit includes a three-level inverter bridge arm switch drive signal generation unit; The three-level inverter bridge arm switch drive signal generation unit includes, in sequence, an output voltage error calculation module, an output voltage controller module, an output current error calculation module, a proportional-integral controller module, an output voltage limiting module, and a pulse width modulation module: The output voltage error calculation module is used to calculate the voltage u. o With the output voltage reference value u o,ref The difference is calculated to obtain the output voltage error signal e2; The output voltage controller module is used to generate an output voltage control signal c2 based on the received output voltage error signal e2. The output current error calculation module is used to compare the output voltage control signal c2 with the output current i o The difference between the signals is used to obtain the output current error signal e3; The proportional-integral controller module is used to generate an output voltage control signal c3 based on the received output current error signal e3. The output voltage limiting module is used to limit the output voltage control signal c3 at both the upper and lower ends to obtain the output voltage modulation signal u. rac ; The pulse width modulation module is used to modulate the received output voltage signal u. rac This generates drive signals for all the switching transistors of the three-level inverter bridge arm.
[0013] The pulse frequency modulation module includes a carrier generation module and a boost bridge arm drive generation module connected in sequence: The carrier generation module is used to generate a first bipolar triangular carrier signal u with a corresponding frequency based on the received frequency signal f1. c1 ; The boost bridge arm drive generation module is used to generate a DC modulation signal u with a value of zero. rdc With the first bipolar triangular carrier signal u c1 The comparison generates complementary drive signals for the upper switch S1 and the lower switch S2, with a constant duty cycle of 0.5.
[0014] Compared with the prior art, the single-arm integrated three-level boost inverter and its control circuit for building photovoltaic systems proposed in this utility model have the following technical advantages: (1) The negative output terminal of the traditional two-stage half-bridge three-level inverter (Boost converter + half-bridge three-level inverter) is connected from the midpoint O of the DC bus unit to the connection point of the two switching transistors in the Boost converter, so that the two switching transistors form a boost bridge arm, thereby realizing the transformation from a two-stage half-bridge three-level inverter to a single-stage boost inverter, reducing the number of energy flow stages, and only requiring traditional output voltage and current dual closed-loop control to achieve self-equalization.
[0015] (2) It can enable the first DC bus capacitor and the second DC bus capacitor to supply power to the load simultaneously, reducing the pressure on the load supply of a single DC bus capacitor and reducing the capacity of the first DC bus capacitor C. dc1 With the second DC bus capacitor C dc2 The capacity.
[0016] (3) The input inductor current is in DCM mode, which suppresses the low-frequency ripple of the input inductor current. No additional low-frequency ripple suppression strategy or sensor to collect the input inductor current is required, which reduces the computational burden of the main control unit and the number of sensors. Attached Figure Description
[0017] Figure 1 A schematic diagram of the structure of the single-bridge integrated three-level boost inverter provided by this utility model; Figure 2 for Figure 1 The diagram shows the main operating waveforms of a single-bridge integrated three-level boost inverter. Figures 3 to 8 for Figure 1 The equivalent circuit diagram of the single-bridge integrated three-level boost inverter shown is shown under different switching states. Figure 9 for Figure 1 The control circuit diagram of the single-bridge integrated three-level boost inverter is shown below. Figure 10 for Figure 1The circuit diagram of the main control unit of the single-bridge integrated three-level boost inverter is shown below. Figure 11 , Figure 12 for Figure 1 The simulation waveforms of the single-bridge integrated three-level boost inverter under different output power conditions are shown. Figure 13 , Figure 14 for Figure 1 The single-bridge integrated three-level boost inverter shown has an average input voltage U pv =100V, output power P o =Partial waveform diagram under 500W operating conditions; Figure 15 for Figure 1 The single-bridge integrated three-level boost inverter shown has an output power P at the end. o =Partial waveform diagram of switching from 250W to 500W; Figure 16 for Figure 1 The single-bridge integrated three-level boost inverter shown has an output power P at the end. o =Partial waveform diagram of switching from 500W to 250W. Detailed Implementation
[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this utility model.
[0019] This utility model embodiment discloses a method such as Figure 1 The single-bridge integrated three-level boost inverter shown includes an input capacitor C. in Input inductance L in Anti-reverse diode D1, DC bus unit, output filter inductor L f Output filter capacitor C f Boost bridge arm and three-level inverter bridge arm; The booster arm includes an upper switch S1 and a lower switch S2; The three-level inverter bridge arm includes an upper switch S3, a lower switch S6, a clamping switch S4, and a clamping switch S5 connected in reverse series with the clamping switch S4. The DC bus unit includes a first DC bus capacitor C. dc1 Second DC bus capacitor C dc2 ; Input capacitor C inThe first terminal is connected to the input inductor L in The first end is connected and serves as the positive terminal of the input. Input inductance L in The second terminal is connected to the anode of the anti-reverse diode D1; The cathode of the anti-reverse diode D1 is at the midpoint of the boost bridge arm, and the output filter capacitor C. f The first terminal is connected and serves as the negative terminal of the output. Output filter capacitor C f The second terminal is connected to the output filter inductor L f The first end is connected and serves as the positive terminal of the output. Output filter inductor L f The second end is connected to the midpoint of the three-level inverter bridge arm; The positive terminal (first terminal) of the DC bus unit is connected to the collectors of the upper switching transistors S1 and S3, the midpoint is connected to the collector of the clamping switching transistor S4, and the negative terminal (second terminal) is connected to the emitters of the lower switching transistors S2 and S6, and the input capacitor C. in The second end is connected to serve as the negative terminal of the input.
[0020] To simplify the analysis, the following assumptions are made: Input capacitance C in Input inductance L in Anti-reverse diode D1, DC bus unit, output filter inductor L f Output filter capacitor C f The boost bridge arm and the three-level inverter bridge arm are both ideal devices.
[0021] The theoretical waveforms of key signals in the single-bridge integrated three-level boost inverter provided by this utility model are shown below. Figure 2 As shown, it can be seen that the first DC bus capacitor C dc1 With the second DC bus capacitor C dc2 The connection point is used as the potential reference point O, and the voltage u at the midpoint A of the boost bridge arm is... AO There are a total of +U dc / 2 with -U dc / 2 Two cases, the midpoint voltage u of the three-level inverter bridge arm BO There is +U dc / 2 with -U dc In the cases of / 2 and 0, the voltage at the midpoint of the bridge arm is specified as +U. dc / 2 is the "+1" state, -U dc / 2 represents the "-1" state, and 0 represents the "0" state. Therefore, the inverter theoretically has 6 switching states, which are: (1) When switches S2, S4, and S5 are turned on and the remaining switches are turned off, the boost bridge arm is in the "-1" state and the three-level inverter bridge arm is in the "0" state, such as Figure 3 As shown; (2) When switches S2, S3, and S4 are turned on and the remaining switches are turned off, the boost bridge arm is in the "-1" state and the three-level inverter bridge arm is in the "+1" state, such as Figure 4 As shown; (3) Switches S2, S5, and S6 are turned on, and the remaining switches are turned off. The boost bridge arm is in the "-1" state, and the three-level inverter bridge arm is in the "-1" state, such as... Figure 5 As shown; (4) Switches S1, S4, and S5 are turned on, and the remaining switches are turned off. The boost bridge arm is in the "+1" state, and the three-level inverter bridge arm is in the "0" state. Figure 6 As shown; (5) Switches S1, S3, and S4 are turned on, and the remaining switches are turned off. The boost bridge arm is in the "+1" state, and the three-level inverter bridge arm is in the "+1" state, such as... Figure 7 As shown; (6) Switches S2, S5, and S6 are turned on, and the remaining switches are turned off. The boost bridge arm is in the "+1" state, and the three-level inverter bridge arm is in the "-1" state. Figure 8 As shown.
[0022] from Figure 3 and Figure 7 The current flow in the equivalent circuit diagram of the switching state shows that the proposed first DC bus capacitor and second DC bus capacitor simultaneously supply power to the output terminal, unlike the traditional two-stage half-bridge inverter DC bus unit where only one capacitor supplies power to the output terminal at any given time. Therefore, reducing the power supply pressure on a single capacitor allows for a reduction in the capacitance values of the first and second DC bus capacitors.
[0023] like Figure 2 As shown, the three-level inverter bridge arm modulates the output voltage signal u. rac During the positive half-cycle, it operates in a switching mode between "0" and "+1" states, with the duration varying according to a sinusoidal pattern; the three-level inverter bridge arm modulates the output voltage signal u. rac During the negative half-cycle, the operating mode, which continuously switches between "0" and "-1" states, also varies in duration according to a sinusoidal law. Taking the midpoint O of the DC bus unit as a reference point, the average switching cycle value of the voltage at the midpoint B of the three-level inverter bridge arm is... BO >For: (1) In the formula, M is the modulation ratio, and U dc ω is the average value of the DC bus unit terminal voltage, and ω is the output terminal voltage modulation signal u. rac angular frequency; The boost bridge arm continuously switches between "-1" and "+1" states during operation, with a duty cycle D=0.5. When the boost bridge arm is in the "-1" state, i.e., the input inductor L... in Start charging, input inductor current i Lin Linear increase, duration 0.5T s1 T s1 During the switching cycle of the boost bridge arm, the following occurs: (2) In the formula, U pv L is the average value of the input voltage, and L is the input inductance. in The inductance value.
[0024] When the boost bridge arm just switches to the "+1" state, the input inductor L in Discharge begins, and the voltage across its terminals is U. dc -U pv until the input inductor L in The current is 0, and the duration of this period is dT. s1 ; (3) Where d is the input inductance L in The equivalent duty cycle when the current is not zero, T s1 This refers to the switching cycle of the boost bridge arm.
[0025] During this period: (4) In the formula, U dc This represents the average value of the DC bus unit terminal voltage. As can be seen, in this operating mode, the boost ratio from the DC bus unit to the input is the same as that of a traditional DCM-Boost converter, which is: (5) In the formula, P o For the output power, f s1 D is the switching frequency of the boost bridge arm, and D is the duty cycle of the lower switch S2.
[0026] According to formula (5), it can be seen that the boost capability of a single-bridge integrated three-level boost inverter is related to the duty cycle D of the lower switch S2 and the switching frequency f of the boost bridge arm. s1 related.
[0027] Theoretically, the switching frequency f of the boost bridge arm can be adjusted. s1 Alternatively, adjusting the duty cycle D of the lower switch S2 can achieve different output power P. o The terminal voltage of the DC bus unit below.
[0028] Method 1: Adjust the duty cycle D of the lower switch S2 to regulate the terminal voltage of the DC bus unit.
[0029] The switching frequency f of the fixed boost bridge arm s1 =20kHz, adjust the duty cycle D of the lower transistor S2, then the average switching cycle of the voltage from the midpoint of the boost bridge arm to the midpoint of the DC bus unit in the single-bridge integrated three-level boost inverter is... AO >For: (6) At this point, the average switching cycle value of the midpoint voltage between the three-level inverter bridge arm and the boost bridge arm is... BA >For: (7) In the formula, M is the modulation ratio, which can be seen to introduce DC bias.
[0030] Method 2: Adjust the switching frequency f of the boost bridge arm s1 Adjust the terminal voltage of the DC bus unit.
[0031] With the duty cycle D of the fixed lower transistor S2 being 0.5, the average value of the voltage across the boost bridge arm from the midpoint of the boost arm to the midpoint of the DC bus unit in the single-bridge integrated three-level boost inverter during the switching cycle is... AO >For: (8) At this time, the average switching cycle value of the midpoint voltage between the inverter arm and the boost arm is... BA >For: (9) As can be seen, it eliminates DC bias. Therefore, this utility model uses method two to adjust the terminal voltage of the DC bus unit.
[0032] Formula (10) gives Figure 1 The formula for determining the inductance value L of the input inductor in the single-bridge integrated three-level boost inverter shown is as follows: (10) In the formula, U dc P represents the average terminal voltage of the DC bus unit. o,max f represents the maximum output power. s1,min U is the minimum switching frequency of the boost bridge arm. pv This represents the average value of the input voltage.
[0033] Combining formulas (5) and (9), the gain of the output voltage can be obtained as follows: (11) In the formula, U om This represents the amplitude of the output voltage.
[0034] In a specific embodiment of this utility model, it is also provided that Figure 1 The control circuit of the single-bridge integrated three-level boost inverter shown is as follows: Figure 9 As shown, it includes: A DC bus voltage sensor, connected in parallel with the DC bus unit, is used to acquire the terminal voltage u of the DC bus unit. dc ; The output voltage sensor, and its output filter capacitor C f Parallel connection, used to acquire the voltage u at the output terminal. o ; An output current sensor, connected in series with the load of the single-bridge integrated three-level boost inverter, is used to collect the output current i. o ; The main control unit, connected to the DC bus voltage sensor, the output voltage sensor, and the output current sensor, is used to analyze the terminal voltage u of the acquired DC bus unit. dc Output voltage u o and the output current i o The signals are processed to obtain the drive signals for each switching transistor; A driving circuit, which is connected to the main control unit, is used to drive the switching transistors according to the driving signals of each switching transistor output by the main control unit.
[0035] In one embodiment of this utility model, Figure 9 The main control unit of the control circuit shown is as follows: Figure 10 As shown, it includes a boost bridge arm switch drive signal generation unit and a three-level inverter bridge arm switch drive signal generation unit.
[0036] The boost bridge arm switch drive signal generation unit includes a DC bus voltage error calculation module, a DC bus voltage controller module, a frequency limiting module, and a pulse frequency modulation module connected in sequence. The DC bus voltage error calculation module is used to calculate the terminal voltage u of the DC bus unit. dc Compared with the benchmark value u dc,ref The difference is calculated to obtain the DC bus voltage error signal e1; the DC bus voltage controller module is used to generate a DC bus voltage frequency modulation signal c1 based on the received DC bus voltage error signal e1; the frequency limiting module is used to perform upper and lower limiting on the received DC bus voltage frequency modulation signal c1 to obtain a frequency signal f1; the pulse frequency modulation module is used to generate drive signals for all switching transistors of the boost bridge arm based on the received frequency signal f1.
[0037] The three-level inverter bridge arm switch drive signal generation unit includes, in sequence, an output voltage error calculation module, an output voltage controller module, an output current error calculation module, a proportional-integral controller module, an output voltage limiting module, and a pulse width modulation module; the output voltage error calculation module is used to calculate the voltage u. o With the output voltage reference value u o,ref The output voltage error signal e2 is obtained by subtracting the received output voltage error signal e2; the output voltage controller module is used to generate an output voltage control signal c2 based on the received output voltage error signal e2; the output current error calculation module is used to calculate the output voltage control signal c2 and the output current i o The output current error signal e3 is obtained by subtracting the received signal e3 from the output current error signal; the proportional-integral controller module is used to generate an output voltage control signal c3 based on the received output current error signal e3; the output voltage limiting module is used to limit the output voltage control signal c3 at the upper and lower limits to obtain an output voltage modulation signal u. rac The pulse width modulation module is used to modulate the received output voltage signal u. rac This generates drive signals for all the switching transistors of the three-level inverter bridge arm.
[0038] The pulse frequency modulation module includes a carrier generation module and a boost bridge arm drive generation module connected in sequence: the carrier generation module is used to generate a first bipolar triangular carrier signal u of the corresponding frequency according to the received frequency signal f1. c1 The boost bridge arm drive generation module is used to generate a DC modulation signal u with a value of zero. rdc With the first bipolar triangular carrier signal u c1 The comparison generates complementary drive signals for the upper switch S1 and the lower switch S2, with a constant duty cycle of 0.5.
[0039] To verify the feasibility of the photovoltaic inverter and its control method proposed in this invention, a Simulink simulation model was built for principle verification.
[0040] The design specifications of the converter proposed in this utility model are: the switching frequency f of the three-level inverter bridge arm. s2 =20kHz, minimum switching frequency f of the boost bridge arm s1,min =20kHz, input voltage U pv =100V, average terminal voltage U of DC bus unit dc =400V, maximum output power P o,max =500W, the amplitude of the output voltage U om =156V (110V RMS), input inductance L = 166.7μH. First DC bus capacitor C dc1Second DC bus capacitor C dc1 The capacitance value of each capacitor is 650μF, and the output filter capacitor C... f The capacitance is 6.9μF, and the output filter inductor L f The inductance is 3.6mH, and the input capacitance is C. in The capacitance is 44μF.
[0041] Figure 11 , Figure 12 When using the given inverter and its control circuit, the input voltage U pv The average value is 100V, and the output power is in P o =500W and P o Under 250W operating conditions, the input inductor current i of this single-bridge integrated three-level boost inverter Lin The drive signal u of the lower switch S2 ge,s2 The waveform diagram verifies the driving signal u of the switching transistor S2 under different operating conditions. ge,s2 The feasibility of a control circuit and control method for stabilizing the terminal voltage of a DC bus unit by adjusting the frequency accordingly.
[0042] Figure 13 , Figure 14 The midpoint of the boost bridge arm is connected to the first DC bus capacitor C. dc1 With the second DC bus capacitor C dc2 Connection point potential difference u AO The midpoint of the three-level inverter bridge arm is connected to the first DC bus capacitor C. dc1 With the second DC bus capacitor C dc2 Connection point potential difference u BO The terminal voltage u of the DC bus unit dc The voltage u of the first DC bus capacitor cdc1 Second DC bus voltage u cdc2 The overall and detailed waveform diagrams verify the voltage u of the first DC bus capacitor when using this control circuit and control method. cdc1 With the second DC bus voltage u cdc2 It has a certain voltage equalization capability, and the capacitance C from the midpoint of its three-level inverter bridge arm to the first DC bus. dc1 With the second DC bus capacitor C dc2 Connection point voltage u BO The three-level characteristics.
[0043] Figure 15 The average voltage U at the input terminal is given. pv At 100V, the output power P o Switching from 250W to P o =500W DC bus unit terminal voltage u dc Output voltage uo Output current i o The waveform. Figure 16 The input voltage U is given. pv When the voltage is 100V, the output power is from P. o =500W switch to P o =250W DC bus unit terminal voltage u dc Output voltage u o Output current i o The waveform shows that the average value U of the input voltage is... pv =100V, output power P o When switching between 250W and 500W, the system can always maintain the average DC bus voltage U. dc =400V voltage regulation control and output voltage u o The proposed inverter was controlled to produce a 110V / 50Hz sinusoidal waveform, verifying its boost inverter function and the effectiveness of the proposed control circuit and method. These results demonstrate that the single-arm integrated three-level boost inverter and its control circuit and method proposed in this paper for building-integrated photovoltaic systems are feasible for achieving boost inverter operation.
[0044] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0045] The above description of the embodiments is only for the purpose of helping to understand the method and core idea of this utility model, and is not intended to limit it. It should be noted that those skilled in the art can make several improvements and modifications to this utility model without departing from the principle of this utility model, and these improvements and modifications also fall within the protection scope of this utility model.
Claims
1. A single-arm integrated three-level boost inverter for building-integrated photovoltaic systems, characterized in that, include: Input capacitor C in Input inductance L in Anti-reverse diode D1, DC bus unit, output filter inductor L f Output filter capacitor C f Boost bridge arm and three-level inverter bridge arm; The booster arm includes an upper switch S1 and a lower switch S2; The three-level inverter bridge arm includes an upper switch S3, a lower switch S6, a clamping switch S4, and a clamping switch S5 connected in reverse series with the clamping switch S4. The DC bus unit includes a first DC bus capacitor. C dc1 Second DC bus capacitor C dc2 ; Input capacitor C in The first terminal and the input inductor L in The first end is connected and serves as the positive terminal of the input. Input inductance L in The second terminal is connected to the anode of the anti-reverse diode D1; The cathode of the anti-reverse diode D1 is at the midpoint of the boost bridge arm, and the output filter capacitor. C f The first terminal is connected and serves as the negative terminal of the output. Output filter capacitor C f The second terminal is connected to the output filter inductor L f The first end is connected and serves as the positive terminal of the output. Output filter inductor L f The second end is connected to the midpoint of the three-level inverter bridge arm; The first end of the DC bus unit is connected to the collectors of the upper switching transistors S1 and S3, and the midpoint is connected to the collector of the clamping switching transistor S4. The second end is connected to the emitter of the lower switching transistors S2 and S6, and the input capacitor. C in The second end is connected to serve as the negative terminal of the input.
2. The single-bridge integrated three-level boost inverter according to claim 1, characterized in that, Input inductance L in inductance value L satisfy: In the formula, U dc This represents the average terminal voltage of the DC bus unit. U pv The average value of the input voltage. P o,max This represents the maximum power output. f s1,min This is the minimum switching frequency of the boost bridge arm.
3. The single-bridge integrated three-level boost inverter according to claim 1, characterized in that, Minimum switching frequency of the boost bridge arm f s1,min 20kHz, input inductance L in inductance value L It is 166.7 μH.
4. A control circuit for a single-bridge-arm integrated three-level boost inverter as described in claim 1, characterized in that, The control circuit includes: A DC bus voltage sensor, connected in parallel with the DC bus unit, is used to collect the terminal voltage of the DC bus unit. u dc ; The output voltage sensor, along with the output filter capacitor C f Parallel connection, used to collect the voltage at the output terminal. u o ; An output current sensor, connected in series with the load of the single-bridge integrated three-level boost inverter, is used to collect the output current. i o ; The main control unit, connected to the DC bus voltage sensor, the output voltage sensor, and the output current sensor, is used to analyze the terminal voltage of the acquired DC bus unit. u dc Output voltage u o and the current at the output terminal i o The signals are processed to obtain the drive signals for each switching transistor; A driving circuit, which is connected to the main control unit, is used to drive the switching transistors to turn on and off according to the driving signals of each switching transistor output by the main control unit.
5. The control circuit according to claim 4, characterized in that, The main control unit includes a boost bridge arm switch drive signal generation unit; The boost bridge arm switch drive signal generation unit includes a DC bus voltage error calculation module, a DC bus voltage controller module, a frequency limiting module, and a pulse frequency modulation module connected in sequence. The DC bus voltage error calculation module is used to calculate the terminal voltage of the DC bus unit. u dc Compared with the benchmark value u dc,ref The difference is calculated to obtain the DC bus voltage error signal. e 1; The DC bus voltage controller module is used to determine the DC bus voltage error signal received. e 1. Generate DC bus voltage frequency modulation signal c 1; The frequency limiting module is used to modulate the signal according to the received DC bus voltage frequency. c 1. Obtain the frequency signal by performing upper and lower limiting. f 1; The pulse frequency modulation module is used to adjust the received frequency signal. f 1. Generate drive signals for all switching transistors of the boost bridge arm.
6. The control circuit according to claim 4, characterized in that, The main control unit includes a three-level inverter bridge arm switch driving signal generation unit; The three-level inverter bridge arm switch drive signal generation unit includes, in sequence, an output voltage error calculation module, an output voltage controller module, an output current error calculation module, a proportional-integral controller module, an output voltage limiting module, and a pulse width modulation module: The output voltage error calculation module is used to calculate the voltage. u o With the output voltage reference value u o,ref The difference is calculated to obtain the output voltage error signal. e 2; The output voltage controller module is used to adjust the received output voltage error signal. e 2. Generate output voltage control signal c 2; The output current error calculation module is used to calculate the output voltage control signal. c 2 and output current i o The output current error signal is obtained by subtracting the signals from each other. e 3; The proportional-integral controller module is used to determine the output current error signal received. e 3. Generate output voltage control signal c 3; The output voltage limiting module is used to control the output voltage signal. c 3. Perform upper and lower limiting to obtain the output voltage modulation signal. u rac ; The pulse width modulation module is used to modulate the signal according to the received output voltage. u rac This generates drive signals for all the switching transistors of the three-level inverter bridge arm.
7. The control circuit of the single-bridge integrated three-level boost inverter according to claim 5, characterized in that, The pulse frequency modulation module includes a carrier generation module and a boost bridge arm drive generation module connected in sequence: The carrier generation module is used to generate a frequency signal based on the received frequency signal. f 1. Generate the first bipolar triangular carrier signal of the corresponding frequency. u c1 ; The boost bridge arm drive generation module is used to generate a DC modulation signal with a value of zero. u rdc With the first bipolar triangular carrier signal u c1 The comparison generates complementary drive signals for the upper switch S1 and the lower switch S2, with a constant duty cycle of 0.5.