A clock calibration circuit

Abstract

The application relates to a clock calibration circuit, belonging to the technical field of electronic circuits, which comprises a satellite signal receiving unit for receiving a satellite signal and generating a time reference signal according to the satellite signal; a voltage-controlled clock source unit comprising a clock signal output; and a master control unit connected with the satellite signal receiving unit and the voltage-controlled clock source unit respectively, for receiving the time reference signal and the clock signal, generating a voltage adjustment signal based on the deviation of the time reference signal and the clock signal, and adjusting the frequency of the clock signal. The application can improve the short-term accuracy and long-term stability of the clock signal, and reduce the circuit volume.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and in particular to a clock calibration circuit. Background Technology

[0002] Currently, high-precision clock signals play a crucial role in modern communication systems, precision measuring instruments, and data synchronization transmission. As the most fundamental and widely used frequency source, the stability of the crystal oscillator's output frequency directly affects the performance of the entire electronic system. However, ordinary crystal oscillators inevitably experience frequency drift due to factors such as changes in ambient temperature and their own aging, failing to meet the increasingly stringent requirements of high-precision applications.

[0003] To improve clock signal accuracy, two mainstream technical solutions are currently employed. The first is to use a superior crystal oscillator, such as a temperature-compensated crystal oscillator (TCXO) or an oven-controlled crystal oscillator (OCXO). TCXOs reduce frequency drift due to temperature variations through built-in temperature compensation circuits, but their long-term stability is still affected by component aging. OCXOs maintain the crystal at a constant temperature through an internal temperature-controlled chamber, significantly reducing temperature drift and providing excellent short-term stability, but they suffer from inherent drawbacks such as high power consumption, large size, and high cost. The second solution utilizes a higher-level external time reference, such as the high-precision timing signal provided by a Global Navigation Satellite System (GNSS), to continuously calibrate the local crystal oscillator's frequency. Existing GNSS-based calibration circuits mostly support only a single frequency band of satellite signal reception. When this frequency band is interfered with or blocked, the entire calibration system fails, resulting in poor reliability. Therefore, obtaining a clock source that combines excellent short-term accuracy with long-term stability is a pressing issue that needs to be addressed. Utility Model Content

[0004] This application provides a clock calibration circuit that can improve the short-term accuracy and long-term stability of clock signals while reducing circuit size.

[0005] A clock calibration circuit, comprising: A satellite signal receiving unit is used to receive satellite signals and generate a time reference signal based on the satellite signals. A voltage-controlled clock source unit includes a clock signal output. The main control unit is connected to the satellite signal receiving unit and the voltage-controlled clock source unit, respectively, and is used to receive the time reference signal and the clock signal, and generate a voltage adjustment signal based on the deviation between the time reference signal and the clock signal to adjust the frequency of the clock signal.

[0006] By adopting the above technical solution, a high-precision absolute time reference can be provided by generating a time reference signal through the satellite signal receiving unit; a local clock signal can be output through the voltage-controlled clock source unit to provide the operating frequency for the system; and a closed-loop control can be constructed by the main control unit generating a voltage adjustment signal based on the deviation between the two to compensate for the frequency drift of the local clock in real time, thereby significantly improving the long-term frequency stability of the clock signal.

[0007] Optionally, the satellite signal receiving unit includes at least an antenna interface J3, an antenna interface J5, an RF switch U25, an RF switch U26, and a signal combiner M1. The antenna interface J3 and the antenna interface J5 are used to receive satellite signals in the first frequency band and satellite signals in the second frequency band, respectively. The RF input terminal of the RF switch U25 is connected to the antenna interface J3, the RF output terminal of the RF switch U25 is connected to the first input terminal of the signal combiner M1, the RF input terminal of the RF switch U26 is connected to the antenna interface J5, and the RF output terminal of the RF switch U26 is connected to the second input terminal of the signal combiner M1. The selection control terminals of both radio frequency switch U25 and radio frequency switch U26 are connected to the main control unit to receive control signals issued by the main control unit and to receive satellite signals of the first frequency band and / or the second frequency band.

[0008] By adopting the above technical solution and setting up dual antenna interfaces to receive satellite signals from the first and second frequency bands, dual-frequency reception can be achieved to eliminate ionospheric errors, thereby improving the accuracy of the time reference signal. By controlling the RF switch through the main control unit, the operating mode can be flexibly selected, thereby enhancing the circuit's environmental adaptability and anti-interference capability.

[0009] Optionally, the satellite signal receiving unit further includes a low-noise amplifier U9 and a positioning module U4; The output terminal of the signal combiner M1 is connected to the input terminal of the low-noise amplifier U9, the output terminal of the low-noise amplifier U9 is connected to the radio frequency signal input terminal of the positioning module U4, and the time reference signal output terminal of the positioning module U4 outputs the time reference signal.

[0010] By adopting the above technical solution and setting a low-noise amplifier U9, the merged satellite signal can be amplified and the signal-to-noise ratio can be improved, thereby increasing the receiving sensitivity and ensuring that the positioning module can stably lock onto the satellite even under weak signal conditions, thus ensuring the continuity of the time reference signal.

[0011] Optionally, the data transmitting end of the main control unit is connected to the data receiving end of the positioning module U4, the data receiving end of the main control unit is connected to the data transmitting end of the positioning module U4, and the timing signal input end of the main control unit is connected to the time reference signal output end of the positioning module U4.

[0012] By adopting the above technical solution, bidirectional communication can be achieved through the data connection between the main control unit and the positioning module, enabling the main control unit to determine the validity of the time reference signal and thus avoid erroneous calibration. By connecting the time reference signal to the timing signal input terminal of the main control unit, high-precision frequency measurement can be performed using hardware, thereby ensuring the accuracy of deviation calculation.

[0013] Optionally, the voltage-controlled clock source unit includes at least a crystal oscillator U21, a crystal oscillator X1, and a clock selection switch U27; The signal output terminal of the crystal oscillator U21 is connected to the first signal input terminal of the clock selection switch U27, the signal output terminal of the crystal oscillator X1 is connected to the second signal input terminal of the clock selection switch U27, and the voltage control terminals of both the crystal oscillator U21 and the crystal oscillator X1 are connected to the voltage regulation output terminal of the main control unit to receive the voltage regulation signal. The selection control terminal of the clock selection switch U27 is connected to the main control unit to receive the selection signal issued by the main control unit and select the output of the crystal oscillator U21 or the crystal oscillator X1 as the clock signal.

[0014] By adopting the above technical solution, and by setting two crystal oscillators and having the main control unit control the clock selection switch, intelligent switching can be performed according to the system's operating stage, thereby optimizing startup time and power consumption performance. By connecting the same voltage regulation signal to the two oscillators, the control circuit can be simplified, enabling seamless calibration of any selected clock source.

[0015] Optionally, the clock calibration circuit further includes inductor L3, inductor L4, and resistor R44; One end of the inductor L3 is connected to the RF input terminal of the RF switch U25, and the other end of the inductor L3 is connected to the antenna interface J5. One end of the inductor L4 is connected to the connection point of the inductor L3 and the antenna interface J3, and the other end of the inductor L4 supplies power to the active antenna. The other RF input terminal of the RF switch U25 is grounded through the resistor R44.

[0016] By adopting the above technical solution and setting up a bias circuit consisting of inductors L3 and L4 and resistor R44, the DC power supply voltage can be fed to the external active antenna through the radio frequency coaxial cable, thereby enhancing the satellite signal reception capability and improving the system performance in areas with weak signals.

[0017] Optionally, the clock calibration circuit further includes inductor L5, inductor L6, and resistor R45; One end of the inductor L6 is connected to the RF input terminal of the RF switch U26, and the other end of the inductor L6 is connected to the antenna interface J5. One end of the inductor L5 is connected to the connection point of the inductor L3 and the antenna interface J5, and the other end of the inductor L5 supplies power to the active antenna. The other RF input terminal of the RF switch U26 is grounded through the resistor R45.

[0018] By adopting the above technical solution, and by setting inductors L5 and L6 and resistor R45 to form another independent bias circuit, a stable power supply can be provided to the second active antenna connected to antenna interface J5, thereby fully leveraging the performance advantages of the dual-antenna configuration and ensuring that both receiving links operate in the best condition.

[0019] Optionally, the crystal oscillator U21 is a voltage-controlled temperature-compensated crystal oscillator, and the crystal oscillator X1 is a voltage-controlled temperature-compensated crystal oscillator.

[0020] In summary, this application includes at least the following beneficial effects: 1. A time reference signal is generated by the satellite signal receiving unit, which can provide a high-precision absolute time reference; a local clock signal is output by the voltage-controlled clock source unit, which can provide the operating frequency for the system; and a voltage regulation signal is generated by the main control unit based on the deviation between the two for correction, which can build a closed-loop control, compensate for the frequency drift of the local clock in real time, and thus significantly improve the long-term frequency stability of the clock signal. Attached Figure Description

[0021] Figure 1 This is a structural block diagram of the clock calibration circuit according to an embodiment of this application; Figure 2 This is a schematic diagram of the circuit structure of the clock calibration circuit in an embodiment of this application; Figure 3 This is a schematic diagram of the circuit structure of the satellite signal receiving unit of the clock calibration circuit in an embodiment of this application; Figure 4 This is a schematic diagram of the circuit structure of the main control module of the clock calibration circuit in an embodiment of this application; Figure 5 This is a schematic diagram of the circuit structure of the voltage-controlled clock source unit of the clock calibration circuit in the embodiment of this application. Detailed Implementation

[0022] This application is in conjunction with the appendix Figure 1 -Appendix Figure 5 Let's take an example to explain in more detail.

[0023] This application discloses a clock calibration circuit, as one embodiment of which is shown in the attached diagram. Figure 1 As shown and attached Figure 2 As shown, it includes: a satellite signal receiving unit, used to receive satellite signals and generate a time reference signal based on the satellite signals; As attached Figure 3 As shown, in one embodiment of a satellite signal receiving unit, the satellite signal receiving unit includes at least an antenna interface J3, an antenna interface J5, an RF switch U25, an RF switch U26, and a signal combiner M1. The antenna interface J3 and antenna interface J5 are used to receive satellite signals in a first frequency band and a second frequency band, respectively. The RF input terminal of the RF switch U25 is connected to the antenna interface J3, the RF output terminal of the RF switch U25 is connected to the first input terminal of the signal combiner M1, the RF input terminal of the RF switch U26 is connected to the antenna interface J5, and the RF output terminal of the RF switch U26 is connected to the second input terminal of the signal combiner M1. The selection control terminals of both radio frequency switch U25 and radio frequency switch U26 are connected to the main control unit to receive control signals issued by the main control unit and to receive satellite signals of the first frequency band and / or the second frequency band.

[0024] In this embodiment, the function of this unit is to receive external satellite navigation signals such as GPS and BeiDou, and demodulate them to extract a high-precision time reference signal, typically a second pulse signal, unaffected by its own aging. The unit includes two antenna interfaces, J3 and J5, used to receive satellite signals from the first and second frequency bands, respectively. Various types of antenna interfaces can be used, such as ceramic antennas and helical antennas. For example, antenna interface J3 receives GPS L1 band signals, and antenna interface J5 receives BeiDou B1 band signals. The unit also includes two radio frequency (RF) switches, U25 and U26. The signal path of antenna interface J3 is connected to the input of RF switch U25, and the signal path of antenna interface J5 is connected to the input of RF switch U26. The selection control terminals of RF switches U25 and U26 are connected to the main control unit. The main control unit can issue control signals to select satellite signals from the first and / or second frequency bands according to preset logic or external commands. This allows the system to flexibly select the antenna path with better signal quality or automatically switch when a path fails, greatly improving system reliability.

[0025] To power the active antenna, see attached Figure 3 As shown, the clock calibration circuit also includes a bias circuit. The clock calibration circuit further includes inductors L3 and L4, resistors R44, L5, and L6, and resistor R45. One end of the inductor L3 is connected to the RF input terminal of the RF switch U25, and the other end of the inductor L3 is connected to the antenna interface J5. One end of the inductor L4 is connected to the connection point of the inductor L3 and the antenna interface J3, and the other end of the inductor L4 supplies power to the active antenna. The other RF input terminal of the RF switch U25 is grounded through the resistor R44. One end of the inductor L6 is connected to the RF input terminal of the RF switch U26, and the other end of the inductor L6 is connected to the antenna interface J5. One end of the inductor L5 is connected to the connection point of the inductor L3 and the antenna interface J5, and the other end of the inductor L5 supplies power to the active antenna. The other RF input terminal of the RF switch U26 is grounded through the resistor R45.

[0026] In this embodiment, inductors L3, L4, L5, and L6 serve to match impedance and transmit signals, while resistors R44 and R45 are used to achieve port impedance matching and prevent reflection of signals without load.

[0027] As attached Figure 3 As shown, as a further embodiment of the satellite signal receiving unit, the satellite signal receiving unit also includes a low-noise amplifier U9 and a positioning module U4; The output terminal of the signal combiner M1 is connected to the input terminal of the low-noise amplifier U9, the output terminal of the low-noise amplifier U9 is connected to the radio frequency signal input terminal of the positioning module U4, and the time reference signal output terminal of the positioning module U4 outputs the time reference signal.

[0028] In this embodiment, the outputs of RF switches U25 and U26 are connected to the two inputs of a signal combiner M1, which combines the selected satellite signals into a single path. The selected satellite RF signals are combined by the signal combiner M1 and then immediately sent to a low-noise amplifier U9. The purpose of the LNA is to compensate for cable and PCB trace losses between the antenna and the receiving module, and to improve the signal-to-noise ratio, thereby ensuring that the subsequent positioning module U4 can quickly and stably lock onto the satellite even under weak signal conditions. The positioning module U4 is the core of this unit. It is an integrated GNSS receiver module with L1+L5 dual-frequency reception capability, supporting BDS+GPS+Galileo satellite system joint positioning, and also supporting independent positioning by China's BeiDou-2 and BeiDou-3 systems. This module is responsible for down-converting, demodulating, and performing correlation operations on the input RF signals, ultimately outputting positioning, velocity measurement, and timing information. Among these, the most important output is the high-precision time reference signal output from its time reference signal output terminal, such as the 1PPS pin. This signal is strictly synchronized with Coordinated Universal Time (UTC), and its pulse leading edge exhibits extremely high long-term stability and accuracy. It receives satellite signals from different frequency bands via an antenna interface, selects them using an RF switch, combines them using a signal combiner, amplifies them using a low-noise amplifier, and finally generates a time reference signal using a positioning module. This allows for the use of multiple satellite systems and frequency bands to improve signal quality and accelerate clock discipline.

[0029] As attached Figure 4 As shown, as a further implementation of the main control unit, the data transmitting end of the main control unit is connected to the data receiving end of the positioning module U4, the data receiving end of the main control unit is connected to the data transmitting end of the positioning module U4, and the timing signal input end of the main control unit is connected to the time reference signal output end of the positioning module U4.

[0030] In this embodiment, the main control unit is a microcontroller module with integrated wireless communication capabilities, such as a single-chip microcomputer or an ARM microcontroller. Its data transmitting end is connected to the data receiving end of the positioning module U4, and its data receiving end is connected to the data transmitting end of the positioning module U4. Its timing signal input end is connected to the time reference signal output end of the positioning module U4. The main control unit receives the time reference signal and the clock signal, calculates the deviation between them, and then generates a voltage adjustment signal. Simultaneously, the main control unit can also control the selection of the RF switch and the clock selection switch. The main control unit can also utilize its wireless communication function to connect to a WIFI or BLE network to accelerate the first positioning time using ephemeris data, thereby shortening the clock discipline time and replacing traditional wired connections such as network cables / serial ports / USB.

[0031] As attached Figure 5As shown, as a further embodiment of the voltage-controlled clock source unit, the voltage-controlled clock source unit includes at least a crystal oscillator U21, a crystal oscillator X1, and a clock selection switch U27; wherein, the crystal oscillator U21 is a voltage-controlled temperature-compensated crystal oscillator, and the crystal oscillator X1 is a voltage-controlled temperature-compensated crystal oscillator; the signal output terminal of the crystal oscillator U21 is connected to the first signal input terminal of the clock selection switch U27, the signal output terminal of the crystal oscillator X1 is connected to the second signal input terminal of the clock selection switch U27, and the voltage control terminals of both the crystal oscillator U21 and the crystal oscillator X1 are connected to the voltage regulation output terminal of the main control unit to receive the voltage regulation signal; The selection control terminal of the clock selection switch U27 is connected to the main control unit to receive the selection signal issued by the main control unit and select the output of the crystal oscillator U21 or the crystal oscillator X1 as the clock signal.

[0032] In this embodiment, the unit includes two different types of voltage-controlled crystal oscillators: a temperature-controlled crystal oscillator U21 (OCXO) and a temperature-compensated crystal oscillator X1 (TCXO). The OCXO U21 has extremely high short-term stability and low phase noise, but consumes more power and has a longer warm-up time; the TCXO X1, on the other hand, has the advantages of low power consumption and fast start-up. The voltage control terminals of both are connected to the voltage regulation output terminal of the main control unit to receive the voltage regulation signal sent by the main control unit, thereby fine-tuning their output frequency. The signal output terminals of the two crystal oscillators, U21 and X1, are respectively connected to the two input terminals of the clock selection switch U27. The selection control terminal of the clock selection switch U27 is also connected to the main control unit. The main control unit can send a selection signal according to the system's operating mode, such as using the TCXO for fast output during cold start and switching after the OCXO stabilizes, to determine which oscillator's output is ultimately selected as the system's clock signal. The output of clock selection switch U27 is the high-precision calibrated clock signal that the entire clock calibration circuit ultimately provides to the outside world.

[0033] Specifically, after the system powers on, the main control unit first controls the voltage-controlled clock source unit to output an initial local clock. Simultaneously, the satellite signal receiving unit begins operation, capturing satellite signals and outputting a 1PPS time reference signal. Using the 1PPS signal as a reference, the main control unit precisely measures the number of pulses in the local clock signal during this period and compares it with the theoretical value to calculate the frequency deviation. Based on the magnitude and direction of the deviation, the main control unit adjusts its DAC output, generating a new voltage regulation signal applied to the voltage control terminal of the selected crystal oscillator U21 or X1 to correct its frequency. This process repeats continuously, forming a dynamic closed-loop phase-locked loop system, ultimately ensuring that the clock signal frequency is precisely tamed and locked to the satellite time reference, thus outputting a clock signal that combines low cost, high precision, and high long-term stability.

[0034] The implementation principle of this application embodiment is as follows: A satellite signal receiving unit receives satellite signals from multiple frequency bands and multiple satellite systems to generate an accurate time reference signal. A voltage-controlled clock source unit provides a clock signal, and the main control unit compares the deviation between the time reference signal and the clock signal to generate a voltage adjustment signal to adjust the clock signal frequency. A dual-band or single-band antenna can be switched to balance signal quality and anti-interference requirements. This overcomes the frequency drift problem caused by changes in the internal working environment of the voltage-controlled oven-controlled crystal oscillator (OCXO). Without significantly increasing cost and size, it utilizes satellite signals to improve the short-term and long-term accuracy of the clock signal, while accelerating the clock discipline time of the OCXO, improving frequency calibration efficiency, enhancing system response speed, and making it more suitable for mobile applications.

[0035] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A clock calibration circuit, characterized in that, include: A satellite signal receiving unit is used to receive satellite signals and generate a time reference signal based on the satellite signals. A voltage-controlled clock source unit includes a clock signal output. The main control unit is connected to the satellite signal receiving unit and the voltage-controlled clock source unit, respectively, and is used to receive the time reference signal and the clock signal, and generate a voltage adjustment signal based on the deviation between the time reference signal and the clock signal to adjust the frequency of the clock signal.

2. The clock calibration circuit according to claim 1, characterized in that: The satellite signal receiving unit includes at least an antenna interface J3, an antenna interface J5, an RF switch U25, an RF switch U26, and a signal combiner M1. The antenna interface J3 and the antenna interface J5 are used to receive satellite signals in the first frequency band and satellite signals in the second frequency band, respectively. The RF input terminal of the RF switch U25 is connected to the antenna interface J3, the RF output terminal of the RF switch U25 is connected to the first input terminal of the signal combiner M1, the RF input terminal of the RF switch U26 is connected to the antenna interface J5, and the RF output terminal of the RF switch U26 is connected to the second input terminal of the signal combiner M1. The selection control terminals of both radio frequency switch U25 and radio frequency switch U26 are connected to the main control unit to receive control signals issued by the main control unit and to receive satellite signals of the first frequency band and / or the second frequency band.

3. The clock calibration circuit according to claim 2, characterized in that: The satellite signal receiving unit also includes a low-noise amplifier U9 and a positioning module U4; The output terminal of the signal combiner M1 is connected to the input terminal of the low-noise amplifier U9, the output terminal of the low-noise amplifier U9 is connected to the radio frequency signal input terminal of the positioning module U4, and the time reference signal output terminal of the positioning module U4 outputs the time reference signal.

4. The clock calibration circuit according to claim 3, characterized in that: The data transmitting end of the main control unit is connected to the data receiving end of the positioning module U4, the data receiving end of the main control unit is connected to the data transmitting end of the positioning module U4, and the timing signal input end of the main control unit is connected to the time reference signal output end of the positioning module U4.

5. The clock calibration circuit according to claim 1, characterized in that: The voltage-controlled clock source unit includes at least a crystal oscillator U21, a crystal oscillator X1, and a clock selection switch U27; The signal output terminal of the crystal oscillator U21 is connected to the first signal input terminal of the clock selection switch U27, the signal output terminal of the crystal oscillator X1 is connected to the second signal input terminal of the clock selection switch U27, and the voltage control terminals of both the crystal oscillator U21 and the crystal oscillator X1 are connected to the voltage regulation output terminal of the main control unit to receive the voltage regulation signal. The selection control terminal of the clock selection switch U27 is connected to the main control unit to receive the selection signal issued by the main control unit and select the output of the crystal oscillator U21 or the crystal oscillator X1 as the clock signal.

6. The clock calibration circuit according to claim 2, characterized in that: The clock calibration circuit also includes inductor L3, inductor L4 and resistor R44; One end of the inductor L3 is connected to the RF input terminal of the RF switch U25, and the other end of the inductor L3 is connected to the antenna interface J5. One end of the inductor L4 is connected to the connection point of the inductor L3 and the antenna interface J3, and the other end of the inductor L4 supplies power to the active antenna. The other RF input terminal of the RF switch U25 is grounded through the resistor R44.

7. The clock calibration circuit according to claim 6, characterized in that: The clock calibration circuit also includes inductor L5, inductor L6 and resistor R45; One end of the inductor L6 is connected to the RF input terminal of the RF switch U26, and the other end of the inductor L6 is connected to the antenna interface J5. One end of the inductor L5 is connected to the connection point of the inductor L3 and the antenna interface J5, and the other end of the inductor L5 supplies power to the active antenna. The other RF input terminal of the RF switch U26 is grounded through the resistor R45.

8. The clock calibration circuit according to claim 5, characterized in that: The crystal oscillator U21 is a voltage-controlled temperature-compensated crystal oscillator, and the crystal oscillator X1 is a voltage-controlled temperature-compensated crystal oscillator.

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