A full duplex pit signal conditioning circuit

Abstract

The utility model relates to radio frequency identification technology field discloses a kind of full duplex PIT signal conditioning circuit, including RLC series resonance circuit, antenna fault detection circuit, signal amplification circuit, FDX-B signal conditioning circuit, FDX-A signal conditioning circuit, TROVAN signal conditioning circuit, full-bridge drive circuit, dead zone control circuit, clock generator circuit and microcontroller;After signal amplification circuit, independently set three parallel special conditioning circuit (FDX-B, FDX-A, TROVAN), allow the radio frequency signal from the same antenna to be synchronously and independently filtered, shaped and demodulated, microcontroller can receive three-way demodulated digital signal in parallel, and respectively decoding, in the scanning process of a device, can seamlessly identify target with different protocol labels, greatly expand the applicability and efficiency of device in complex application scenarios (such as simultaneously managing pets, assets and wild animals).

Description

Technical Field

[0001] This utility model relates to the field of radio frequency identification technology, specifically a full-duplex PIT signal conditioning circuit. Background Technology

[0002] Currently, the technology used in industries such as seasonal migration of fish species, livestock and pet management, IoT device management, and car anti-theft is for target tracking, statistics, and coding. It mostly adopts low-frequency passive RFID technology, namely PIT passive electronic tags.

[0003] Full-duplex PIT is currently the internationally accepted standard for electronic tag identification of fish. The advantages of full-duplex electronic tags include: fast scanning speed, low cost, simple structure, small size, and compliance with global standards, thus making them widely applicable.

[0004] Currently, there are several PIT full-duplex protocols, including FDX-A, FDX-B, and TROVAN. FDX-A and FDX-B are used in scenarios such as pet chip tracking and livestock management; TROVAN is used in scenarios such as industrial tracking, industrial asset management, wildlife research, and medical applications.

[0005] The current technology has the following problems: 1. Insufficient compatibility, only supports one type of full-duplex protocol; 2. Insufficient noise processing capability of the signal chain leads to weak signal recognition ability. Therefore, we need to propose a full-duplex PIT signal conditioning circuit. Utility Model Content

[0006] The purpose of this invention is to provide a full-duplex PIT signal conditioning circuit that can simultaneously identify three full-duplex PIT protocols, including FDX-A, FDX-B, and TROVAN, through a low-noise signal chain and parallel signal decomposition technology, in order to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, this utility model provides the following technical solution: a full-duplex PIT signal conditioning circuit, comprising an RLC series resonant circuit, an antenna fault detection circuit, a signal amplification circuit, an FDX-B signal conditioning circuit, an FDX-A signal conditioning circuit, a TROVAN signal conditioning circuit, a full-bridge drive circuit, a dead-time control circuit, a clock generator circuit, and a microcontroller. The antenna fault detection circuit, signal amplification circuit, and full-bridge drive circuit are all electrically connected to the RLC series resonant circuit. The FDX-B signal conditioning circuit, FDX-A signal conditioning circuit, and TROVAN signal conditioning circuit are all electrically connected to the signal amplification circuit and the microcontroller. The antenna fault detection circuit is electrically connected to the microcontroller. The dead-time control circuit is electrically connected to the full-bridge drive circuit, the clock generator circuit, and the microcontroller, respectively.

[0008] Preferably, the RLC series resonant circuit includes a resonant resistor R5, a resonant capacitor, and a resonant inductor L1 connected in series. The resonant capacitor includes capacitor group one, capacitor group two, and capacitor group three connected in parallel. Capacitor group two and capacitor group three are connected in series, and the series-connected capacitor group two and capacitor group three are connected in parallel across capacitor group one. Capacitor group one includes capacitors C6, C7, C8, and C9 connected in parallel. Capacitor group two includes capacitors C10, C12, and C15 connected in parallel. Capacitor group three includes capacitors C11, C13, and C16 connected in parallel. Diodes D1 and D2 are connected in parallel across the two ends of the resonant inductor L1.

[0009] Preferably, the full-bridge drive circuit includes chip T2, chip T6, resistor R3 connected to resonant inductor L1, MOSFET T1B and MOSFET T23A, MOSFET T5B and MOSFET T23B connected to resonant capacitor, one end of resistor R3 is connected to MOSFET Q1, and the base of MOSFET Q1 is connected to resistor R1 and resistor R2 respectively. The source of MOSFET T1B is connected to the source of MOSFET T23A. The gate of MOSFET T1B is connected to pin 5 of chip T2, and the gate of MOSFET T23A is connected to pin 7 of chip T2. The source of MOSFET T5B is connected to the source of MOSFET T23B. The gate of MOSFET T5B is connected to pin 5 of chip T6, and the gate of MOSFET T23B is connected to pin 7 of chip T6.

[0010] Preferably, the antenna fault detection circuit includes an amplifier U31. Pin 3 of the amplifier U31 is connected to resistors R97 and R98 connected in series, and resistor R100 and capacitor C88 connected in parallel. Pins 1 and 4 of the amplifier U31 are connected, and resistor R99 is connected to pin 1 of the amplifier U31. One end of resistor R99 is connected to capacitor C89 and resistor R101 connected in parallel.

[0011] Preferably, the signal amplification circuit includes an amplifier U30B, a capacitor C81 is connected to pin 6 of the amplifier U30B, and a resistor R96 and a capacitor C85 are connected in parallel between pins 6 and 7 of the amplifier U30B.

[0012] Preferably, the FDX-B signal conditioning circuit includes an amplifier U30C, an amplifier U30D, a hysteresis comparator U33, and a chip U32A connected in sequence. A resistor R92, a resistor R91, and a capacitor C80 are connected in series between pin 15 of the amplifier U30C and pin 7 of the amplifier U30B. A resistor R94 is connected between pin 14 of the amplifier U30C and pin 19 of the amplifier U30D. A resistor R105 and a capacitor C90 are connected in parallel between pin 20 of the amplifier U30D and pin 6 of the hysteresis comparator U33. A resistor R104 is connected between pin 1 of the hysteresis comparator U33 and pin 2 of the chip U32A.

[0013] Preferably, the FDX-A signal conditioning circuit includes amplifiers U34B, U34C, U34D, and U35C connected in sequence. A capacitor C100, a resistor R115, and a resistor R116 are connected in series between pin 7 of amplifier U34B and pin 15 of amplifier U34C. A resistor R117 and a resistor R118 are connected in series between pin 14 of amplifier U34C and pin 19 of amplifier U34D. A resistor R119 and a resistor R120 are connected in series between pin 20 of amplifier U34D and pin 15 of amplifier U35C.

[0014] Preferably, the TROVAN signal conditioning circuit includes amplifiers U36B, U36C, and U36D connected in series, a hysteresis comparator U39, and a chip U37 electrically connected to amplifier U36D. A capacitor C108, a resistor R123, and a resistor R124 are connected in series at pin 6 of amplifier U36B. A capacitor C109, a resistor R125, and a resistor R126 are connected in series between pin 7 of amplifier U36B and pin 15 of amplifier U36C. A resistor R127 and a resistor R128 are connected in series between pin 14 of amplifier U36C and pin 18 of amplifier U36D. A resistor R132 is connected to pin 1 of chip U37, and a resistor R133 is connected to pin 2 of chip U37. Both resistors R132 and R133 are connected to pin 19 of amplifier U36D. Pin 20 of amplifier U36D is connected to pin 4 of hysteresis comparator U39.

[0015] Preferably, the dead-time control circuit includes a D flip-flop U23B, an OR gate U22A, an OR gate U26C, an OR gate U21, an OR gate U22B, an OR gate U24D, and a NOT gate U28D, a NOT gate U27E, and a NOT gate U25F. Both OR gate circuits U22A and U26C are electrically connected to D flip-flop U23B. The NOT gate circuits U28D, U26C, U27E, U24D, and U25F are connected in sequence. Both OR gate circuits U22A and U22B are electrically connected. Both OR gate circuits U21 and U24D are electrically connected to OR gate circuit U22B.

[0016] Preferably, the clock generator circuit includes NOT gate U19B, NOT gate U19C, counter U18, and NOT gate U19A connected in sequence. A resistor R81 and a crystal oscillator Y2 are connected in parallel between pins 3 and 4 of NOT gate U19B. Capacitors C73 and C74 are connected to the two ends of crystal oscillator Y2, respectively. A capacitor C75 is connected between pin 4 of NOT gate U19B and pin 5 of NOT gate U19C. A resistor RF83 is connected between pin 6 of NOT gate U19C and pin 10 of counter U18. A resistor R79 is connected to pin 9 of counter U18. A resistor R80 is connected to pin 7 of counter U18. A resistor R84 is connected to pin 6 of counter U18. Resistors R79, R80, and R84 are all connected to pin 1 of NOT gate U19A.

[0017] Compared with the prior art, the beneficial effects of this utility model are: 1. This utility model sets up three parallel dedicated conditioning circuits (FDX-B, FDX-A, TROVAN) after the signal amplification circuit, which allows radio frequency signals from the same antenna to be filtered, shaped and demodulated synchronously and independently. The microcontroller can receive the three demodulated digital signals in parallel and decode them separately. During a single scan of a device, it can seamlessly identify targets with different protocol tags, which greatly expands the applicability and efficiency of the device in complex application scenarios (such as managing pets, assets and wildlife at the same time).

[0018] 2. Each parallel conditioning path of this invention adopts a multi-feedback active low-pass filter, which can provide a steeper roll-off characteristic and accurately filter out out-of-band interference and noise outside the respective protocol carrier frequency, thereby significantly improving the signal-to-noise ratio. Each conditioning path ends with a hysteresis comparator for waveform shaping, which can convert the filtered analog signal into a clean, jitter-free digital square wave, greatly reducing the risk of the microcontroller misjudging bits during decoding.

[0019] 3. The dead time control of this utility model is extremely precise and stable, and is not affected by microcontroller program crashes or interrupt delays. It fundamentally avoids the risk of "shoot-through" short circuits of the upper and lower bridge arm MOSFETs in the full-bridge circuit, and greatly improves the reliability and lifespan of the system.

[0020] 4. The antenna fault detection circuit of this utility model is linked with the microcontroller to form a closed-loop protection system. When the antenna has an open circuit or short circuit fault, the microcontroller can immediately stop the full bridge drive to prevent damage to the power devices. Attached Figure Description

[0021] Figure 1 This is a system block diagram of the present invention; Figure 2 This is a circuit diagram of the signal amplification circuit and the FDX-B signal conditioning circuit of this utility model; Figure 3 This is a circuit diagram of the FDX-A signal conditioning circuit of this utility model; Figure 4 This is a circuit diagram of the TROVAN signal conditioning circuit of this utility model; Figure 5 This is the circuit diagram of the RLC series resonant circuit of this utility model; Figure 6 This is a circuit diagram of the full-bridge drive circuit of this utility model; Figure 7 This is a circuit diagram of the dead-zone control circuit of this utility model; Figure 8 This is a circuit diagram of the clock generator circuit of this utility model.

[0022] In the diagram: 1. RLC series resonant circuit; 2. Antenna fault detection circuit; 3. Signal amplification circuit; 4. FDX-B signal conditioning circuit; 5. FDX-A signal conditioning circuit; 6. TROVAN signal conditioning circuit; 7. Full-bridge drive circuit; 8. Dead-time control circuit; 9. Clock generator circuit; 10. Microcontroller. Detailed Implementation

[0023] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0024] Please see Figure 1-8This utility model provides a technical solution: a full-duplex PIT signal conditioning circuit, including an RLC series resonant circuit 1, an antenna fault detection circuit 2, a signal amplification circuit 3, an FDX-B signal conditioning circuit 4, an FDX-A signal conditioning circuit 5, a TROVAN signal conditioning circuit 6, a full-bridge drive circuit 7, a dead-time control circuit 8, a clock generator circuit 9, and a microcontroller 10. The antenna fault detection circuit 2, signal amplification circuit 3, and full-bridge drive circuit 7 are all electrically connected to the RLC series resonant circuit 1. The FDX-B signal conditioning circuit 4, FDX-A signal conditioning circuit 5, and TROVAN signal conditioning circuit 6 are all electrically connected to the signal amplification circuit 3 and the microcontroller 10. The antenna fault detection circuit 2 is electrically connected to the microcontroller 10. The dead-time control circuit 8 is electrically connected to the full-bridge drive circuit 7, the clock generator circuit 9, and the microcontroller 10, respectively.

[0025] The RLC series resonant circuit 1 includes a resonant resistor R5, a resonant capacitor, and a resonant inductor L1 connected in series. The resonant capacitor includes capacitor group one, capacitor group two, and capacitor group three connected in parallel. Capacitor group two and capacitor group three are connected in series, and the series-connected capacitor group two and capacitor group three are connected in parallel across capacitor group one. Capacitor group one includes capacitors C6, C7, C8, and C9 connected in parallel. Capacitor group two includes capacitors C10, C12, and C15 connected in parallel. Capacitor group three includes capacitors C11, C13, and C16 connected in parallel. Diodes D1 and D2 are connected in parallel across the two ends of the resonant inductor L1.

[0026] The resonant capacitor and resonant resistor R5 are located in the internal circuit of the card reader, where the inductance of the identification antenna and the resonant capacitor determine the resonant frequency of the circuit.

[0027] The RLC series resonant circuit 1 also includes enameled wire for monitoring data from external PIT (Passive Integrated Transponder) tags. Based on design requirements and the magnitude of the operating current, enameled wire with a suitable cross-sectional area is selected for winding. The winding parameters are mainly the inductance of inductor L1 and the DC resistance of resonant resistor R5. Generally, the larger the inductance (the more turns wound), the higher the sensitivity of PIT identification, but the loss caused by DC resistance will also increase, so it is necessary to select an appropriate inductance.

[0028] Capacitors C6, C7, C8, and C9 can be selected via jumpers, and resonant resistor R5 is used to adjust the Q value of the RLC resonant circuit.

[0029] Because RLC series resonant circuits generate a lot of heat during long-term operation, this can be mitigated by using two large-area open-window copper sheets ( Figure 5The two shaded squares in the middle are used for heat dissipation to ensure stable circuit operation.

[0030] The full-bridge drive circuit 7 uses a full-bridge circuit composed of two sets of N-channel and P-channel power MOSFETs, and is driven by a full-bridge driver. The timing and dead-time control of the full-bridge operation are implemented by a dedicated logic circuit, namely the dead-time control circuit 8.

[0031] The full-bridge drive circuit 7 includes chip T2, chip T6, resistor R3 connected to resonant inductor L1, MOSFET T1B and MOSFET T23A, MOSFET T5B and MOSFET T23B connected to resonant capacitor, one end of resistor R3 is connected to MOSFET Q1, and the base of MOSFET Q1 is connected to resistor R1 and resistor R2 respectively. Chips T2 and T6 are full-bridge driver chips, and their control signals come from the dead-time control circuit 8.

[0032] The MOSFET Q1, resistor R1, and resistor R2 form an antenna energy discharge circuit, which is used to quickly discharge the energy in the RLC circuit when the antenna stops resonating.

[0033] The source of MOSFET T1B is connected to the source of MOSFET T23A. The gate of MOSFET T1B is connected to pin 5 of chip T2, and the gate of MOSFET T23A is connected to pin 7 of chip T2. The source of MOSFET T5B is connected to the source of MOSFET T23B. The gate of MOSFET T5B is connected to pin 5 of chip T6, and the gate of MOSFET T23B is connected to pin 7 of chip T6.

[0034] The antenna fault detection circuit 2 includes an amplifier U31. Pin 3 of the amplifier U31 is connected to resistors R97 and R98 connected in series, and resistor R100 and capacitor C88 connected in parallel. Pins 1 and 4 of the amplifier U31 are connected, and resistor R99 is connected to pin 1 of the amplifier U31. One end of resistor R99 is connected to capacitor C89 and resistor R101 connected in parallel.

[0035] Antenna fault detection circuit 2 monitors the operating status of the RLC series resonant circuit and reports it as diagnostic information. If the RLC series resonant circuit does not oscillate, the circuit connected to the sampling point of the RLC series resonant circuit will identify the circuit's operating status and feed the signal back to the microcontroller 10 to monitor the antenna for open circuits and short circuits. This is a system self-diagnostic function.

[0036] The input to antenna fault detection circuit 2 comes from the signal sampling point FDX-IN. After being divided by resistors R97, R98, and R100, the sampled signal is stepped down to the design value, buffered by a voltage follower, and then output to microcontroller 10. Three different outputs are generated when the antenna resonates, is open-circuited, or short-circuited.

[0037] The signal amplification circuit 3 includes an amplifier U30B. A capacitor C81 is connected to pin 6 of the amplifier U30B. A resistor R96 and a capacitor C85 are connected in parallel between pins 6 and 7 of the amplifier U30B.

[0038] The signal amplification circuit 3 is used to amplify the original modulated signal at the signal sampling point, so as to facilitate processing by the subsequent circuit.

[0039] The signal amplification circuit 3 amplifies the original modulated signal at the signal sampling point and simultaneously provides the output to the FDX-B signal conditioning circuit 4, the FDX-A signal conditioning circuit 5, and the TROVAN signal conditioning circuit 6.

[0040] The input of signal amplifier circuit 3 is AC coupled through capacitor C81, and the signal is amplified by an inverting proportional amplifier circuit composed of resistors R93 and R96 and amplifier U30B.

[0041] The FDX-B signal conditioning circuit 4 employs differential biphase coding and AM-PSK modulation with a carrier frequency of 134.2 kHz. The FDX-B signal conditioning circuit 4 includes a multi-stage active low-pass filter to filter out out-of-band interference and noise, improving the signal-to-noise ratio. Simultaneously, the filter removes the carrier signal while retaining the modulated signal. The filtered modulated signal is then converted into a digital signal by a waveform shaping circuit before being sent to the microcontroller 10 for decoding.

[0042] The FDX-B signal conditioning circuit 4 includes an amplifier U30C, an amplifier U30D, a hysteresis comparator U33, and a chip U32A connected in sequence. A resistor R92, a resistor R91, and a capacitor C80 are connected in series between pin 15 of the amplifier U30C and pin 7 of the amplifier U30B. A resistor R94 is connected between pin 14 of the amplifier U30C and pin 19 of the amplifier U30D. A resistor R105 and a capacitor C90 are connected in parallel between pin 20 of the amplifier U30D and pin 6 of the hysteresis comparator U33. A resistor R104 is connected between pin 1 of the hysteresis comparator U33 and pin 2 of the chip U32A.

[0043] The modulated signal after passing through signal amplification circuit 3 is then input to hysteresis comparator U33 after passing through a fourth-order multi-feedback low-pass filter composed of amplifier U30C, amplifier U30D and peripheral circuits. Differential encoding is generated from the NRZ signal by using the D flip-flop of the XOR gate of chip U32A, and finally input to microcontroller 10 for decoding.

[0044] The FDX-A signal conditioning circuit 5 employs differential biphase coding and AM-PSK modulation with a carrier frequency of 125kHz. After passing through the signal amplification circuit 3, one path of the original modulated signal is input to the FDX-A signal conditioning circuit 5. This circuit also includes a multi-stage active low-pass filter to filter out out-of-band interference and noise, improving the signal-to-noise ratio. Simultaneously, the filter removes the carrier signal, retaining the modulated signal. The filtered modulated signal is then converted into a digital signal by a waveform shaping circuit before being sent to the microcontroller 10 for decoding.

[0045] The FDX-A signal conditioning circuit 5 includes amplifiers U34B, U34C, U34D, and U35C connected in sequence. A capacitor C100, a resistor R115, and a resistor R116 are connected in series between pin 7 of amplifier U34B and pin 15 of amplifier U34C. A resistor R117 and a resistor R118 are connected in series between pin 14 of amplifier U34C and pin 19 of amplifier U34D. A resistor R119 and a resistor R120 are connected in series between pin 20 of amplifier U34D and pin 15 of amplifier U35C.

[0046] The modulated signal after passing through signal amplification circuit 3 is then input to hysteresis comparator U33 for induction after passing through an 8th-order multi-feedback low-pass filter composed of amplifiers U34B, U34C, U34D, and U35C, and finally input to microcontroller 10 for decoding.

[0047] The TROVAN signal conditioning circuit 6 employs PSK phase shift keying modulation and differential biphase coding, with a carrier frequency of 128kHz. After passing through the signal amplification circuit 3, one path of the original modulated signal is input to the TROVAN signal conditioning circuit 6. This circuit also includes multi-stage active low-pass filters to filter out out-of-band interference and noise, improving the signal-to-noise ratio. However, its first-stage active low-pass filter is shared with the FDX-A signal conditioning circuit. Simultaneously, the filter removes the carrier signal while retaining the modulated signal. The filtered modulated signal is then converted into a digital signal by a waveform shaping circuit before being sent to the microcontroller 10 for decoding.

[0048] The TROVAN signal conditioning circuit 6 includes amplifiers U36B, U36C, and U36D connected in series, a hysteresis comparator U39, and a chip U37 electrically connected to amplifier U36D. A capacitor C108, resistor R123, and resistor R124 are connected in series at pin 6 of amplifier U36B. A capacitor C109, resistor R125, and resistor R126 are connected in series between pin 7 of amplifier U36B and pin 15 of amplifier U36C. Resistors R127 and R128 are connected in series between pin 14 of amplifier U36C and pin 18 of amplifier U36D. Resistor R132 is connected to pin 1 of chip U37, and resistor R133 is connected to pin 2 of chip U37. Resistors R132 and R133 are both connected to pin 19 of amplifier U36D. Pin 20 of amplifier U36D is connected to pin 4 of hysteresis comparator U39.

[0049] The sampling point of the TROVAN signal comes from the output of the second-order active low-pass filter of the FDX-A signal conditioning circuit 5, and then passes through the fourth-order multi-feedback low-pass filter composed of amplifiers U36B and U36C, before entering the second-order active low-pass filter with configurable gain SK topology composed of amplifier U36D. Finally, it enters the hysteresis comparator U39 for shaping and is then input to the microcontroller 10 for decoding.

[0050] The FDX-A signal conditioning circuit 5, FDX-B signal conditioning circuit 4, and TROVAN signal conditioning circuit 6 are all load-modulated signals. Therefore, the original signal first goes through the diode detection circuit for envelope detection, then through the amplification, filtering, and shaping circuits to obtain the corresponding encoded signal. Finally, the microcontroller 10 decodes the three encoded signals to obtain the full-duplex electronic tag information.

[0051] Dead-time control circuit 8 uses a digital logic chip to implement hardware dead-time control. Its advantages include high timing accuracy and precise dead-time control, while not consuming microcontroller resources. Following the PIT protocol requirements, it uses the resonant frequency to drive the full-bridge driver in full-bridge drive circuit 7, causing the RLC circuit to resonate and simultaneously achieving dead-time control, reducing MOSFET losses.

[0052] The dead-time control circuit 8 includes a D flip-flop U23B, an OR gate U22A, an OR gate U26C, an OR gate U21, an OR gate U22B, an OR gate U24D, and a NOT gate U28D, a NOT gate U27E, and a NOT gate U25F. Both OR gate circuits U22A and U26C are electrically connected to D flip-flop U23B. The NOT gate circuits U28D, U26C, U27E, U24D, and U25F are connected in sequence. Both OR gate circuits U22A and U22B are electrically connected. Both OR gate circuits U21 and U24D are electrically connected to OR gate circuit U22B.

[0053] The microcontroller 10 enables or disables the dead-time control circuit 8 by setting the pins PIC-29-0 and PIC-32 high.

[0054] The clock generator circuit 9 is used to provide the operating frequency of the dead-time control circuit 8.

[0055] The clock generator circuit 9 includes NOT gate U19B, NOT gate U19C, counter U18, and NOT gate U19A connected in sequence. A resistor R81 and a crystal oscillator Y2 are connected in parallel between pins 3 and 4 of NOT gate U19B. Capacitors C73 and C74 are connected to the two ends of crystal oscillator Y2, respectively. A capacitor C75 is connected between pin 4 of NOT gate U19B and pin 5 of NOT gate U19C. A resistor RF83 is connected between pin 6 of NOT gate U19C and pin 10 of counter U18. A resistor R79 is connected to pin 9 of counter U18. A resistor R80 is connected to pin 7 of counter U18. A resistor R84 is connected to pin 6 of counter U18. Resistors R79, R80, and R84 are all connected to pin 1 of NOT gate U19A.

[0056] The NOT gate U19B, crystal oscillator Y2, capacitor C73, and capacitor C74 form a three-point oscillation circuit, which is then divided by the counter U18 to provide the clock frequency to the dead-time control circuit 8 and the FDX-B signal conditioning circuit 4.

[0057] The main function of the microcontroller 10 is: 1. Decode the digital signals output from FDX-B signal conditioning circuit 4, FDX-A signal conditioning circuit 5, and TROVAN signal conditioning circuit 6; 2. Control and configure the dead-time control circuit 8, such as starting and stopping the full-bridge operation; configure different resonant drive frequencies for different PIT protocols; 3. Monitor the output of the antenna fault detection circuit 2 to determine the antenna status. When the antenna experiences a short circuit or open circuit fault, the microcontroller 10 will first stop enabling the full-bridge drive circuit 7 and report the diagnostic information.

[0058] The microcontroller 10 can be a 32-bit microcontroller from the Cortex-M4 series or an FPGA controller. It primarily decodes the demodulated FDX-B, FDX-A, and TROVAN signals, with a full-duplex PIT bit rate of 4194 bits / s, which is sufficient for most microcontrollers.

[0059] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A full-duplex PIT signal conditioning circuit, characterized in that: It includes an RLC series resonant circuit (1), an antenna fault detection circuit (2), a signal amplification circuit (3), an FDX-B signal conditioning circuit (4), an FDX-A signal conditioning circuit (5), a TROVAN signal conditioning circuit (6), a full-bridge drive circuit (7), a dead-time control circuit (8), a clock generator circuit (9), and a microcontroller (10). The antenna fault detection circuit (2), signal amplification circuit (3), and full-bridge drive circuit (7) are all electrically connected to the RLC series resonant circuit (1). The FDX-B signal conditioning circuit (4), FDX-A signal conditioning circuit (5), and TROVAN signal conditioning circuit (6) are all electrically connected to the signal amplification circuit (3) and the microcontroller (10). The antenna fault detection circuit (2) is electrically connected to the microcontroller (10). The dead zone control circuit (8) is electrically connected to the full-bridge drive circuit (7), the clock generator circuit (9), and the microcontroller (10), respectively.

2. The full-duplex PIT signal conditioning circuit according to claim 1, characterized in that: The RLC series resonant circuit (1) includes a resonant resistor R5, a resonant capacitor, and a resonant inductor L1 connected in series. The resonant capacitor includes capacitor group one, capacitor group two, and capacitor group three connected in parallel. The capacitor group two and capacitor group three are connected in series, and the capacitor group two and capacitor group three connected in series are connected in parallel across the two ends of capacitor group one. The capacitor group one includes capacitors C6, C7, C8, and C9 connected in parallel. The capacitor group two includes capacitors C10, C12, and C15 connected in parallel. The capacitor group three includes capacitors C11, C13, and C16 connected in parallel. The two ends of the resonant inductor L1 are connected to diodes D1 and D2 connected in parallel.

3. The full-duplex PIT signal conditioning circuit according to claim 2, characterized in that: The full-bridge drive circuit (7) includes chip T2, chip T6, resistor R3 connected to resonant inductor L1, MOSFET T1B and MOSFET T23A, MOSFET T5B and MOSFET T23B connected to resonant capacitor. One end of resistor R3 is connected to MOSFET Q1, and the base of MOSFET Q1 is connected to resistor R1 and resistor R2 respectively. The source of MOSFET T1B is connected to the source of MOSFET T23A. The gate of MOSFET T1B is connected to pin 5 of chip T2, and the gate of MOSFET T23A is connected to pin 7 of chip T2. The source of MOSFET T5B is connected to the source of MOSFET T23B. The gate of MOSFET T5B is connected to pin 5 of chip T6, and the gate of MOSFET T23B is connected to pin 7 of chip T6.

4. The full-duplex PIT signal conditioning circuit according to claim 1, characterized in that: The antenna fault detection circuit (2) includes an amplifier U31. Pin 3 of the amplifier U31 is connected to resistors R97 and R98 in series and resistors R100 and capacitor C88 in parallel. Pins 1 and 4 of the amplifier U31 are connected, and a resistor R99 is connected to pin 1 of the amplifier U31. One end of the resistor R99 is connected to capacitor C89 and resistor R101 in parallel.

5. The full-duplex PIT signal conditioning circuit according to claim 1, characterized in that: The signal amplification circuit (3) includes an amplifier U30B, a capacitor C81 is connected to pin 6 of the amplifier U30B, and a resistor R96 and a capacitor C85 are connected in parallel between pin 6 and pin 7 of the amplifier U30B.

6. A full-duplex PIT signal conditioning circuit according to claim 5, characterized in that: The FDX-B signal conditioning circuit (4) includes amplifier U30C, amplifier U30D, hysteresis comparator U33, and chip U32A connected in sequence. Resistors R92, R91, and capacitor C80 are connected in series between pin 15 of amplifier U30C and pin 7 of amplifier U30B. Resistor R94 is connected between pin 14 of amplifier U30C and pin 19 of amplifier U30D. Resistor R105 and capacitor C90 are connected in parallel between pin 20 of amplifier U30D and pin 6 of hysteresis comparator U33. Resistor R104 is connected between pin 1 of hysteresis comparator U33 and pin 2 of chip U32A.

7. The full-duplex PIT signal conditioning circuit according to claim 1, characterized in that: The FDX-A signal conditioning circuit (5) includes amplifiers U34B, U34C, U34D, and U35C connected in sequence. A capacitor C100, a resistor R115, and a resistor R116 are connected in series between pin 7 of amplifier U34B and pin 15 of amplifier U34C. A resistor R117 and a resistor R118 are connected in series between pin 14 of amplifier U34C and pin 19 of amplifier U34D. A resistor R119 and a resistor R120 are connected in series between pin 20 of amplifier U34D and pin 15 of amplifier U35C.

8. The full-duplex PIT signal conditioning circuit according to claim 1, characterized in that: The TROVAN signal conditioning circuit (6) includes amplifiers U36B, U36C, and U36D connected in series, a hysteresis comparator U39, and a chip U37 electrically connected to amplifier U36D. A capacitor C108, a resistor R123, and a resistor R124 are connected in series at pin 6 of amplifier U36B. A capacitor C109, a resistor R125, and a resistor R126 are connected in series between pin 7 of amplifier U36B and pin 15 of amplifier U36C. A resistor R127 and a resistor R128 are connected in series between pin 14 of amplifier U36C and pin 18 of amplifier U36D. A resistor R132 is connected to pin 1 of chip U37. A resistor R133 is connected to pin 2 of chip U37. Both resistors R132 and R133 are connected to pin 19 of amplifier U36D. Pin 20 of amplifier U36D is connected to pin 4 of hysteresis comparator U39.

9. A full-duplex PIT signal conditioning circuit according to claim 1, characterized in that: The dead-time control circuit (8) includes a D flip-flop U23B, an OR gate U22A, an OR gate U26C, an OR gate U21, an OR gate U22B, an OR gate U24D, and a NOT gate U28D, a NOT gate U27E, and a NOT gate U25F. Both OR gate circuits U22A and U26C are electrically connected to D flip-flop U23B. The NOT gate circuits U28D, U26C, U27E, U24D, and U25F are connected in sequence. Both OR gate circuits U22A and U22B are electrically connected. Both OR gate circuits U21 and U24D are electrically connected to OR gate circuit U22B.

10. A full-duplex PIT signal conditioning circuit according to claim 1, characterized in that: The clock generator circuit (9) includes NOT gate circuit U19B, NOT gate circuit U19C, counter U18, and NOT gate circuit U19A connected in sequence. A resistor R81 and a crystal oscillator Y2 are connected in parallel between pins 3 and 4 of NOT gate circuit U19B. Capacitors C73 and C74 are connected to the two ends of crystal oscillator Y2 respectively. A capacitor C75 is connected between pin 4 of NOT gate circuit U19B and pin 5 of NOT gate circuit U19C. A resistor RF83 is connected between pin 6 of NOT gate circuit U19C and pin 10 of counter U18. A resistor R79 is connected to pin 9 of counter U18. A resistor R80 is connected to pin 7 of counter U18. A resistor R84 is connected to pin 6 of counter U18. Resistors R79, R80, and R84 are all connected to pin 1 of NOT gate circuit U19A.

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