A data compression processing circuit based on FPGA

Abstract

The utility model discloses a data compression processing circuit based on FPGA, and the circuit utilizes input valid indication signal that it receives to buffer input data, outputs current data and historical data through shift register group module, detects the repetitiveness of two continuous data through repeated detection module, and outputs repetitiveness detection result, utilizes input valid indication signal that it receives, repetitiveness detection result and overflow value selection signal dynamic update counting, and outputs count value, count overflow indication signal and masking control signal through saturation counter module, utilizes input valid indication signal that it receives, repetitiveness detection result, count overflow indication signal, masking control signal and data noise filter length selection signal and splices target data with count value as compression data package output through data assembly module, and gives output valid indication signal. The utility model realizes the real -time compression of repeated data through repeated detection - counting coding.

Description

Technical Field

[0001] This utility model relates to the field of digital logic circuit design technology, and in particular to a data compression processing circuit based on FPGA. Background Technology

[0002] In Industrial Internet of Things (IIoT) scenarios, sensors (such as temperature, pressure, and humidity sensors) typically collect data at a fixed frequency. When environmental parameters change slowly, the continuously reported values ​​often exhibit high repetition. Directly transmitting raw data streams containing a large number of repetitive values ​​would result in wasted bandwidth.

[0003] Traditional compression algorithms such as LZ77 / LZ4 and Huffman coding require complex state machines and a large amount of storage resources (such as BRAM), which consume too much resources on FPGAs. For example, LZ4 requires a hash dictionary and a sliding window, occupying more than 500 LUTs, which is difficult to meet the real-time requirements of low-end FPGAs.

[0004] Therefore, there is an urgent need for an FPGA-based real-time compression processing circuit for repetitive data. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by providing a data compression processing circuit based on FPGA. This invention employs a dynamic compression architecture of repeated detection-counting encoding, achieving real-time compression of single-cycle delays through real-time comparison with pipeline counting using a single comparator.

[0006] The objective of this invention is achieved through the following technical solution: a data compression processing circuit based on FPGA, comprising: The shift register group module is used to buffer input data, i.e., repetitive data input to the data compression processing circuit; the shift register group module includes a clock signal input terminal, a reset signal input terminal, an input valid indication signal input terminal, a set of data input terminals, a set of current data output terminals, and a set of historical data output terminals; A repetition detection module is used to detect the repetition of two consecutive input data outputs from the shift register group module. The repetition detection module includes a set of current data input terminals, a set of historical data input terminals, and a repetition detection result output terminal. The current data input terminals are connected to the current data output terminal, and the historical data input terminals are connected to the historical data output terminal. A saturation counter module is used to dynamically update the count value based on the repeatability detection result output by the repeatability detection module. The saturation counter module includes a first input terminal, a second input terminal, a repeatability detection result input terminal, a third input terminal, an overflow value selection input terminal, a set of count value output terminals, a count overflow indication signal output terminal, and a masking control signal output terminal. The data assembly module is used to concatenate the historical data output by the shift register group module with the count value into a compressed data packet and output it, and provide an output validity indication signal to achieve real-time compression processing of repetitive data. The data assembly module includes a fourth input terminal, a fifth input terminal, a set of sixth input terminals, a set of count value input terminals, a count overflow indication signal input terminal, a masking control signal input terminal, a data noise filtering length selection input terminal, a seventh input terminal, an eighth input terminal, a set of data output terminals, and an output validity indication signal output terminal. Among them, the count value input terminal is connected to the count value output terminal, the count overflow indication signal input terminal is connected to the saturation count overflow indication signal output terminal, and the masking control signal input terminal is connected to the masking control signal output terminal. Specifically, the clock signal input terminal is connected to the first and fourth input terminals, the reset signal input terminal is connected to the second and fifth input terminals, the input valid indication signal input terminal is connected to the third and eighth input terminals, the historical data output terminal is connected to the historical data input terminal and the sixth input terminal, and the repeatability test result output terminal is connected to the repeatability test result input terminal and the seventh input terminal.

[0007] Furthermore, the shift register group module includes two 2-to-1 selectors, a primary register, and a secondary register. One data input terminal of the first 2-to-1 selector is the data input terminal of the shift register group module. The other data input terminal of the first 2-to-1 selector is connected to the output terminal of the primary register to serve as the current data output terminal of the shift register group module. The selection control signal input terminals of the two 2-to-1 selectors are connected to serve as the input valid indication signal input terminal of the shift register group module. The output terminal of the first 2-to-1 selector is connected to the data input terminal of the primary register. The clock input terminals of the primary register and the secondary register are connected to serve as the clock signal input terminal of the shift register group module. The reset control terminals of the primary register and the secondary register are connected to serve as the reset signal input terminal of the shift register group module. The output terminal of the primary register is connected to one data input terminal of the second 2-to-1 selector. The other data input terminal of the second 2-to-1 selector is connected to the output terminal of the secondary register to serve as the historical data output terminal of the shift register group module. The output terminal of the second 2-to-1 selector is connected to the data input terminal of the secondary register.

[0008] Furthermore, the duplicate detection module includes an equal value comparator, the two input terminals of which are the current data input terminal and the historical data input terminal of the duplicate detection module, respectively, and the output terminal of the equal value comparator is the duplicate detection result output terminal of the duplicate detection module.

[0009] Furthermore, the saturation counter module specifically includes: The clock input terminals of the first D flip-flop, the second D flip-flop, and the register are connected as the first input terminal of the saturation counter module. The reset control terminal of the first D flip-flop, the second D flip-flop, and the register is connected as the second input terminal of the saturation counter module. The selection control signal input terminals of the first 2-to-1 selector, the third 2-to-1 selector, and the sixth 2-to-1 selector are connected as the third input terminal of the saturation counter module. The selection control signal input terminal of the seventh 2-to-1 selector is used as the overflow value selection input terminal of the saturation counter module. One data input terminal of the first 2-to-1 selector is connected to a high level. The other data input terminal of the first 2-to-1 selector is connected to one data input terminal of the second 2-to-1 selector, the output terminal of the first D flip-flop, one data input terminal of the third 2-to-1 selector, and one data input terminal of the first AND gate. The output terminal of the first 2-to-1 selector is connected to the other data input terminal of the second 2-to-1 selector. The output terminal of the second 2-to-1 selector is connected to the data input terminal of the first D flip-flop. The selection control signal input terminal of the second 2-to-1 selector is connected to the selection control signal input terminal of the fourth 2-to-1 selector and the output terminal of the first AND gate. The other data input terminal of the third 2-to-1 selector is connected to the other data input terminal of the first AND gate, one data input terminal of the fourth 2-to-1 selector, the output terminal of the second D flip-flop, and one data input terminal of the second AND gate as the masking control signal output terminal of the saturation counter module. The output terminal of the third 2-to-1 selector is connected to the other data input terminal of the fourth 2-to-1 selector. The output terminal of the fourth 2-to-1 selector is connected to the data input terminal of the second D flip-flop. The other data input of the second AND gate is the repeatability detection result input of the saturation counter module. The NOT input of the second AND gate is connected to the output of the seventh 2-to-1 selector as the count overflow indication signal output of the saturation counter module. The output of the second AND gate is connected to the selection control signal input of the fifth 2-to-1 selector. One data input of the adder is connected to a high level. The other data input of the adder is connected to a data input of the sixth 2-to-1 selector, the output of the register, an input of the first equivalent comparator, and an input of the second equivalent comparator as the count value output of the saturation counter module. The output of the adder is connected to the fifth 2-to-1 selector... One data input terminal of the first 2-to-1 selector is connected to the other data input terminal of the second 2-to-1 selector, which receives the signal corresponding to the default value of the counter being 1. The output terminal of the fifth 2-to-1 selector is connected to the other data input terminal of the sixth 2-to-1 selector, and the output terminal of the sixth 2-to-1 selector is connected to the data input terminal of the register. The other input terminal of the first equal-value comparator receives the maximum count value signal corresponding to the effective bit width of the counter being 4 bits, and the other input terminal of the second equal-value comparator receives the maximum count value signal corresponding to the effective bit width of the counter being 8 bits. The output terminals of the first and second equal-value comparators are connected one-to-one to the two data input terminals of the seventh 2-to-1 selector.

[0010] Furthermore, the data assembly module specifically includes: The clock inputs of D flip-flops 1 and 2 are connected as the fourth input of the data assembly module. The reset control terminals of D flip-flops 1 and 2 are connected as the fifth input of the data assembly module. One data input of AND gate 1 is connected to the data input of D flip-flop 2 as the eighth input of the data assembly module. The NOT input of AND gate 1 is connected to one data input of AND gate 2 and the NOT input of AND gate 3 as the seventh input of the data assembly module. The other data input of AND gate 2 is connected to one data input of OR gate 2 as the count overflow indicator signal input of the data assembly module. The output of AND gate 1 is connected to the selection control signal input of 2-to-1 selector 1. One data input of 2-to-1 selector 1 is grounded. The other data input of 2-to-1 selector 1 is connected to the output of D flip-flop 1 and one data input of OR gate 1. The output of 2-to-1 selector 1 is connected to one data input of 2-to-1 selector 2. The other data input of the selector is connected to a high level. The output of the second 2-to-1 selector is connected to the data input of the first D flip-flop. One input of the larger comparator is used as the data noise filtering length selection input of the data assembly module. The other input of the larger comparator is connected to one input of the bit splicing as the count value input of the data assembly module. The output of the larger comparator is connected to the other data input of the first OR gate. The output of the first OR gate is connected to one data input of the third AND gate. The output of the third AND gate is connected to the other data input of the second OR gate. The output of the second OR gate and the output of the second D flip-flop are respectively connected to two data inputs of the fourth AND gate. The third data input of the fourth AND gate is used as the masking control signal input of the data assembly module. The output of the fourth AND gate is used as the output valid indication signal output of the data assembly module. The other input of the bit splicing is used as the sixth input of the data assembly module. The output of the bit splicing is used as the data output of the data assembly module.

[0011] Furthermore, the data assembly module also includes a control pulse input terminal for receiving control pulse signals.

[0012] Furthermore, the data assembly module also includes a third OR gate, the output of the fourth AND gate is connected to one data input of the third OR gate, the other data input of the third OR gate serves as the control pulse input of the data assembly module, and the output of the third OR gate serves as the output valid indication signal output of the data assembly module.

[0013] Compared with the prior art, the beneficial effects of this utility model are: (1) Resource efficiency: This utility model uses a shift register + comparator to replace the traditional dictionary structure, which effectively reduces the storage resource occupation. It does not require BRAM (Block RAM) and relies entirely on registers and combinational logic. It can reduce logic resource consumption by 85% compared with the traditional solution, and is suitable for low-end FPGAs (such as Cyclone IV).

[0014] (2) Strong real-time performance: The compression processing circuit of this utility model has strong real-time performance, single-cycle processing delay, and supports 120MHz~130MHz data stream, which meets the real-time needs of industry.

[0015] (3) Flexible and adaptable: This utility model can support dynamic adjustment of the data noise filtering length and the effective bit width of the counter, adapting to diverse sensor data modes.

[0016] (4) Reduced power consumption: The compression processing circuit designed in this utility model is very simple, small in scale, and low in resource consumption, which can effectively reduce the overall power consumption and can be powered by battery.

[0017] (5) Applicable scenarios: In this utility model, if the input data bit width of the implemented circuit is 8 bits and the output data bit width is 16 bits, the consumption of logic resources is relatively small, requiring only 40 logic elements and 28 registers. It is suitable for application scenarios with high data repeatability (such as temperature and humidity sensors), and is especially suitable for applications with data redundancy > 50% and repetition length ≥ 3. This utility model can reduce the average repetition length and minimum redundancy requirements by expanding the bit width of the input and output data without changing the circuit structure. For example, when the input bit width is 32 bits and the average repetition length is 2, the corresponding minimum redundancy requirement drops to 40%; when the average repetition length is 5, the corresponding minimum redundancy requirement drops to 25%. This utility model can effectively reduce the compression ratio, making the circuit scheme more universal, thereby expanding the application scenarios of the circuit. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the FPGA-based data compression processing circuit of this utility model; Figure 2 This is a schematic diagram of the internal circuit logic of the shift register group module of this utility model; Figure 3 This is a schematic diagram of the internal circuit logic of the repeat detection module of this utility model; Figure 4 This is a schematic diagram of the internal circuit logic of the saturation counter module of this utility model; Figure 5This is a schematic diagram of the internal circuit logic of the data assembly module of this utility model; Figure 6 This is a timing waveform diagram of the present invention when the data noise filtering length is 0, the maximum count value is 15 (decimal), and the data sequence is input intermittently one by one; Figure 7 This is a timing waveform diagram of the data noise filtering length of 2, the maximum count value of 255 (decimal), and the continuous input of the data sequence in this utility model; Figure 8 This is a timing waveform diagram of the data noise filtering length being 0, the maximum count value being 15 (decimal), and the data sequence being intermittently and randomly continuously input. Figure 9 This is a screenshot of the FPGA synthesis process summary information in this utility model; Figure 10 This is a screenshot of the Fmax report of the static timing analysis after FPGA synthesis in the Slow Corner Model of this utility model. Detailed Implementation

[0019] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0020] The present invention will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementation methods can be combined with each other.

[0021] like Figure 1As shown, the FPGA-based data compression processing circuit of this invention consists of four sub-modules: a shift register group module, a repetition detection module, a saturation counter module, and a data assembly module. The shift register group module buffers the input data, i.e., the repetitive data input to the data compression processing circuit. The repetition detection module detects the repetition of two consecutive input data points output by the shift register group module. The saturation counter module dynamically updates the count value based on the repetition detection result output by the repetition detection module. The data assembly module concatenates the historical data output by the shift register group module with the count value to form a compressed data packet and outputs it, providing a valid output indication signal to achieve real-time compression processing of repetitive data. Traditional FPGA compression may use lookup tables or block RAM (BRAM), but the data compression processing circuit of this invention avoids using these logic resources, achieving a lightweight implementation. It can handle repetitive data, compressing and outputting repetitive data. The repetitive data input to the data compression processing circuit includes repetitive data such as industrial steady-state data (e.g., constant temperature workshop), equipment vibration monitoring data (intermittent repetition), periodic sensor data (e.g., liquid level monitoring), or steady-state signal data from high-frequency sampling (e.g., pressure).

[0022] like Figure 1 As shown, the shift register group module includes a clock signal input terminal for receiving the clock signal clk, a reset signal input terminal for receiving the reset signal rst_n, an input valid indicator signal input terminal for receiving the input valid indicator signal data_valid, a set of data input terminals for receiving input data data_in[7:0], a set of current data output terminals for outputting the stored current data new_data[7:0], and a set of historical data output terminals for outputting the stored previous historical data old_data[7:0].

[0023] The repeatability detection module includes a set of current data input terminals for receiving the current data new_data[7:0] output from the shift register group module, a set of historical data input terminals for receiving the historical data old_data[7:0] output from the shift register group module, and a repeatability detection result output terminal for outputting the repeatability detection result is_repeat. The set of current data input terminals of the repeatability detection module is connected one-to-one with the set of current data output terminals of the shift register group module, and the set of historical data input terminals of the repeatability detection module is connected one-to-one with the set of historical data output terminals of the shift register group module.

[0024] The saturation counter module includes a first input terminal for receiving the clock signal clk, a second input terminal for receiving the reset signal rst_n, a repeatability detection result input terminal for receiving the repeatability detection result is_repeat output by the repeatability detection module, a third input terminal for receiving the input validity indication signal data_valid, an overflow value selection input terminal for receiving the overflow value selection signal mod_sel, a set of count value output terminals for outputting the count value counter[7:0], a count overflow indication signal output terminal for outputting the count overflow indication signal overflow, and a masking control signal output terminal for outputting the masking control signal mask. The first input terminal of the saturation counter module is connected to the clock signal input terminal of the shift register group module, the second input terminal of the saturation counter module is connected to the reset signal input terminal of the shift register group module, the repeatability detection result input terminal of the saturation counter module is connected to the repeatability detection result output terminal of the repeatability detection module, and the third input terminal of the saturation counter module is connected to the input validity indication signal input terminal of the shift register group module.

[0025] The data assembly module includes a fourth input terminal for receiving the clock signal clk, a fifth input terminal for receiving the reset signal rst_n, a set of sixth input terminals for receiving the historical data old_data[7:0] output by the shift register group module, a set of count value input terminals for receiving the count value counter[7:0] output by the saturation counter module, a count overflow indicator signal input terminal for receiving the count overflow indicator signal overflow output by the saturation counter module, a masking control signal input terminal for receiving the masking control signal mask output by the saturation counter module, a data noise filtering length selection input terminal for receiving the data noise filtering length selection signal flt_cfg, a seventh input terminal for receiving the repeatability detection result is_repeat output by the repeatability detection module, an eighth input terminal for receiving the input validity indicator signal data_valid, a set of data output terminals for outputting compressed output data compressed_data, and an output validity indicator signal output terminal for outputting the output validity indicator signal output_valid. The fourth input terminal of the data assembly module is connected to the clock signal input terminal of the shift register group module. The fifth input terminal of the data assembly module is connected to the reset signal input terminal of the shift register group module. A set of sixth input terminals of the data assembly module is connected one-to-one with a set of historical data output terminals of the shift register group module and a set of historical data input terminals of the repeat detection module. A set of count value input terminals of the data assembly module is connected one-to-one with a set of count value output terminals of the saturation counter module. The count overflow indication signal input terminal of the data assembly module is connected to the count overflow indication signal output terminal of the saturation counter module. The masking control signal input terminal of the data assembly module is connected to the masking control signal output terminal of the saturation counter module. The seventh input terminal of the data assembly module is connected to the repeatability detection result output terminal of the repeatability detection module and the repeatability detection result input terminal of the saturation counter module. The eighth input terminal of the data assembly module is connected to the input validity indication signal input terminal of the shift register group module.

[0026] Specifically, the clock signal input terminal of the shift register group module is connected to the first input terminal of the saturated counter module and the fourth input terminal of the data assembly module to receive the clock signal clk; the reset signal input terminal of the shift register group module is connected to the second input terminal of the saturated counter module and the fifth input terminal of the data assembly module to receive the reset signal rst_n; the input valid indicator signal input terminal of the shift register group module is connected to the third input terminal of the saturated counter module and the eighth input terminal of the data assembly module to receive the input valid indicator signal data_valid; a set of historical data output terminals of the shift register group module is connected one-to-one with a set of historical data input terminals of the repeat detection module and a set of sixth input terminals of the data assembly module; and the repeatability detection result output terminal of the repeatability detection module is connected to the repeatability detection result input terminal of the saturated counter module and the seventh input terminal of the data assembly module.

[0027] In this embodiment, as Figure 2 As shown, the shift register group module includes two 2-to-1 multiplexers (MUX), a primary register, and a secondary register. One data input terminal of the first 2-to-1 MUX serves as the data input terminal of the shift register group module to receive input data data_in[7:0]. The other data input terminal of the first 2-to-1 MUX is connected to the output terminal of the primary register and serves as the current data output terminal of the shift register group module to output the current data new_data[7:0]. The selection control signal input terminals of the two 2-to-1 MUX are connected as the input valid indicator signal input terminal of the shift register group module to receive the input valid indicator signal data_valid. The output terminal of the first 2-to-1 MUX is connected to the data input terminal of the primary register. The clock input terminals (rising edge triggered) of the first-level register and the second-level register are connected as the clock signal input terminals of the shift register group module to receive the clock signal clk. The reset control terminals of the first-level register and the second-level register are connected as the reset signal input terminals of the shift register group module to receive the reset signal rst_n. The output terminal of the first-level register is connected to one data input terminal of the second 2-to-1 MUX. The other data input terminal of the second 2-to-1 MUX is connected to the output terminal of the second-level register as the historical data output terminal of the shift register group module to output the previous historical data old_data[7:0]. The output terminal of the second 2-to-1 MUX is connected to the data input terminal of the second-level register.

[0028] like Figure 2As shown, in the shift register group module, the first-level register is used to store the current data new_data[7:0], and the second-level register is used to store the previous historical data old_data[7:0]. Both the first-level and second-level registers are 8-bit wide registers composed of 8 D flip-flops (DFFs) connected in parallel. The specific logic process of the shift register group module includes: when the clk valid edge arrives, if data_valid is sampled as high, data_in[7:0] is shifted into the first-level register for latching; when the clk valid edge arrives, if data_valid is sampled as high, the current data new_data[7:0] stored in the first-level register is shifted into the second-level register for latching; when the clk valid edge arrives, if data_valid is sampled as low, the data stored in the first-level and second-level registers retains their original values ​​and is not updated; rstn is used to reset and initialize the first-level and second-level registers. The reset values ​​of the first-level and second-level registers can be arbitrary values, and they are not required to be all 00H or all FFH.

[0029] In this embodiment, as Figure 3 As shown, the repeat detection module is implemented using an equality comparator. It compares the two sets of data output from the shift register group module, namely the current data new_data[7:0] and the historical data old_data[7:0], for equality. If they are equal, the repeat detection result is_repeat is output as 1; otherwise, the repeat detection result is_repeat is output as 0. The circuit of the repeat detection module is a pure combinational logic circuit, using only one equality comparator for comparing whether the data are equal. The two inputs of the equality comparator serve as one set of current data inputs for the repeat detection module to receive the current data new_data[7:0] output from the shift register group module and one set of historical data inputs to receive the historical data old_data[7:0] output from the shift register group module. The output of the equality comparator serves as the repeat detection result output for the repeat detection module to output the repeat detection result is_repeat. If the repeatability detection result is_repeat is 1, it means that the current input data new_data[7:0] and the historical data old_data[7:0] are equal, that is, the two input data are repeated.

[0030] In this embodiment, the internal circuit of the saturation counter module is as follows: Figure 4As shown, it includes: a first D flip-flop (DFF), a second DFF, and the clock input (rising edge triggered) of the register connected together as the first input of the saturation counter module to receive the clock signal clk; a first DFF, a second DFF, and the reset control terminal of the register connected together as the second input of the saturation counter module to receive the reset signal rst_n; selection control signal inputs of a first 2-to-1 MUX, a third 2-to-1 MUX, and a sixth 2-to-1 MUX connected together as the third input of the saturation counter module to receive the input validity indication signal data_valid; and a selection control signal input of a seventh 2-to-1 MUX as the saturation counter module. The overflow value selection input is used to receive the overflow value selection signal mod_sel; one data input of the first 2-to-1 MUX is connected to a high level; the other data input of the first 2-to-1 MUX is connected to one data input of the second 2-to-1 MUX, the output of the first DFF, one data input of the third 2-to-1 MUX, and one data input of the first AND gate; the output of the first 2-to-1 MUX is connected to the other data input of the second 2-to-1 MUX; the output of the second 2-to-1 MUX is connected to the data input of the first DFF; the selection control signal input of the second 2-to-1 MUX is connected to the selection control signal input of the fourth 2-to-1 MUX, and the first AND gate. The output terminals of the gates are connected. The other data input terminal of the third 2-to-1 MUX is connected to the other data input terminal of the first AND gate, one data input terminal of the fourth 2-to-1 MUX, the output terminal of the second DFF, and one data input terminal of the second AND gate. This serves as the masking control signal output terminal of the saturation counter module, used to output the masking control signal mask. The output terminal of the third 2-to-1 MUX is connected to the other data input terminal of the fourth 2-to-1 MUX, and the output terminal of the fourth 2-to-1 MUX is connected to the data input terminal of the second DFF. The other data input terminal of the second AND gate is the repeatability detection result input terminal of the saturation counter module, used to receive the repeatability detection result output by the repeatability detection module. If is_repeat, the NOT input of the second AND gate is connected to the output of the seventh 2-to-1 MUX as the output of the saturation counter module to output the overflow indicator signal overflow; the output of the second AND gate is connected to the selection control signal input of the fifth 2-to-1 MUX, one data input of the adder is connected to a high level, and the other data input of the adder is connected to one data input of the sixth 2-to-1 MUX, the output of the register, one input of the first equal value comparator, and one input of the second equal value comparator as the output of the saturation counter module to output the count value counter[7:0];The output of the adder is connected to one data input of the fifth 2-to-1 MUX. The other data input of the fifth 2-to-1 MUX receives the signal 8'h01 corresponding to the default value of the counter being 1. The output of the fifth 2-to-1 MUX is connected to the other data input of the sixth 2-to-1 MUX. The output of the sixth 2-to-1 MUX is connected to the data input of the register. The other input of the first equal-value comparator receives the maximum count value signal 8'd15 corresponding to the effective bit width of the counter being 4 bits. The other input of the second equal-value comparator receives the maximum count value signal 8'd255 corresponding to the effective bit width of the counter being 8 bits. The outputs of the first and second equal-value comparators are connected one-to-one with the two data inputs of the seventh 2-to-1 MUX. The register is an 8-bit register composed of eight D flip-flops connected in parallel.

[0031] like Figure 4 As shown, in the saturation counter module, the maximum bit width of the counter is 8 bits. Its maximum count value can be configured according to the effective bit width of the counter, specifically by selecting the overflow value using the mod_sel signal. Different effective bit widths and maximum count values ​​can be selected: when mod_sel=1, the effective bit width of the counter is 8 bits, and its maximum count value is 2. 8 -1=255. When the counter counts to 255, it overflows. After overflow, the count value will return to 1. Simultaneously, if there is an overflow, the overflow indicator signal overflow=1 is output; otherwise, if there is no overflow, the overflow indicator signal overflow=0 is output. When mod_sel=0, the effective bit width of the counter is 4 bits, and its maximum count value is 2. 4-1=15. When the counter counts to 15, it overflows. After overflow, the count value will return to 1. Simultaneously, if there is an overflow, the overflow indicator signal overflow=1 is output; otherwise, if there is no overflow, the overflow indicator signal overflow=0 is output. The specific logic for generating the masking control signal mask is as follows: When the saturation counter module is reset, the mask defaults to 0. After reset, if two data entries have been shifted into the shift register group module, the output mask is 1, and it remains 1 until a reset action occurs and clears it to zero. The specific functions of the masking control signal mask are: ① When mask is 1, the counter is allowed to increment by 1; ② Mask is provided to the data assembly module. When mask is 1, the output valid indicator signal output_valid is allowed to be output; otherwise, the output valid indicator signal output_valid is masked to 0. The output logic of the counter value specifically includes: ① The default value of counter is 1, and counter = 1 when the saturation counter module is reset; ② The counter value is updated when there is data input, that is, when the input valid indication signal data_valid = 1; ③ When data_valid is 0, the counter value remains unchanged; ④ When data_valid is 1, if the repeatability detection result is_repeat output by the repeatability detection module is 1, and at this time mask = 1 and overflow = 0, then the counter is incremented by 1; ⑤ When data_valid is 1, if the repeatability detection result is_repeat output by the repeatability detection module is 0, or mask = 0, or overflow = 1, then the counter is automatically reset to the default value of 1.

[0032] In this embodiment, the internal circuitry of the data assembly module is as follows: Figure 5As shown, this specifically includes: the clock input terminals of DFF 1 and DFF 2 are connected as the fourth input terminal of the data assembly module to receive the clock signal clk; the reset control terminals of DFF 1 and DFF 2 are connected as the fifth input terminal of the data assembly module to receive the reset signal rst_n; one data input terminal of AND gate 1 is connected to the data input terminal of DFF 2 as the eighth input terminal of the data assembly module to receive the input validity indication signal data_valid; and the NOT input terminal of AND gate 1 is connected to one data input terminal of AND gate 2 and the NOT input terminal of AND gate 3 as the seventh input terminal of the data assembly module to receive the input signal from the repeat detection module. The repeatability test result is_repeat. The other data input of AND gate 2 is connected to one data input of OR gate 2 as the overflow indicator signal input of the data assembly module to receive the overflow indicator signal. The output of AND gate 1 is connected to the selection control signal input of MUX 1. One data input of MUX 1 is grounded. The other data input of MUX 1 is connected to the output of DFF 1 and one data input of OR gate 1. The output of MUX 1 is connected to one data input of MUX 2. The other data input of MUX 2 is... The input is connected to a high level. The output of the second 2-to-1 MUX is connected to the data input of the first DFF. One input of the comparator is used as the data noise filtering length selection input of the data assembly module to receive the data noise filtering length selection signal flt_cfg. The other input of the comparator is connected to one input of the bit splicing module as the count value input of the data assembly module to receive the count value counter[7:0]. The output of the comparator is connected to the other data input of the first OR gate. The output of the first OR gate is connected to one data input of the third AND gate. The output of the third AND gate is connected to the other data input of the second OR gate. The output of the OR gate and the output of the second DFF are respectively connected to two of the data inputs of the fourth AND gate. The third data input of the fourth AND gate serves as the masking control signal input of the data assembly module to receive the masking control signal mask. The output of the fourth AND gate serves as the output valid indicator signal output of the data assembly module to output the output valid indicator signal output_valid. The other input of the bit splicing serves as the sixth input of the data assembly module to receive the historical data old_data[7:0]. The output of the bit splicing serves as the data output of the data assembly module to output the compressed output data compressed_data. The greater than comparator is a numerical comparator used to determine whether input data 1 (counter) is greater than input data 2 (flt_cfg). If the output of the greater than comparator is 1, it means that input data 1 is greater than input data 2.

[0033] like Figure 5 As shown, in the data assembly module, the target data and the count value counter are directly bit-concatenated. Since the purpose of this invention is to compress repetitive data, the output format after bit concatenation is {old_data, counter}, with old_data placed in the high bits and the count value counter placed in the low 8 bits. After bit concatenation, the compressed output data compressed_data[15:0] is obtained. Bit concatenation utilizes FPGA wiring resources to directly connect the data and the counter, avoiding additional shift logic. Therefore, bit concatenation processing has zero logic overhead. That is, the two sets of signals old_data and counter are directly pulled over and arranged in order to obtain the output result after bit concatenation. No additional logic gate circuits are introduced during the concatenation process, so the bit concatenation process is called zero logic overhead. The output data {old_data, counter} requires synchronization between `old_data` and `counter`. `old_data` always represents the starting value of the repeating sequence (e.g., the reference value for consecutive AAH→AAH→AAH is the first AAH). A register temporary storage mechanism ensures a strict correspondence between the data (from the shift register module's `old_data`) and the count value. Furthermore, to facilitate accurate acquisition of the compressed output data `compressed_data` by subsequent circuits, this data assembly module provides an output validity indicator signal `output_valid`: when `output_valid` is 1, it indicates that the compressed output data `compressed_data` is valid and usable; otherwise, it is considered invalid. The high-level target length of `output_valid` is one clock cycle. Specifically, the output triggering rule for `compressed_data` is as follows: when non-repeating data is detected, or when the counter overflows (i.e., the overflow indicator signal `overflow` from the saturation counter module is 1), the corresponding data and count value will be compressed and output.

[0034] It is worth noting that if, after a reset, the first input data differs from the default value of the shift register group module, immediately triggering a data compression output is clearly incorrect. The output of the repeat detection module is only meaningful after at least the second input data has been received. If the first data, the second data, and even subsequent data are identical, and the first data is compressed and sent before the second data is received, it will ultimately result in an extra data transmission, a situation that needs to be avoided. To address this, a masking control signal `mask` is set in the saturation counter module. `output_valid` is only allowed when `mask` is 1; otherwise, `output_valid` is forcibly masked to 0. The masking control signal `mask` can prevent a false triggering of a data compression output due to the difference between the input data and the default value of the shift register group module during the initial stage after reset (when the first data is input). The control effect of `mask` is... Figure 6 and Figure 8 This is reflected in both.

[0035] The data assembly module includes an input validity indication delay signal, data_valid_diy, such as... Figure 5 As shown, its generation logic is as follows: using a second DFF, data_valid_diy is obtained by clocking once on the valid edge of clk; when data_valid_diy is reset, its value is 0. The function of data_valid_diy is to ensure that the high level duration of output_valid is one clock cycle, not longer. This ensures that each valid compressed code output is sampled only once, instead of being repeatedly sampled and causing multiple data transmissions. The control function of data_valid_diy is... Figure 6 and Figure 8 This is reflected in both.

[0036] The input port of the data assembly module has a data noise filtering length selection signal flt_cfg. By configuring flt_cfg, different repetition modes can be adapted. Different flt_cfg settings correspond to different data noise filtering lengths, as shown in Table 1. The control function of flt_cfg is... Figure 6 , Figure 7 and Figure 8 This is reflected in both.

[0037] Table 1: Data Noise Filtering Length Settings When consecutive identical data segments are long and exceed the counter overflow value, they should be compressed and output in batches. For example, if the counter overflow value is 15 and the input data sequence contains 16 consecutive AAHs, the data assembly module will output them in two parts: (AAH, 0FH) and (AAH, 01H). As another example, if the input data sequence contains 32 consecutive AAHs, the data assembly module will output them in three parts: (AAH, 0FH), (AAH, 0FH), and (AAH, 02H).

[0038] It is particularly important to note that if the data noise filtering length is set to a non-zero value, special care must be taken to prevent the tail data from being omitted in the compressed output of long sequences. For example, a flt_cfg setting of 10B can filter out noise of 2 data lengths. If the counter overflow value is 15 and the input data sequence contains 16 consecutive AAHs, the data assembly module should output (AAH, 0FH) and (AAH, 01H). It should not be filtered out simply because the amount of data sent the second time is less than the flt_cfg value. This is because the remaining data is the same as the previous 15 data, accumulating to 16 consecutive identical data, far exceeding the flt_cfg setting. Therefore, the number of AAHs in the batch compression output should be the same as the number of consecutive AAHs in the input. To ensure this, a tail_window logic signal is specifically included in the data assembly module. Its function is to ensure that the remaining data at the tail is not lost when compressing and outputting repetitive long sequences. The number of remaining data is the modulo of the number of consecutive repetitive data points divided by the counter overflow value, i.e., the remainder. The tail_window control function is... Figure 6 and Figure 7 This is reflected in all of them. The generation logic of tail_window is as follows: When reset, the default value of tail_window is 0; when the is_repeat output of the repeat detection module is 1 and the overflow of the saturation counter module occurs, that is, the overflow output of the saturation counter module is 1, tail_window is set to 1; when there is data input, that is, data_valid is 1 and the is_repeat output of the repeat detection module is 0, tail_window is cleared to 0; at other times, tail_window is maintained.

[0039] In this embodiment, traditional compression algorithms may involve complex logic and state machines, which have been simplified in this invention. The key point of this data compression processing circuit lies in its duplicate detection-counting encoding architecture, using comparators and counters to achieve real-time compression. It mainly includes a shift register group module, a duplicate detection module, a saturation counter module, and a data assembly module, such as... Figure 1As shown. The data flow is as follows: Input data sequence is buffered using a two-stage shift register → the equal value comparator in the repetition detection module detects consecutive identical data → the saturation counter module records the repetition count → when data changes or the counter overflows, the compressed data pair `compressed_data` (data `old_data`, count value `counter`) is output. The specific processing logic rules of this data compression circuit are: ① Comparison mechanism: the current data is compared with the previous data each time; ② Repetition determination: if the current data is the same as the previous one (the two data in the shift register group module are equal), the counter increments; otherwise, the currently accumulated count value is output and the counter is reset, with a reset value of 1; Output trigger condition: data change or the counter reaches its maximum value (assuming the effective bit width of the counter is set to 4, the maximum count value is 15). The `old_data` of the data assembly module comes from the `old_data` output by the shift register group module. When new non-repetitive data is input, the data assembly module immediately compresses and outputs the previous data and the corresponding count value `counter`, with `output_valid` high for one clock cycle. The hardware synchronization mechanism ensures that the data `old_data` and the count value `counter` strictly correspond.

[0040] The input rate of the input data_in can be continuous (i.e., data_valid is continuously high) or intermittent (i.e., data_valid is pulsed with low-level intervals of any clock cycle). The timing waveform can be found in [reference needed]. Figure 6 , Figure 7 , Figure 8 . Figure 6 In the code, mod_sel=0 reflects the control functions of mask, data_validdly, and tail_window, and demonstrates the data compression output when the counter overflows. Figure 7 In this context, rst_n, mod_sel, mask, data_valid, and data_valid_diy are all at high levels, which can reflect the digital noise filtering function and the counter overflow value selection function. Figure 8 In the code, mod_sel, overflow, and tail_window are all low, indicating a random input data sequence. Data is transmitted continuously for a period, followed by a period of inactivity, and then intermittently transmitted again. In this case, the compressed output data (compressed_data) and the output valid indicator signal (output_valid) remain correct. The overall circuit performance can achieve single-cycle throughput: processing one data item per clock cycle, ensuring its real-time performance.

[0041] The overflow value selection signal `mod_sel` in this data compression processing circuit is of great significance. Specifically, for data sequences with long repetition lengths, different `mod_sel` configurations will result in different compression encoding output delays. For example, if `mod_sel` is set to 1, the counter overflow value is 255. For AAH data with a repetition length of 256, the data assembly module needs to have shifted in 255 data points before outputting the first batch of compressed data. This introduces a long response delay. If such a slow response speed is unacceptable in practical applications, `mod_sel` can be set to 0, so that the data assembly module can output data promptly after shifting in 15 consecutive identical data points. Furthermore, different `mod_sel` configurations affect the data compression ratio. To maximize the compression ratio, `mod_sel` should be set to 1. The longer the average repetition length of the data sequence, the more effective the compression ratio will be when `mod_sel` is set to 1.

[0042] The configuration of the data compression processing circuit with the data noise filtering length selection signal flt_cfg is of great significance, as flt_cfg can be configured as needed. Specifically, some sensor data may experience slight fluctuations in a short period, resulting in two consecutive different values, but remaining stable over a long period. If these short-term fluctuations are considered noise and it is not desired to compress this short-term fluctuating data, the flt_cfg configuration item can be set. Setting the flt_cfg to 00B results in no data loss during compression, suitable for highly dynamic scenarios (such as rapid fluctuations in vibration sensors), but it is sensitive to transient noise, and the compression ratio will decrease. Setting the flt_cfg to other values ​​requires multiple consecutive data points to be identical, suitable for steady-state or slowly changing scenarios (such as temperature monitoring), and its advantage is the suppression of occasional noise and improved compression efficiency. The core value of configurable data noise filtering length lies in scenario adaptation; by configuring flt_cfg, compression ratio and noise immunity are balanced to adapt to diverse data patterns.

[0043] In this embodiment, assume that the redundancy is P, that is, the proportion of the "redundant" part in the continuously repeated data to the total data is P, the average repeat sequence length is L, the input data bit width is X bits, the output data bit width is Y bits, and the total data volume of the input data sequence is N entries, then the total number of repeat sequences is (P*N) / L, and the non-repeated data volume is (1-P)*N. In this case, the original data volume is N*X, and the compressed data volume is [(P*N) / L]*Y+(1-P)*N*Y. The compression ratio is the ratio of the compressed data volume to the original data volume. If the compression ratio is less than 1, it indicates that the data is compressed; if the compression ratio is greater than or equal to 1, it indicates that the data is not compressed or even expanded; the smaller the compression ratio, the better the compression effect. The calculation formula of the compression ratio is: compression ratio = [(P*N / L+(1-P)*N)*Y] / (N*X). After simplifying this compression ratio calculation formula, the compression ratio = [(P / L+(1-P))*Y] / X=(P / L+1-P)*(Y / X). To make the compression ratio less than 1, (P / L+1-P)*(Y / X)<1, that is, P / L+1-P<X / Y, which can be finally rearranged as: P>(1-X / Y) / (1-1 / L). It can be seen from this formula that the data compression processing circuit has practical value, and its practical value depends on the following three core indicators: ① Redundancy P: the proportion of the repeated part in the data to the data; ② Average repeat length L: the average length of consecutive identical data in a repeat sequence; ③ Input-output bit width ratio X / Y. Among them, the redundancy can be used to measure the compressibility of data. The higher the redundancy, the greater the compression potential. When the redundancy needs to exceed (1-X / Y) / (1-1 / L), the corresponding compression ratio can be reduced to less than 100%, which reflects the practical value of the data compression processing circuit.

[0044] For example, analyzing a data compression circuit with an input data width of 8 bits, a counter width of 8 bits, and an output data width of 16 bits, we find that the compression ratio is (P / L + 1 - P) * (16 / 8) < 1, and its redundancy needs to satisfy: P > (1 / 2) / (1 - 1 / L). Analyzing a data compression circuit with an input data width of 16 bits, a counter width of 8 bits, and an output data width of 24 bits, we find that the compression ratio is (P / L + 1 - P) * (24 / 16) < 1, and its redundancy needs to satisfy: P > (1 / 3) / (1 - 1 / L). Analyzing a data compression circuit with an input data width of 24 bits, a counter width of 8 bits, and an output data width of 32 bits, we find that the compression ratio is (P / L + 1 - P) * (32 / 24) < 1, and its redundancy needs to satisfy: P > (1 / 4) / (1 - 1 / L). Analysis of a data compression processing circuit with an input data width of 32 bits, a counter width of 8 bits, and an output data width of 40 bits yields a compression ratio of (P / L+1-P)*(40 / 32)<1, and its redundancy needs to satisfy: P>(1 / 5) / (1-1 / L).

[0045] Table 2: Comparison of Key Thresholds The output signal bit width is the sum of the input signal bit width and the counter bit width; the wider the input signal, the smaller the difference between it and the output bit width. As shown in Table 2, a comparison of key thresholds, when the counter bit width is 8 bits, the average repetition length requirement can be reduced to 2 when the input bit width reaches 16 bits. The longer the input bit width, the lower the minimum redundancy requirement for the same average repetition length. This broadens the application scenarios of the circuit. For example, when the input bit width is 32 bits and the average repetition length is 5, the data stream margin reaches 25%, achieving a compression ratio of less than 1. Therefore, without changing the structure of the compression processing circuit, simply expanding the bit width of the relevant input and output data can effectively reduce the compression ratio, making the compression processing circuit more versatile and expanding its application scenarios. The compression processing circuit of this invention can be applied to application scenarios with a high proportion of repetitive data, such as industrial steady-state data (e.g., constant temperature workshops), equipment vibration monitoring (intermittent repetitive), periodic sensor data (e.g., liquid level monitoring), and steady-state signals in high-frequency sampling (e.g., pressure). It can significantly reduce transmission load and improve system energy efficiency.

[0046] In some embodiments, the compression processing circuit of this invention was implemented using an Intel Cyclone IV EP4CE6F17C6 FPGA. The input data width is 8 bits, the counter width is 8 bits, and the output data width is 16 bits. The final implementation parameters are: 40 logic elements (LEs), 28 registers, and a maximum frequency of 130MHz. A screenshot of the FPGA's synthesis flow summary is shown below. Figure 9 As shown, the Static Timing Analysis (STA) Slow 1200mV 85C Model Fmax Summary report is as follows: Figure 10 As shown. Furthermore, the compression processing circuit is extended to dynamically change the configuration signals flt_cfg and mod_sel through the APB / I2C / SPI / UART interface to adapt to dynamically changing data modes (e.g., flt_cfg is configured to a value of 0 for transient data and a non-zero value for steady-state data).

[0047] In some embodiments, output optimization is also required. At the end of the data stream, the untriggered count value is forced to be output to avoid losing the last segment of repetitive data. A control pulse input can be added to the data assembly module to receive the control pulse signal send_over, which is active high. When send_over is high, it indicates the end of the data sequence. The data assembly module also includes an OR gate (number 3), with the output of an AND gate (number 4) connected to one data input of the OR gate (number 3). The other data input of the OR gate (number 3) serves as the control pulse input for the data assembly module to receive the control pulse signal send_over, and the output of the OR gate (number 3) serves as the output valid indicator signal output for the data assembly module to output a new output valid indicator signal output_valid. By adding an OR gate to OR the send_over signal and the original output_valid signal, the new output valid indicator signal output_valid is obtained, thereby compressing the last segment of repetitive data for output.

[0048] In other embodiments, the sensor's data bit width may be more than 8 bits, such as 16 bits, 24 bits, or 32 bits. Correspondingly, expanding the bit width of the shift register group module, the input bit width of the equal value comparator in the repeat detection module, and the bit width of the data assembly module can achieve circuit scheme adaptation. At the same time, the data compression rate will be significantly improved, making the compression processing circuit in this invention adaptable to a wider range of application scenarios. Furthermore, based on an Intel Cyclone IV EP4CE6F17C6 FPGA, a logic circuit implementation was performed for the scheme with "32-bit input data width, 8-bit counter width, and 40-bit output data width." The final implementation parameters are: LE usage of 91; register usage of 76; and a maximum frequency Fmax of 120MHz.

[0049] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A data compression processing circuit based on FPGA, characterized in that, include: The shift register group module is used to buffer input data, i.e., repetitive data input to the data compression processing circuit; the shift register group module includes a clock signal input terminal, a reset signal input terminal, an input valid indication signal input terminal, a set of data input terminals, a set of current data output terminals, and a set of historical data output terminals; A repetition detection module is used to detect the repetition of two consecutive input data outputs from the shift register group module. The repetition detection module includes a set of current data input terminals, a set of historical data input terminals, and a repetition detection result output terminal. The current data input terminals are connected to the current data output terminal, and the historical data input terminals are connected to the historical data output terminal. A saturation counter module is used to dynamically update the count value based on the repeatability detection result output by the repeatability detection module. The saturation counter module includes a first input terminal, a second input terminal, a repeatability detection result input terminal, a third input terminal, an overflow value selection input terminal, a set of count value output terminals, a count overflow indication signal output terminal, and a masking control signal output terminal. The data assembly module is used to concatenate the historical data output by the shift register group module with the count value into a compressed data packet and output it, and provide an output validity indication signal to achieve real-time compression processing of repetitive data. The data assembly module includes a fourth input terminal, a fifth input terminal, a set of sixth input terminals, a set of count value input terminals, a count overflow indication signal input terminal, a masking control signal input terminal, a data noise filtering length selection input terminal, a seventh input terminal, an eighth input terminal, a set of data output terminals, and an output validity indication signal output terminal. Among them, the count value input terminal is connected to the count value output terminal, the count overflow indication signal input terminal is connected to the saturation count overflow indication signal output terminal, and the masking control signal input terminal is connected to the masking control signal output terminal. Specifically, the clock signal input terminal is connected to the first and fourth input terminals, the reset signal input terminal is connected to the second and fifth input terminals, the input valid indication signal input terminal is connected to the third and eighth input terminals, the historical data output terminal is connected to the historical data input terminal and the sixth input terminal, and the repeatability test result output terminal is connected to the repeatability test result input terminal and the seventh input terminal.

2. The FPGA-based data compression processing circuit according to claim 1, characterized in that, The shift register module includes two 2-to-1 multiplexers, a primary register, and a secondary register. One data input of the first 2-to-1 multiplexer is the data input of the shift register module. The other data input of the first 2-to-1 multiplexer is connected to the output of the primary register to serve as the current data output of the shift register module. The selection control signal inputs of the two 2-to-1 multiplexers are connected to serve as the input valid indication signal input of the shift register module. The output of the first 2-to-1 multiplexer is connected to the data input of the primary register. The clock inputs of the primary register and the secondary register are connected to serve as the clock signal input of the shift register module. The reset control of the primary register and the secondary register are connected to serve as the reset signal input of the shift register module. The output of the primary register is connected to one data input of the second 2-to-1 multiplexer. The other data input of the second 2-to-1 multiplexer is connected to the output of the secondary register to serve as the historical data output of the shift register module. The output of the second 2-to-1 multiplexer is connected to the data input of the secondary register.

3. The FPGA-based data compression processing circuit according to claim 1, characterized in that, The duplicate detection module includes an equal value comparator. The two input terminals of the equal value comparator are the current data input terminal and the historical data input terminal of the duplicate detection module, respectively. The output terminal of the equal value comparator is the duplicate detection result output terminal of the duplicate detection module.

4. The FPGA-based data compression processing circuit according to claim 1, characterized in that, The saturation counter module specifically includes: The clock input terminals of the first D flip-flop, the second D flip-flop, and the register are connected as the first input terminal of the saturation counter module. The reset control terminal of the first D flip-flop, the second D flip-flop, and the register is connected as the second input terminal of the saturation counter module. The selection control signal input terminals of the first 2-to-1 selector, the third 2-to-1 selector, and the sixth 2-to-1 selector are connected as the third input terminal of the saturation counter module. The selection control signal input terminal of the seventh 2-to-1 selector is used as the overflow value selection input terminal of the saturation counter module. One data input terminal of the first 2-to-1 selector is connected to a high level. The other data input terminal of the first 2-to-1 selector is connected to one data input terminal of the second 2-to-1 selector, the output terminal of the first D flip-flop, one data input terminal of the third 2-to-1 selector, and one data input terminal of the first AND gate. The output terminal of the first 2-to-1 selector is connected to the other data input terminal of the second 2-to-1 selector. The output terminal of the second 2-to-1 selector is connected to the data input terminal of the first D flip-flop. The selection control signal input terminal of the second 2-to-1 selector is connected to the selection control signal input terminal of the fourth 2-to-1 selector and the output terminal of the first AND gate. The other data input terminal of the third 2-to-1 selector is connected to the other data input terminal of the first AND gate, one data input terminal of the fourth 2-to-1 selector, the output terminal of the second D flip-flop, and one data input terminal of the second AND gate as the masking control signal output terminal of the saturation counter module. The output terminal of the third 2-to-1 selector is connected to the other data input terminal of the fourth 2-to-1 selector. The output terminal of the fourth 2-to-1 selector is connected to the data input terminal of the second D flip-flop. The other data input of the second AND gate is the repeatability detection result input of the saturation counter module. The NOT input of the second AND gate is connected to the output of the seventh 2-to-1 selector as the count overflow indication signal output of the saturation counter module. The output of the second AND gate is connected to the selection control signal input of the fifth 2-to-1 selector. One data input of the adder is connected to a high level. The other data input of the adder is connected to a data input of the sixth 2-to-1 selector, the output of the register, an input of the first equivalent comparator, and an input of the second equivalent comparator as the count value output of the saturation counter module. The output of the adder is connected to the fifth 2-to-1 selector... One data input terminal of the first 2-to-1 selector is connected to the other data input terminal of the second 2-to-1 selector, which receives the signal corresponding to the default value of the counter being 1. The output terminal of the fifth 2-to-1 selector is connected to the other data input terminal of the sixth 2-to-1 selector, and the output terminal of the sixth 2-to-1 selector is connected to the data input terminal of the register. The other input terminal of the first equal-value comparator receives the maximum count value signal corresponding to the effective bit width of the counter being 4 bits, and the other input terminal of the second equal-value comparator receives the maximum count value signal corresponding to the effective bit width of the counter being 8 bits. The output terminals of the first and second equal-value comparators are connected one-to-one to the two data input terminals of the seventh 2-to-1 selector.

5. The FPGA-based data compression processing circuit according to claim 1, characterized in that, The data assembly module specifically includes: The clock inputs of D flip-flops 1 and 2 are connected as the fourth input of the data assembly module. The reset control terminals of D flip-flops 1 and 2 are connected as the fifth input of the data assembly module. One data input of AND gate 1 is connected to the data input of D flip-flop 2 as the eighth input of the data assembly module. The NOT input of AND gate 1 is connected to one data input of AND gate 2 and the NOT input of AND gate 3 as the seventh input of the data assembly module. The other data input of AND gate 2 is connected to one data input of OR gate 2 as the count overflow indicator signal input of the data assembly module. The output of AND gate 1 is connected to the selection control signal input of 2-to-1 selector 1. One data input of 2-to-1 selector 1 is grounded. The other data input of 2-to-1 selector 1 is connected to the output of D flip-flop 1 and one data input of OR gate 1. The output of 2-to-1 selector 1 is connected to one data input of 2-to-1 selector 2. The other data input of the selector is connected to a high level. The output of the second 2-to-1 selector is connected to the data input of the first D flip-flop. One input of the larger comparator is used as the data noise filtering length selection input of the data assembly module. The other input of the larger comparator is connected to one input of the bit splicing as the count value input of the data assembly module. The output of the larger comparator is connected to the other data input of the first OR gate. The output of the first OR gate is connected to one data input of the third AND gate. The output of the third AND gate is connected to the other data input of the second OR gate. The output of the second OR gate and the output of the second D flip-flop are respectively connected to two data inputs of the fourth AND gate. The third data input of the fourth AND gate is used as the masking control signal input of the data assembly module. The output of the fourth AND gate is used as the output valid indication signal output of the data assembly module. The other input of the bit splicing is used as the sixth input of the data assembly module. The output of the bit splicing is used as the data output of the data assembly module.

6. The FPGA-based data compression processing circuit according to claim 5, characterized in that, The data assembly module also includes a control pulse input terminal for receiving control pulse signals.

7. The FPGA-based data compression processing circuit according to claim 6, characterized in that, The data assembly module also includes a No. 3 OR gate, the output of the No. 4 AND gate is connected to one data input of the No. 3 OR gate, the other data input of the No. 3 OR gate serves as the control pulse input of the data assembly module, and the output of the No. 3 OR gate serves as the output valid indication signal output of the data assembly module.

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