Redundant gateway

Abstract

The utility model provides a kind of redundancy gateway, comprising: main control chip, two or more Ethernet chips, Ethernet chip is connected with main control chip communication;Switching circuit is electrically connected with two or more Ethernet chips, switching circuit realizes the communication connection of network interface and selected Ethernet chip;Isolation control circuit is electrically connected with main control chip, isolation control circuit is electrically connected with switching circuit, isolation control circuit controls switching circuit to switch two or more Ethernet chips according to the first switching signal of main control chip;Two or more conversion modules, conversion module is connected with acquisition interface communication;Conversion circuit is electrically connected with isolation control circuit and two or more conversion modules, conversion circuit realizes the communication connection of selected conversion module and isolation control circuit, conversion circuit is controlled to switch conversion module by isolation control circuit.The utility model is switched by the redundancy design of Ethernet chip and conversion module, ensure the smoothness of the link of gateway.

Description

Technical Field

[0001] This utility model relates to the field of industrial intelligent technology, and in particular to a redundant gateway. Background Technology

[0002] Industrial smart gateways, also known as data collectors, are intelligent products widely used in industrial applications. They can collect data from industrial equipment, such as sensors and water / electricity meters, and transmit the data to an industrial IoT platform via Ethernet for data display and control.

[0003] However, industrial environments are often harsh, especially outdoors, where they are highly susceptible to interference from lightning strikes, surges, and static electricity. Typically, this interference can damage gateway devices via wired Ethernet and data acquisition interfaces (RS485 / RS232 / MBUS). A common practice is to enhance the electromagnetic shielding of the Ethernet and data acquisition interfaces; however, once electromagnetic interference enters the gateway's motherboard, it can damage the interfaces, causing communication failures or data acquisition malfunctions. Utility Model Content

[0004] The redundant gateway provided by this utility model ensures the smooth operation of the gateway link through the redundant design of the Ethernet chip and conversion module.

[0005] This utility model provides a redundant gateway, including: Main control chip, Two or more Ethernet chips, wherein the Ethernet chips are communicatively connected to the main control chip; A switching circuit is electrically connected to two or more Ethernet chips, and the switching circuit realizes the communication connection between the network port and the selected Ethernet chip. An isolation control circuit is electrically connected to the main control chip and to the switching circuit. The isolation control circuit controls the switching circuit to switch between two or more Ethernet chips according to the first switching signal of the main control chip. Two or more conversion modules, wherein the conversion modules are communicatively connected to the acquisition interface; A conversion circuit is electrically connected to the isolation control circuit and two or more conversion modules. The conversion circuit enables communication between the selected conversion module and the isolation control circuit. The conversion circuit is controlled by the isolation control circuit to switch the conversion modules.

[0006] Optionally, the two or more Ethernet chips include: A first Ethernet chip communicates with the main control chip via a simplified media independent interface (RMII). The first Ethernet chip has a first receive differential pin pair and a first transmit differential pin pair, which are communicatively connected to the switching circuit. The second Ethernet chip communicates with the main control chip via a simplified media independent interface (RMII). The second Ethernet chip has a second receive differential pin pair and a second transmit differential pin pair, which are communicatively connected to the switching circuit.

[0007] Optionally, the switching circuit includes: The first relay has its normally closed pin electrically connected to the first transmit differential pin, its normally open pin electrically connected to the second transmit differential pin, and its common pin electrically connected to the network port. The positive and negative terminals of the coil of the first relay are electrically connected through a Schottky diode and a capacitor connected in parallel. The second relay has its normally closed pin electrically connected to the first receiving differential pin, its normally open pin electrically connected to the second receiving differential pin, and its common pin electrically connected to the network port for communication. The positive terminal of the second relay's coil is electrically connected to the positive terminal of the first relay's coil, and the negative terminal of the second relay's coil is electrically connected to the negative terminal of the first relay's coil.

[0008] Optionally, the switching circuit further includes: The first transistor has its first terminal electrically connected to the negative terminals of the coils of the first and second relays, and its second terminal grounded. A voltage detection and reset chip, wherein the reset signal pin of the voltage detection and reset chip is electrically connected to the base of a first transistor, and the voltage source pin of the voltage detection and reset chip is electrically connected to an isolation control circuit; A high-speed comparator, wherein the positive power supply pin and the non-inverting input pin of the high-speed comparator are electrically connected, and the output pin of the high-speed comparator is electrically connected to the voltage source pin of the voltage detection and reset chip; The voltage divider branch includes a diode and two voltage divider resistors connected in series. The first end of the voltage divider branch is electrically connected to one of the pins of the first receive differential pin pair and the first transmit differential pin pair. The first end of the voltage divider branch is grounded through a transient suppression diode. The second end of the voltage divider branch is grounded. The common terminal of the two voltage divider resistors is electrically connected to the positive input pin of the high-speed comparator.

[0009] Optionally, the two or more conversion modules include: The first serial port conversion chip has a first differential signal pin pair that is communicatively connected to the acquisition interface, and a first receive output pin and a first transmit input pin that are electrically connected to the conversion circuit. The second serial port conversion chip has its second differential signal pin connected to the acquisition interface, and its second receive output pin and second transmit input pin electrically connected to the conversion circuit.

[0010] Optionally, the conversion circuit includes: The third relay has its normally closed pin electrically connected to the first receive output pin and the first transmit input pin of the first serial port conversion chip, and its normally open pin electrically connected to the second receive output pin and the second transmit input pin of the second serial port conversion chip. The common pin of the third relay is communicatively connected to the isolation control circuit. The positive and negative terminals of the coil of the third relay are electrically connected through a Schottky diode and a capacitor connected in parallel. The second transistor has its first terminal electrically connected to the negative terminal of the coil of the third relay, and its second terminal grounded. A voltage divider resistor string, wherein the first end of the voltage divider resistor string is electrically connected to a voltage source, the second end of the voltage divider resistor string is electrically connected to the base of a second transistor, and the common end of the voltage divider resistor string is electrically connected to an isolation control circuit.

[0011] Optionally, the two or more conversion modules further include: A first enabling circuit, comprising: The first resistor is electrically connected to the isolation voltage node, and the second end of the first resistor is electrically connected to the first receive enable pin and the first transmit enable pin of the first serial port conversion chip. The third transistor has its first terminal electrically connected to the second terminal of the first resistor, and its second terminal grounded. The second resistor has its first end electrically connected to one of the first receive output pin and the first transmit input pin, and its second end electrically connected to the base of the third transistor. The third resistor has its first end electrically connected to the second end of the second resistor, and the second end of the third resistor is grounded. A second enabling circuit, comprising: The fourth resistor is electrically connected to the isolation voltage node, and the second end of the fourth resistor is electrically connected to the receive enable pin and the transmit enable pin of the second serial port conversion chip. The fourth transistor has its first terminal electrically connected to the second terminal of the fourth resistor, and its second terminal is grounded. The fifth resistor has its first end electrically connected to one of the second receive output pin and the second transmit input pin, and its second end electrically connected to the base of the fourth transistor. The sixth resistor has its first end electrically connected to the second end of the fifth resistor, and its second end is grounded.

[0012] Optionally, two pins in the third differential signal pin pair of the acquisition interface are grounded through bidirectional transient suppression diodes, the negative pin in the third differential signal pin pair is electrically connected to the isolation voltage node through a pull-up resistor, and the positive pin in the third differential signal pin pair is electrically connected to the isolation voltage node through a pull-down resistor.

[0013] Optionally, the isolation control circuit includes: A first isolation chip, a first side of the first isolation chip is communicatively connected to the conversion circuit, and a second side of the first isolation chip is communicatively connected to the main control chip; The second isolation chip has a first pin on the first side that outputs a first control signal to the switching circuit, and a second pin on the first side that outputs a second control signal to the conversion circuit. The first pin on the second side of the second isolation chip receives the first control signal from the main control chip, and the second pin on the second side of the isolation chip receives the second control signal from the main control chip.

[0014] Optionally, it also includes an isolation power supply, wherein the input side of the isolation power supply is electrically connected to the power supply voltage source via a ferrite bead, the output side of the isolation power supply is electrically connected to an isolation voltage node via a ferrite bead, the isolation voltage node is grounded via two parallel capacitors, and the output side of the isolation power supply is grounded via a transient suppression diode; The power supply voltage source is used to supply power to the switching circuit, two or more Ethernet chips and the main control chip, and the isolation voltage node is used to supply power to two or more conversion modules and the conversion circuit.

[0015] This invention incorporates redundant Ethernet chips and redundant conversion modules, and switches between these redundant Ethernet chips and redundant conversion modules via an isolation control circuit. This ensures the smooth operation of the data acquisition link and prevents data loss due to device failure. Attached Figure Description

[0016] Figure 1 This is a structural block diagram of a redundant gateway according to an embodiment of the present invention; Figure 2This is a schematic diagram of the main control chip of a redundant gateway according to another embodiment of the present invention; Figure 3 This is a schematic diagram of the first Ethernet chip of a redundant gateway according to another embodiment of the present invention; Figure 4 This is a schematic diagram of the second Ethernet chip in a redundant gateway according to another embodiment of the present invention; Figure 5 This is a schematic diagram of the switching circuit of a redundant gateway according to another embodiment of the present invention; Figure 6 This is a schematic diagram of the network transformer of a redundant gateway according to another embodiment of the present invention; Figure 7 This is a schematic diagram of two or more conversion modules of a redundant gateway according to another embodiment of the present invention; Figure 8 This is a schematic diagram of the conversion circuit of a redundant gateway according to another embodiment of the present invention; Figure 9 This is a schematic diagram of the first enable circuit of two or more conversion modules of a redundant gateway according to another embodiment of the present invention; Figure 10 This is a schematic diagram of the second enable circuit for two or more conversion modules of a redundant gateway according to another embodiment of the present invention; Figure 11 This is a schematic diagram of the isolation control circuit of a redundant gateway according to another embodiment of the present invention; Figure 12 This is a schematic diagram of the isolated power supply of a redundant gateway according to another embodiment of the present invention; Figure 13 This is a schematic diagram of the power supply for a redundant gateway according to another embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0018] This utility model embodiment provides a redundant gateway, such as Figure 1 As shown, it includes: Main control chip U1, In some embodiments, the main control chip U1 serves as the control center of the entire redundant gateway, responsible for collecting data from sub-devices and communicating with the IoT platform. It can also receive control commands from the IoT platform and forward them to the sub-devices.

[0019] Two or more Ethernet chips, wherein the Ethernet chips are communicatively connected to the main control chip U1; In some embodiments, two or more Ethernet chips are designed to be redundant with each other. If the Ethernet chip being used is damaged, other Ethernet chips can be used for Ethernet communication by switching.

[0020] A switching circuit is electrically connected to two or more Ethernet chips, and the switching circuit realizes the communication connection between the network port and the selected Ethernet chip. In some embodiments, the switching circuit is used to switch between two or more Ethernet chips and establish a communication connection between the selected Ethernet chip and the network port. During the switching process, switching can be performed based on control signals sent by the main control chip U1 through the isolation control circuit, or based on the level signals output by the hardware circuit. The network port can be, for example, an RJ45 network interface, responsible for internet communication with external devices. The Ethernet chip can communicate with the network port through a network transformer U6, for example. The main functions of the network transformer U6 are signal isolation, impedance matching, anti-interference, signal enhancement, and transmission distance extension.

[0021] An isolation control circuit is electrically connected to the main control chip U1 and to the switching circuit. The isolation control circuit controls the switching circuit to switch between two or more Ethernet chips according to the first switching signal of the main control chip U1. In some embodiments, the isolation control circuit primarily functions to isolate signals, preventing external electromagnetic interference from directly affecting the main control chip U1 through the signal lines. One side of the isolation control circuit is connected to the main control chip U1, while the other side is connected to a switching circuit, a conversion circuit, and two or more conversion modules, thereby isolating the field side from the control side.

[0022] Two or more conversion modules, wherein the conversion modules are communicatively connected to the acquisition interface; In some embodiments, the main function of the conversion module is to convert the signal level corresponding to the acquisition interface with the signal level inside the main control chip U1, such as converting RS485 level to TTL level inside the main control chip U1. Two or more conversion modules are redundant; if the conversion module in use fails, other conversion modules can be used for communication.

[0023] A conversion circuit is electrically connected to the isolation control circuit and two or more conversion modules. The conversion circuit enables communication between the selected conversion module and the isolation control circuit. The conversion circuit is controlled by the isolation control circuit to switch the conversion modules.

[0024] In some embodiments, the conversion circuit is mainly used to switch between two or more conversion modules. During switching, the switching can be performed according to the control signal sent by the main control chip U1 through the isolation control circuit, or according to the level signal output by the hardware circuit.

[0025] In this embodiment of the invention, redundant Ethernet chips and redundant conversion modules are designed, and the redundant Ethernet chips and redundant conversion modules are switched through an isolation control circuit. This ensures the smooth operation of the data acquisition link and avoids the disconnection of the data acquisition link due to device damage, thereby preventing data loss.

[0026] As an optional implementation method, such as Figures 2-4 As shown, the two or more Ethernet chips include: The first Ethernet chip U2 is connected to the main control chip U1 via a simplified media independent interface RMII. The first Ethernet chip U2 has a first receive differential pin pair and a first transmit differential pin pair, which are connected to the switching circuit. The second Ethernet chip U3 is connected to the main control chip U1 via a simplified media independent interface RMII. The second Ethernet chip U3 has a second receive differential pin pair and a second transmit differential pin pair, which are connected to the switching circuit.

[0027] In some embodiments, the two Ethernet chips have the same function. Both Ethernet chips are connected to the main control chip U1 via a simplified media independent interface RMII (involving signals including RMII_TXEN, RMII_TXD0, RMII_TXD1, RMII_RXDV, RMII_RXD0, RMII_RXD1, RMII_MDC, RMII_MDIO, and RMII_NRST) to achieve data transmission with the main control chip U1. The first Ethernet chip U2 is connected to the switching circuit via RX_N1, RX_P1, TX_N1, and TX_P1, where RX_N1 and RX_P1 form a first receive differential pin pair, and TX_N1 and TX_P1 form a first transmit differential pin pair. The second Ethernet chip U3 is connected to the switching circuit via RX_N2, RX_P2, TX_N2, and TX_P2, where RX_N2 and RX_P2 form a second receive differential pin pair, and TX_N2 and TX_P2 form a second transmit differential pin pair.

[0028] As an optional implementation method, such as Figures 5-6 As shown, the switching circuit includes: The first relay K1 has its normally closed pin connected to the first transmit differential pin, its normally open pin connected to the second transmit differential pin, and its common pin connected to the network port. The positive and negative terminals of the coil of the first relay K1 are connected in parallel through a Schottky diode and a capacitor. The second relay K2 has its normally closed pin electrically connected to the first receiving differential pin, its normally open pin electrically connected to the second receiving differential pin, and its common pin electrically connected to the network port. The positive terminal of the coil of the second relay K2 is electrically connected to the positive terminal of the coil of the first relay K1, and the negative terminal of the coil of the second relay K2 is electrically connected to the negative terminal of the coil of the first relay K1.

[0029] As an optional implementation method, such as Figures 5-6 As shown, the switching circuit further includes: The first transistor Q1 has its first terminal electrically connected to the negative terminals of the coils of the first relay K1 and the second relay K2, and its second terminal grounded. A voltage detection and reset chip U4, wherein the reset signal pin of the voltage detection and reset chip U4 is electrically connected to the base of the first transistor Q1, and the voltage source pin of the voltage detection and reset chip U4 is electrically connected to the isolation control circuit; High-speed comparator U5, the positive power supply pin and the non-inverting input pin of the high-speed comparator U5 are electrically connected, and the output pin of the high-speed comparator U5 is electrically connected to the voltage source pin of the voltage detection and reset chip U4; The voltage divider branch includes a diode and two voltage divider resistors connected in series. The first end of the voltage divider branch is electrically connected to one of the pins of the first receive differential pin pair and the first transmit differential pin pair. The first end of the voltage divider branch is grounded through a transient suppression diode. The second end of the voltage divider branch is grounded. The common terminal of the two voltage divider resistors is electrically connected to the positive input pin of the high-speed comparator U5.

[0030] In some embodiments, when the gateway's network port is struck by lightning or suffers other abnormalities, the internal Ethernet chip (e.g., the first Ethernet chip U2) is easily damaged. Without a redundant protection mechanism, the network will malfunction, the IoT platform will display the gateway as offline, and on-site personnel will need to be dispatched to troubleshoot and repair the fault. In this embodiment, a program switching mechanism can be configured in the main control chip U1. For example, in the default state, CPU_CON1=PYH_OUT is low, below the voltage threshold of the high-speed comparator U5 (e.g., Vd=2.63V). At this time, the RESET pin outputs a low-level reset signal, the first transistor Q1 is cut off, and the relay is open. The normally closed contacts of the first relay K1 and the second relay K2 are closed (i.e., pin3 connects to pin2, and pin6 connects to pin7), enabling first network communication, and the gateway is normally online. When a network anomaly persists for a certain set time, the main control chip U1 sets the control signal CPU_CON1 = PYH_OUT to a high level, exceeding the voltage threshold of the high-speed comparator U5 (e.g., Vd = 2.63V). The output pin RESET outputs a high-level signal, turning on the first transistor Q1. The negative terminals of the coils of the first relay K1 and the second relay K2 are at a low level, driving the normally open contacts of the first relay K1 and the second relay K2 to close (i.e., pin3 connects to pin4, and pin6 connects to pin5), instantly switching to the second Ethernet chip U3. At this time, Ethernet interacts with the external network through the second Ethernet chip U3, ensuring the gateway on the IoT platform remains online and preventing the loss of critical customer data. If communication returns to normal after switching to the second Ethernet chip U3, the main control chip U1 can report the abnormal data to the backend IoT platform, informing them that the first Ethernet chip U2 has been damaged and the second Ethernet chip U3 has been activated. If communication still fails after switching to the second Ethernet chip U3, it indicates that the network anomaly may be caused by other external factors (such as an upper-layer router losing network or power). If the gateway fails to come online in a timely manner within a certain period of time, the IoT platform can report network anomalies to the customer.

[0031] The aforementioned process involves switching control performed by the main control chip U1 at the software level. To ensure smooth communication, adaptive switching design can also be implemented in hardware. For example... Figure 5 As shown, when the surge residual voltage is too high, exceeding the design voltage of the Ethernet chip, it will definitely damage the Ethernet chip in use. Therefore, the first Ethernet chip U2 in use can be switched to the second Ethernet chip U3 by automatically detecting the surge voltage. That is, the transient suppression diode is connected to one of the differential lines in the network port. When selecting the transient suppression diode, choose one with a clamping voltage of Vin. Under a large surge, the voltage across the transient suppression diode is clamped at Vc. Taking Vc=12V as an example, when there is an excessively high surge residual voltage in the link, the voltage across the transient suppression diode will jump to 12V for a period of time. After passing through the diode and two voltage divider resistors (assuming the two voltage divider resistors are 10kΩ and 3.8kΩ, with the 3.8kΩ resistor being closer to the ground terminal), the positive input pin voltage Vin+ can be calculated as 3.9 / (10+3.9)*12V=3.36V. At this time, the positive input pin voltage Vin+ > the reverse input pin voltage Vin-, which is higher. High-speed comparator U5 can detect instantaneous voltage changes, causing its output pin to go high (PHY_OUT = 3.3V), which is higher than the voltage threshold of voltage detection and reset chip U4 (Vd = 2.63V). Voltage detection and reset chip U4 then outputs a high level, driving the first transistor Q1 to conduct. This causes the normally open contacts of the first relay K1 and the second relay K2 to switch to the energized state (pin3 connects to pin4, and pin6 connects to pin5), instantly switching to the second Ethernet chip U3. When the first Ethernet chip U2 is not affected by interference, the voltage level of the differential line in the network port is much lower than 12V. At this time, the positive input pin voltage Vin+ < the negative input pin voltage Vin-, and the output pin of high-speed comparator U5 goes low (PHY_OUT = 0V). The normally open contacts of the first relay K1 and the second relay K2 are in the open state, and communication is by default using the first Ethernet chip U2. In some preferred embodiments, such as... Figure 6 As shown, the first relay K1 and the second relay K2 can be connected to the network port through the network transformer U6 to achieve electrical isolation and safety protection of the two Ethernet chips, signal transmission and impedance matching, level conversion, anti-static and surge protection.

[0032] As an optional implementation method, such as Figure 7 As shown, the two or more conversion modules include: The first serial port conversion chip U7 has a first differential signal pin pair that is communicatively connected to the acquisition interface, and the first receive output pin and the first transmit input pin of the first serial port conversion chip are electrically connected to the conversion circuit. The second serial port conversion chip U8 has a second differential signal pin that is connected to the acquisition interface for communication, and a second receive output pin and a second transmit input pin that are electrically connected to the conversion circuit.

[0033] As an optional implementation method, such as Figure 8 As shown, the conversion circuit includes: The third relay K3 has its normally closed pin electrically connected to the first receive output pin and the first transmit input pin of the first serial port conversion chip U7, and its normally open pin electrically connected to the second receive output pin and the second transmit input pin of the second serial port conversion chip U8. The common pin of the third relay K3 is communicatively connected to the isolation control circuit. The positive and negative terminals of the coil of the third relay K3 are electrically connected through a Schottky diode and a capacitor connected in parallel. The second transistor Q2 has its first terminal electrically connected to the negative terminal of the coil of the third relay K3, and its second terminal grounded. A voltage divider resistor string, wherein the first end of the voltage divider resistor string is electrically connected to a voltage source, the second end of the voltage divider resistor string is electrically connected to the base of the second transistor Q2, and the common end of the voltage divider resistor string is electrically connected to an isolation control circuit.

[0034] As an optional implementation method, such as Figures 9-10 As shown, the two or more conversion modules further include: A first enabling circuit, comprising: The first resistor R1 is electrically connected to the isolation voltage node, and the second end of the first resistor R1 is electrically connected to the first receive enable pin and the first transmit enable pin of the first serial port conversion chip U7. The third transistor Q3 has its first terminal electrically connected to the second terminal of the first resistor R1, and its second terminal grounded. The second resistor R2 has its first end electrically connected to one of the first receive output pin and the first transmit input pin, and its second end electrically connected to the base of the third transistor Q3. The third resistor R3 has its first end electrically connected to the second end of the second resistor R2, and its second end is grounded. A second enabling circuit, comprising: The fourth resistor R4 is electrically connected to the isolation voltage node, and the second end of the fourth resistor R4 is electrically connected to the second receive enable pin and the second transmit enable pin of the second serial port conversion chip U8. The fourth transistor Q4 has its first terminal electrically connected to the second terminal of the fourth resistor R4, and its second terminal is grounded. The fifth resistor R5 has its first end electrically connected to one of the second receive output pin and the second transmit input pin, and its second end electrically connected to the base of the fourth transistor Q4. The sixth resistor R6 has its first end electrically connected to the second end of the fifth resistor R5, and its second end is grounded.

[0035] In some embodiments, the switching principle of the two conversion modules is similar to the switching method of the two Ethernet chips. The common pin of the third relay K3 in the conversion circuit is connected to the main control chip U1 for communication. The normally closed pin of the third relay K3 is connected to the first receive output pin and the first transmit input pin of the first serial port conversion chip U7, and the normally open pin of the third relay K3 is connected to the second receive output pin and the second transmit input pin of the second serial port conversion chip U8. The first serial port conversion chip U7 and the second serial port conversion chip U8 can be switched via the CPU_CON2 control pin of the main control chip U1. The switching process is similar to the process of the main control chip U1 controlling the switching of the two Ethernet chips via CPU_CON1. ​​By default, CPU_CON2 = UART_OUT is low, at which time the second transistor Q2 is turned on, the negative terminal of the coil of the third relay K3 is grounded, and the relay is energized (i.e., pin3 connects to pin4, and pin6 connects to pin5), and the signal is connected to the first serial port conversion chip U7. When no data is returned within the acquisition cycle, the main control chip U1 switches CPU_CON2=UART_OUT to a high level, using the second serial port conversion chip U8. At this time, CPU_CON2=UART_OUT is high, the second transistor Q2 is cut off, and the third relay K3 is in the open state (i.e., pin3 is connected to pin2, and pin6 is connected to pin7). Switching to the second serial port conversion chip U8, if the second serial port conversion chip U8 can communicate normally at this time, the result (first channel failure) can be reported to the IoT platform via Ethernet communication. At the same time, the second serial port conversion chip U8 can also be used to transmit the acquired data, avoiding the loss of customer acquired information and saving customers economic losses. In some preferred embodiments, taking the first enable circuit as an example, the working principle of the two enable circuits is illustrated. During data reception, since no data is being transmitted, UART_TXD1 is at a high level by default, the third transistor Q3 is turned on, the first receive enable pin RE of the first serial port conversion chip U7 is low-level enabled (valid), and the first receive output pin RO is enabled. At this time, the data received from the first differential signal pin pair of the first serial port conversion chip U7 is sent to the main control chip U1 through the first receive output pin RO, completing the data reception process. During data transmission, since data is being transmitted, UART_TXD1 will have a pull-down level, indicating the start of data transmission. At this time, the third transistor Q3 is turned off, the first transmit enable pin DE of the first serial port conversion chip U7 is high-level, and the first transmit input pin DI is enabled. When data '0' is transmitted, data '0' will be transmitted to the first differential signal pin pair, completing the low-level transmission.When the data '1' is transmitted, the third transistor Q3 is turned on, and the first receive enable pin RE and the first transmit enable pin DE are both at low level. Theoretically, this should be the receive enable, but since the data is still being transmitted, the entire path is in a high impedance state. This state is determined by the pull-up resistor of the negative terminal pin A and the pull-down resistor of the positive terminal pin B in the first differential signal pin pair. At this time, AB>0 transmits '1', completing the transmission of the high level.

[0036] As an optional implementation, two pins of the third differential signal pin pair of the acquisition interface are grounded through bidirectional transient suppression diodes, the negative pin of the third differential signal pin pair is electrically connected to the isolation voltage node through a pull-up resistor, and the positive pin of the third differential signal pin pair is electrically connected to the isolation voltage node through a pull-down resistor.

[0037] As an optional implementation method, such as Figure 11 As shown, the isolation control circuit includes: The first isolation chip U9 has a first side that is communicatively connected to the conversion circuit and a second side that is communicatively connected to the main control chip U1. The second isolation chip U10 has a first pin on the first side that outputs a first control signal to the switching circuit, and a second pin on the first side that outputs a second control signal to the conversion circuit. The first pin on the second side of the second isolation chip U10 receives the first control signal from the main control chip U1, and the second pin on the second side of the isolation chip receives the second control signal from the main control chip U1.

[0038] In some embodiments, the control signals output by the main control chip U1 are isolated by the second isolation chip U10 in the isolation control circuit before being transmitted to the switching circuit and the conversion circuit respectively. At the same time, when the conversion circuit transmits the signals acquired by the acquisition interface, it also needs to be isolated by the first isolation chip U9 in the isolation control circuit before being transmitted to the main control chip U1.

[0039] As an optional implementation method, such as Figure 12 As shown, it also includes an isolation power supply U11. The input side of the isolation power supply U11 is electrically connected to the power supply voltage source through a ferrite bead. The output side of the isolation power supply U11 is electrically connected to the isolation voltage node through a ferrite bead. The isolation voltage node is grounded through two parallel capacitors. The output side of the isolation power supply U11 is grounded through a transient suppression diode. The power supply voltage source is used to supply power to the switching circuit, two or more Ethernet chips and the main control chip U1, and the isolation voltage node is used to supply power to two or more conversion modules and the conversion circuit.

[0040] In some embodiments, such as Figure 13 As shown, the power supply voltage source can be provided, for example, by a DC-DC converter circuit. Specifically, a switching regulator U12 and an external filter circuit can convert the 12V voltage to 3.3V to power the switching circuit, the two or more Ethernet chips, and the main control chip U1. The enable signal of the isolation power supply U11 comes from the main control chip U1, and its input power comes from the power supply voltage source, converting the 3.3V voltage to 5V to power the two or more conversion modules and the conversion circuit.

[0041] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A redundant gateway, characterized in that, include: Main control chip, Two or more Ethernet chips, wherein the Ethernet chips are communicatively connected to the main control chip; A switching circuit is electrically connected to two or more of the Ethernet chips, and the switching circuit realizes the communication connection between the network port and the selected Ethernet chip. An isolation control circuit is electrically connected to the main control chip and to the switching circuit. The isolation control circuit controls the switching circuit to switch between two or more Ethernet chips according to a first switching signal from the main control chip. Two or more conversion modules, wherein the conversion modules are used to communicate with the acquisition interface; A conversion circuit is electrically connected to the isolation control circuit and two or more conversion modules. The conversion circuit enables communication between the selected conversion module and the isolation control circuit. The conversion circuit is controlled by the isolation control circuit to switch the conversion modules.

2. The redundant gateway according to claim 1, characterized in that, The two or more Ethernet chips include: A first Ethernet chip communicates with the main control chip via a simplified media independent interface (RMII). The first Ethernet chip has a first receive differential pin pair and a first transmit differential pin pair, which are communicatively connected to the switching circuit. The second Ethernet chip communicates with the main control chip via a simplified media independent interface (RMII). The second Ethernet chip has a second receive differential pin pair and a second transmit differential pin pair, which are communicatively connected to the switching circuit.

3. The redundant gateway according to claim 2, characterized in that, The switching circuit includes: The first relay has its normally closed pin electrically connected to the first transmit differential pin, its normally open pin electrically connected to the second transmit differential pin, and its common pin electrically connected to the network port. The positive and negative terminals of the coil of the first relay are electrically connected through a Schottky diode and a capacitor connected in parallel. The second relay has its normally closed pin electrically connected to the first receiving differential pin, its normally open pin electrically connected to the second receiving differential pin, and its common pin electrically connected to the network port for communication. The positive terminal of the second relay's coil is electrically connected to the positive terminal of the first relay's coil, and the negative terminal of the second relay's coil is electrically connected to the negative terminal of the first relay's coil.

4. The redundant gateway according to claim 3, characterized in that, The switching circuit further includes: The first transistor has its first terminal electrically connected to the negative terminals of the coils of the first and second relays, and its second terminal grounded. A voltage detection and reset chip, wherein the reset signal pin of the voltage detection and reset chip is electrically connected to the base of the first transistor, and the voltage source pin of the voltage detection and reset chip is electrically connected to the isolation control circuit; A high-speed comparator, wherein the positive power supply pin and the non-inverting input pin of the high-speed comparator are electrically connected, and the output pin of the high-speed comparator is electrically connected to the voltage source pin of the voltage detection and reset chip; The voltage divider branch includes a diode and two voltage divider resistors connected in series. The first end of the voltage divider branch is electrically connected to one of the pins of the first receive differential pin pair and the first transmit differential pin pair. The first end of the voltage divider branch is grounded through a transient suppression diode. The second end of the voltage divider branch is grounded. The common terminal of the two voltage divider resistors is electrically connected to the positive input pin of the high-speed comparator.

5. The redundant gateway according to claim 1, characterized in that, The two or more conversion modules include: The first serial port conversion chip has a first differential signal pin pair that is communicatively connected to the acquisition interface, and the first receive output pin and the first transmit input pin of the first serial port conversion chip are electrically connected to the conversion circuit. The second serial port conversion chip has its second differential signal pin connected to the acquisition interface, and its second receive output pin and second transmit input pin electrically connected to the conversion circuit.

6. The redundant gateway according to claim 5, characterized in that, The conversion circuit includes: The third relay has its normally closed pin electrically connected to the first receive output pin and the first transmit input pin of the first serial port conversion chip, and its normally open pin electrically connected to the second receive output pin and the second transmit input pin of the second serial port conversion chip. The common pin of the third relay is communicatively connected to the isolation control circuit. The positive and negative terminals of the coil of the third relay are electrically connected through a Schottky diode and a capacitor connected in parallel. The second transistor has its first terminal electrically connected to the negative terminal of the coil of the third relay, and its second terminal grounded. A voltage divider resistor string, wherein the first end of the voltage divider resistor string is electrically connected to a voltage source, the second end of the voltage divider resistor string is electrically connected to the base of the second transistor, and the common end of the voltage divider resistor string is electrically connected to the isolation control circuit.

7. The redundant gateway according to claim 5, characterized in that, The two or more conversion modules also include: A first enabling circuit, comprising: The first resistor is electrically connected to the isolation voltage node, and the second end of the first resistor is electrically connected to the first receive enable pin and the first transmit enable pin of the first serial port conversion chip. The third transistor has its first terminal electrically connected to the second terminal of the first resistor, and its second terminal grounded. The second resistor has a first end electrically connected to one of the first receive output pin and the first transmit input pin, and a second end electrically connected to the base of the third transistor. The third resistor has its first end electrically connected to the second end of the second resistor, and its second end is grounded. A second enabling circuit, comprising: The fourth resistor is electrically connected to the isolation voltage node, and the second end of the fourth resistor is electrically connected to the second receive enable pin and the second transmit enable pin of the second serial port conversion chip. The fourth transistor has its first terminal electrically connected to the second terminal of the fourth resistor, and its second terminal is grounded. The fifth resistor has its first end electrically connected to one of the first receive output pin and the second transmit input pin, and its second end electrically connected to the base of the fourth transistor. The sixth resistor has its first end electrically connected to the second end of the fifth resistor, and its second end is grounded.

8. The redundant gateway according to claim 5, characterized in that, Two pins in the third differential signal pin pair of the acquisition interface are grounded through bidirectional transient suppression diodes. The negative pin in the third differential signal pin pair of the acquisition interface is electrically connected to the isolation voltage node through a pull-up resistor, and the positive pin in the third differential signal pin pair of the acquisition interface is electrically connected to the isolation voltage node through a pull-down resistor.

9. The redundant gateway according to claim 1, characterized in that, The isolation control circuit includes: A first isolation chip, a first side of which is communicatively connected to the conversion circuit, and a second side of which is communicatively connected to the main control chip; The second isolation chip has a first pin on the first side that outputs a first control signal to the switching circuit, and a second pin on the first side that outputs a second control signal to the conversion circuit. The first pin on the second side of the second isolation chip receives the first control signal from the main control chip, and the second pin on the second side of the isolation chip receives the second control signal from the main control chip.

10. The redundant gateway according to claim 1, characterized in that, It also includes an isolation power supply, the input side of which is electrically connected to the power supply voltage source through a ferrite bead, the output side of which is electrically connected to an isolation voltage node through a ferrite bead, the isolation voltage node is grounded through two parallel capacitors, and the output side of the isolation power supply is grounded through a transient suppression diode; The power supply voltage source is used to supply power to the switching circuit, two or more Ethernet chips and the main control chip, and the isolation voltage node is used to supply power to two or more conversion modules and the conversion circuit.

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