Network cable tester and test circuit thereof

Abstract

The utility model relates to the technical field of ethernet measuring line, especially to a network cable tester and test circuit thereof, through setting up the ethernet integrated chip integrated with MAC module and PHY module, control circuit and interface circuit, control circuit controls the switching of interface circuit in the communication between MAC module and PHY module, can guarantee that test circuit can have communication function and length measuring function simultaneously while simplifying hardware interface and hardware layout, and need not set timing calibration circuit additionally, reduces the situation of data transmission delay or packet loss, improves the synchronous compatibility, in addition, through the full application MAC and the integration of PHY, make the ethernet integrated chip can adapt to more more extensive MCU resources, improve the flexibility of circuit design, and reduce the material cost and PCB area, make the test circuit can be applicable to small embedded device.

Description

Technical Field

[0001] This utility model relates to the field of cable testing technology, and in particular to a network cable tester and its testing circuit. Background Technology

[0002] A network cable length tester (also known as a network cable length tester, cable measuring instrument, or network cable tester) is an electronic device used to accurately measure the physical length of cables and detect the connection status of cables. Its core function is to analyze the cable length through signal transmission characteristics and locate fault points such as open circuits and short circuits. It can help network technicians quickly and accurately assess the physical length and electrical condition of network cables on-site, thereby improving cabling efficiency and reducing troubleshooting time. It is widely used in the field of network cabling construction and maintenance.

[0003] Currently, network cable length testers typically use the physical layer (PHY) of an Ethernet chip to measure length. However, this chip lacks internet connectivity. To enable both length measurement and internet access for data processing, a separate Ethernet controller chip is required. This chip's media access control (MAC) layer is used to achieve internet access, necessitating the use of two separate Ethernet chips. This requires separate configurations for the MAC controller and PHY chip, occupying up to 16 GPIO pins on the MCU (e.g., in MII mode), resulting in complex hardware wiring and high resource consumption. Furthermore, an additional timing calibration circuit is needed between the MAC and PHY chips, which can lead to data transmission delays or packet loss, resulting in poor synchronization compatibility. The separate dual-chip design also increases material costs and PCB area, making it unsuitable for small embedded devices, thus resulting in higher overall costs. Utility Model Content

[0004] This invention provides a network cable tester and its testing circuit, which simplifies the circuit while enabling cable testing and internet access.

[0005] The first aspect of this utility model discloses a test circuit for a network cable tester, the test circuit including a multi-functional circuit, a control circuit, and an interface circuit, wherein: The multifunctional circuit includes an Ethernet integrated chip, on which a PHY module and a MAC module are integrated; The interface circuit is electrically connected to the multifunctional circuit, and the interface circuit is used to connect a network cable. The control circuit is electrically connected to the multifunctional circuit, and the control circuit is used to control the PHY module to be connected to the interface circuit, or the MAC module to be connected to the interface circuit.

[0006] As an optional implementation, in the first aspect of this utility model, the Ethernet integrated chip further integrates a communication interface module; The Ethernet integrated chip is electrically connected to the control circuit through the communication interface module, wherein: The communication interface module is used by the control circuit to activate the MAC module or PHY module of the Ethernet integrated chip.

[0007] As an optional implementation, in the first aspect of this utility model, the communication interface module includes an SPI interface module or an I2C bus interface. The SPI interface module consists of a chip select pin, a serial clock pin, a master transmit / slave receive pin, a master receive / slave transmit pin, and resistors connected in series with each of the pins.

[0008] As an optional implementation, in the first aspect of this utility model, the multifunctional circuit further includes a reset module: The Ethernet integrated chip is electrically connected to the control circuit through the reset module, wherein: The reset module is used to reset the state of the Ethernet integrated chip when the control circuit switches between the length measurement function and the communication function.

[0009] As an optional implementation, in the first aspect of this utility model, the reset module includes an MCU reset module and a chip reset module, wherein: The control circuit, the MCU reset module, the chip reset module, and the Ethernet integrated chip are electrically connected in sequence. The MCU reset module is used to reset the state of the control circuit, and the chip reset module is used to reset the state of the Ethernet integrated chip.

[0010] As an optional implementation, in the first aspect of this utility model, the Ethernet integrated chip further integrates an interrupt control module; The Ethernet integrated chip is electrically connected to the control circuit through the interrupt control module, wherein: The interrupt control module is used to enable the Ethernet integrated chip to trigger the interrupt service routine of the control circuit through the MAC module or the PHY module when preset data conditions are met.

[0011] As an optional implementation, in the first aspect of this utility model, the multifunctional circuit further includes a filtering circuit, which comprises a VDD power supply filtering module and a VCC filtering module. The VDD power supply filtering module and the VCC filtering module are respectively electrically connected to the Ethernet integrated chip, wherein: The VDD power filtering module is used to filter the digital signal power voltage supplied to the Ethernet integrated chip. The VCC filtering module is used to filter the analog signal power supply voltage provided to the Ethernet integrated chip.

[0012] As an optional implementation, in the first aspect of this utility model, the interface circuit includes a network transformer module and an interface module, wherein: The network transformer module is used to realize signal coupling between the MAC module or the PHY module and the interface module.

[0013] As an optional implementation, in the first aspect of this utility model, the test circuit further includes a power circuit, a display circuit, and a function key circuit; The power circuit is electrically connected to the control circuit and the multi-functional control circuit, and is used to supply power to the test circuit. The display circuit is electrically connected to the control circuit and is used to display the data output by the control circuit. The function key circuit is electrically connected to the control circuit and is used for user touch control to enable the PHY module to connect to the interface circuit, or the MAC module to connect to the interface circuit.

[0014] The second aspect of this utility model discloses a network cable tester, which includes a tester body and an analog load circuit as described in any one of the claims disclosed in the first aspect of this utility model, disposed on the tester body.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. The test circuit of the network cable tester provided by this utility model, by setting up an Ethernet integrated chip integrating a MAC module and a PHY module, a control circuit, and an interface circuit, allows the control circuit to switch the interface circuit between the MAC module and the PHY module, thereby enabling the test circuit to simultaneously possess communication and length measurement functions. By fully utilizing the independent monolithic integration of the MAC module and the PHY module, the hardware interface and hardware wiring can be simplified. Furthermore, there is no need for an additional timing calibration circuit, thus reducing data transmission delay or packet loss, improving synchronization compatibility. In addition, reduced resource consumption allows the Ethernet integrated chip to adapt to a wider range of MCU resources, increasing the flexibility of circuit design, reducing material costs and PCB area, and ultimately making the test circuit suitable for small embedded devices, improving its applicability.

[0016] 2. The network cable tester provided by this utility model, by applying a test circuit that includes a highly integrated Ethernet chip, enables the network cable tester to simultaneously have communication and length measurement functions, and has low production costs and high synchronous compatibility. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a test circuit disclosed in an embodiment of this utility model; Figure 2 This is a schematic diagram of the structure of a multifunctional circuit disclosed in an embodiment of this utility model; Figure 3 This is a schematic diagram of the structure of a control circuit disclosed in an embodiment of this utility model; Figure 4 This is a schematic diagram of the structure of a network transformer and RJ45 interface module disclosed in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an LED indicator module disclosed in an embodiment of this utility model; Figure 6 This is a schematic diagram of the structure of a display driver module disclosed in an embodiment of this utility model; Figure 7 This is a schematic diagram of the structure of a display screen backlight module disclosed in an embodiment of this utility model; Figure 8 This is a schematic diagram of the structure of a function key circuit disclosed in an embodiment of this utility model; Figure 9 This is a schematic diagram of the structure of a power detection module disclosed in an embodiment of this utility model; Figure 10 This is a schematic diagram of the structure of a power management module disclosed in an embodiment of this utility model; Figure 11 This is a schematic diagram of the structure of a charging module and a TYPE-C charging interface disclosed in an embodiment of this utility model; Figure 12 This is a schematic diagram of the structure of a power control module disclosed in an embodiment of this utility model; Figure 13 This is a schematic diagram of the structure of an interface insertion detection module disclosed in an embodiment of this utility model; Figure 14This is a schematic diagram of another test circuit disclosed in an embodiment of the present utility model; Figure 15 This is a schematic diagram of a process for measuring the length of a network cable, as disclosed in an embodiment of this utility model. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or end that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or ends.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] This utility model discloses a network cable tester and its test circuit. The test circuit of the provided network cable tester integrates an Ethernet integrated chip with a MAC module and a PHY module, a control circuit, and an interface circuit. The control circuit can control the interface circuit to switch between communication with the MAC module and the PHY module, thereby enabling the test circuit to simultaneously perform communication and length measurement functions. By fully utilizing the independent monolithic integration of the MAC module and the PHY module, the hardware interface and hardware wiring can be simplified. At the same time, there is no need to set up an additional timing calibration circuit, thereby reducing data transmission delay or packet loss and improving synchronization compatibility. In addition, the resource consumption is reduced, allowing the Ethernet integrated chip to be adapted to a wider range of MCU resources, improving the flexibility of circuit design, reducing material costs and PCB area, and thus making the test circuit suitable for small embedded devices, improving applicability. The provided network cable tester, by using a test circuit with a highly integrated Ethernet chip, enables the network cable tester to simultaneously perform communication and length measurement functions, with low production cost and high synchronization compatibility.

[0023] The following combination Figure 1-14 This invention relates to a network cable tester and its test circuit, which will be described in detail below.

[0024] Example This utility model discloses a network cable tester, which includes a tester body and a test circuit. The structure of the tester body is consistent with existing technology and therefore will not be described in detail.

[0025] In one embodiment, the network cable tester is used to detect the length of the network cable and can also perform Internet data processing. In other embodiments, the network cable tester can also be used to test the physical length of other communication cables, such as telephone lines. However, in this case, the Internet data processing function of the network cable tester will be limited due to the different types of cables.

[0026] In one embodiment, optionally, such as Figure 1 As shown, the test circuit includes a multi-functional circuit, a control circuit, and an interface circuit. The multi-functional circuit includes an Ethernet integrated chip, which integrates a PHY module and a MAC module. The PHY module implements the PHY function, i.e., the network cable length measurement function, and the MAC module implements the MAC function, i.e., the communication function. The interface circuit is used to connect to the network cable, which can be the network cable to be measured or a network cable used for internet data processing. The Ethernet integrated chip is electrically connected to the interface circuit. The control circuit is electrically connected to the multi-functional circuit and is used to control the conduction of the PHY module and the interface circuit, or the conduction of the MAC module and the interface circuit.

[0027] As can be seen, the test circuit provided by this utility model, by setting up an Ethernet integrated chip integrating a MAC module and a PHY module, a control circuit, and an interface circuit, allows the control circuit to control the interface circuit to switch between communication with the MAC module and the PHY module, thereby enabling the test circuit to simultaneously possess communication and length measurement functions. By fully utilizing the independent monolithic integration of the MAC module and the PHY module, the hardware interface and hardware wiring can be simplified. At the same time, there is no need to set up an additional timing calibration circuit, thereby reducing data transmission delay or packet loss, improving synchronization compatibility, reducing resource consumption, allowing the Ethernet integrated chip to adapt to a wider range of MCU resources, improving circuit design flexibility, reducing material costs and PCB area, and thus making the test circuit suitable for small embedded devices, improving its applicability.

[0028] Optionally, the Ethernet integrated chip can be as follows: Figure 2 In one embodiment, chip U3 is a DM9000A. In other embodiments, chip U3 can also be a DM9051A. The DM9000A supports MII / RMII interfaces and has the same MAC / PHY integration as the DM9051A, but requires additional network transformer configuration. It is suitable for industrial scenarios with higher requirements for transmission stability.

[0029] In this invention, optionally, the Ethernet integrated chip also integrates a communication interface module. The Ethernet integrated chip is electrically connected to the control circuit via the communication interface module, wherein: The communication interface module is used to enable the control circuit to activate the MAC module or PHY module of the Ethernet integrated chip, so as to switch between MAC function and PHY function.

[0030] Optionally, the communication interface module includes an SPI interface module or an I2C bus interface. The SPI interface module consists of a chip select pin, a serial clock pin, a master transmit / slave receive pin, a master receive / slave transmit pin, and resistors connected in series with each pin. Figure 2As shown, the chip select pin, serial clock pin, master transmit / slave receive pin, and master receive / slave transmit pin of the SPI interface module are MCU_DM_CSN, MCU_DM_SCK, MCU_DM_MOSI, and MCU_DM_MISO, respectively. For each pin, the series resistors can be R9, R8, R11, and R10. It should be noted that the resistance value of each series resistor can be 0. The SPI interface module is used in high-speed, full-duplex, real-time applications requiring independent communication between multiple devices. Specifically, it is used for high-speed data frame transmission (such as Ethernet and CAN FD), multi-MAC device expansion, high-speed PHY parameter configuration (such as 10G PHY), and real-time status feedback. The I2C bus interface specifically includes two lines, SDA / SCL, connecting the control chip U12 and the Ethernet integrated chip U3. Slave devices are distinguished by address codes, saving pin count (e.g., saving two GPIOs). Applications include low pin occupancy, bus simplification, low power consumption, and high reliability (ACK mechanism). Specifically, it's suitable for low-power scenarios (e.g., battery-powered terminals), low transmission rates (e.g., less than 3.4MHz), small data volume configurations (e.g., MAC address settings in 10M Ethernet scenarios), situations with limited pin resources, multiple devices sharing a line (e.g., multiple PHY pins), and low-cost hardware designs. Furthermore, when the control chip U12 (see...) Figure 3 When using an I2C interface module, i.e. without a hardware SPI module, the CSN / SCK / MOSI / MISO timings are simulated by ordinary GPIO software, without the need for dedicated hardware resources, and the interrupt priority is optimized to reduce data loss due to high CPU utilization.

[0031] In one embodiment, the control circuit can be composed of Figure 3 The system consists of a control chip U12 and its peripheral modules. The peripheral modules include an RC reset module, an MCU power supply filter module, and a clock oscillation module. The RC reset module, consisting of a series-connected resistor R5 and capacitor C4 (which also serves as a reset button), generates a reset signal upon power-up via RC charging and discharging, or is manually triggered by the button, restoring the control chip U12 to its initial state. The MCU power supply filter module, consisting of three capacitors C7, C8, and C9 connected in parallel between the 3V3 power supply and ground, filters out high-frequency noise and ripple in the power supply, providing a stable and clean power supply voltage for the control chip U12. The clock oscillation module, consisting of a crystal oscillator Y2 and two load capacitors C52 and C53, provides a stable clock signal to the control chip U12, ensuring the synchronous operation of the internal logic and peripherals of the control chip U12.

[0032] Optionally, the multi-functional circuit also includes a reset module, through which the Ethernet integrated chip is electrically connected to the control circuit, wherein: The reset module is used to reset the status of the control circuit when switching between the length measurement function and the communication function of the Ethernet integrated chip.

[0033] Optionally, the reset module can be as follows: Figure 2 The diagram shows an MCU reset module and a chip reset module, with the control circuit, MCU reset module, chip reset module, and Ethernet integrated chip electrically connected in sequence. The MCU reset module resets the state of the control circuit, and the chip reset module resets the state of the Ethernet integrated chip. Specifically, the MCU reset module consists of resistor R12, and the chip reset module consists of resistor R25 and capacitor C21 connected in parallel. Specifically, the Ethernet integrated chip U3 is electrically connected to the control circuit via the reset module through pin RSTB. Figure 3 The RSTB pin of the control chip U12 shown is shown.

[0034] Specifically, when it is necessary to switch the function of the Ethernet integrated chip U3 from PHY function to MAC function, or from MAC function to PHY function, the function can be switched by controlling the Ethernet integrated chip U3 through the reset module via the control chip U12, so as to make the function switch flexible, simplify the circuit design, and reduce costs.

[0035] Optionally, the Ethernet integrated chip also integrates an interrupt control module, wherein the Ethernet integrated chip is electrically connected to the control circuit through the interrupt control module, wherein: The interrupt control module is used to enable the Ethernet integrated chip to trigger the interrupt service routine of the control circuit through the MAC module or PHY module when preset data conditions are met.

[0036] Optionally, the interrupt control module can be as follows: Figure 2 The resistor R13 shown is used to connect the Ethernet integrated chip U3 to the control circuit via the interrupt pin MCU_DM_INT. Figure 3 The pin shown is MCU_DM_INT of the control chip.

[0037] Specifically, during length measurement or internet access, when the Ethernet integrated chip meets one or more preset data conditions such as data reception completion, transmit buffer empty, or link abnormality, the interrupt service routine of the control circuit can be triggered through the MAC module or PHY module. More specifically, during length measurement, if the PHY module outputs processed digital data and simultaneously marks "reception complete" through the status register, an interrupt can be triggered to notify the external device to read the data if the interrupt function is configured. During internet access, after the encapsulated frame is completely transmitted, the MAC module triggers an interrupt through the MCU_DM_INT pin, the control chip U12 pulls the MCU_DM_CSN level low, and then reads the MAC status register through MCU_DM_MISO to confirm successful data transmission. Alternatively, during data reception, if frame parsing and verification both pass, the MAC module temporarily stores the valid data in the receive buffer and triggers an interrupt through the MCU_DM_INT pin to notify the control chip to read the data. This interrupt mechanism significantly improves the efficiency, real-time performance, and resource utilization of the measurement line when implementing MAC and PHY functions.

[0038] Optionally, the multifunctional circuit also includes a filter circuit, which is electrically connected to the Ethernet integrated chip. The filter circuit is used to filter the power supply voltage provided to the Ethernet integrated chip.

[0039] Optionally, the filter circuit may include, for example: Figure 2 The diagram shows a VDD power supply filter module and a VCC filter module. There are two VDD power supply filter modules: one consisting of two capacitors, C4 and C25, connected in parallel; and the other consisting of two capacitors, C8 and C36, connected in parallel. The Ethernet integrated chip U3 is electrically connected to the VDD power supply (e.g., DM_3.3V) via pin DM_3V3, and is used to filter the digital signal power supply voltage provided to the Ethernet integrated chip U3. The VCC filter module consists of inductor L9 and capacitor C27, both electrically connected to pin VCC3 of the Ethernet integrated chip U3, and filters the analog signal power supply voltage provided to the Ethernet integrated chip U3. In this way, by filtering the power supply voltage, a stable and clean power supply voltage is provided to the Ethernet integrated chip U3, filtering out various interference signals.

[0040] Optionally, the interface circuit includes a network transformer module and an interface module, wherein: The network transformer module is electrically connected to the Ethernet integrated chip and the interface module. The network transformer module is used to realize signal coupling between the MAC module or PHY module and the interface module.

[0041] Optionally, the network transformer module includes a network transformer, and the interface module includes an RJ45 interface module. Optionally, the network transformer can be as follows: Figure 4 The circuit consists of coil XT1, capacitor C11, and capacitor C12. Its receive pins RX+ / RX- and transmit pins TX+ / TX- are electrically connected to the corresponding input interfaces RX+ / RX- and output interfaces TX+ / TX- of the Ethernet integrated chip U3. Optionally, the RJ45 interface module can be configured as follows: Figure 4 The RJ2 configuration shown includes an RJ45 interface module that is electrically connected to the network transformer via interfaces J1-J3 and J6, and pins 10, 9, 8, and 7. Optionally, the RJ45 interface module may further include capacitors C1 and C2, and resistor R50. One end of capacitor C1 is grounded, and the other end is electrically connected to interfaces J7 and J8 of the RJ2. One end of capacitor C2 is grounded, and the other end is electrically connected to interfaces J4 and J5 of the RJ2. One end of resistor R50 is grounded, and the other end is electrically connected to interface JG of the RJ2.

[0042] It should be noted that a network transformer module is optional. For example, if an Ethernet integrated chip such as the DM9051A is used, its input / output interfaces are directly electrically connected to the interface module. If a different Ethernet integrated chip, such as the DM9000A instead of the DM9051A, or in industrial scenarios with higher requirements for transmission stability, an additional network transformer module is necessary to improve data transmission stability. Specifically, the interface type (SPI interface module or I2C bus interface) or chip model (such as DM9000A or DM9051A) can be adjusted to adapt to different hardware, improving the circuit's applicability.

[0043] Optionally, the multifunctional circuit may also include an LED indicator module, wherein the LED indicator module may specifically be as follows: Figure 5 As shown, it specifically consists of a first light-emitting module, a second light-emitting module, and a third light-emitting module. The first light-emitting module consists of a first resistor and a first light-emitting diode connected in series; the second light-emitting module consists of a second resistor and a second light-emitting diode connected in series; and the third light-emitting module consists of a third resistor and a third light-emitting diode connected in series. The number of first, second, and third resistors is not limited and can be one in each module. Figure 5 As shown, the first resistor can be resistor R2, the second resistor can be resistor R3, and the third resistor can be resistor R4. In other embodiments, other numbers may be used. For other numbers of resistors, they can be connected in series or in parallel, depending on specific requirements. The number of the first, second, and third LEDs is not limited; it can be one, such as... Figure 5As shown, the first light-emitting diode can be LED1, the second light-emitting diode can be LED2, and the third light-emitting diode can be LED3. In other embodiments, other numbers may also be used. For other numbers of light-emitting diodes, the diodes can be connected in series or in parallel, depending on specific requirements. Specifically, for the case where both the resistor and the light-emitting diode are one, combined with... Figure 2 One end of resistor R2 is electrically connected to the positive terminal of LED2, one end of resistor R3 is electrically connected to the positive terminal of LED3, and one end of resistor R4 is electrically connected to the positive terminal of LED1. The negative terminals of LED1, LED2, and LED3 are electrically connected to the F_LED, L_LED, and SP_LED pins of the Ethernet integrated chip U3, respectively. The other ends of resistors R2, R3, and R4 are all electrically connected to the power supply. During MAC or PHY functions, when data is being transmitted, the Ethernet integrated chip U3 controls the LED indicator module to flash, allowing the user to intuitively understand that data transmission is in progress. Alternatively, when an external device, such as a switch, is connected to the Ethernet integrated chip U3, the chip controls the LED indicator module to illuminate or turn off synchronously with the LEDs on the external device, allowing the user to intuitively understand the switch's operating status. It should be noted that the number of LED indicator modules can be as follows: Figure 5 The three groups shown can be replaced by one, two, or four groups in other embodiments, and the specific number can be set according to the requirements.

[0044] In this utility model, the specific process of switching between communication and length measurement functions for the PHY and MAC modules integrated in the Ethernet integrated chip is described below in conjunction with... Figures 2-4 , Figure 15 As shown, the specific explanation is as follows: For the PHY module, when switching to PHY function is required, if an RJ45 interface module connected to a cable / network cable is detected, it is initialized first. Specifically: the control chip U12 pulls the RSTB pin of the Ethernet integrated chip U3's reset module low for a first preset duration, such as 15ms. The PHY module resets along with the Ethernet integrated chip U3 and enters the initial state. The internal encoding / decoding module and clock module are restored to their default configurations, and the status register is initialized to "standby mode". The control chip U12 pulls the chip select pin MCU_DM_CS low, and then sends a command to the PHY module's "mode selection register" through the master transmit / slave receive pin MCU_DM_MOSI to activate the PHY module separately. At this time, the MAC module enters sleep mode to avoid resource conflicts. The control chip U12 sends configuration commands to the PHY module through the master transmit / slave receive pin MCU_DM_MOSI, including: configuring the transmission rate to the "rate control register"; configuring the duplex mode to the "duplex control register"; and configuring the encoding mode to the "encoding mode register". Afterwards, the control chip U12 reads the "Link Status Register" of the PHY module through the master-slave pin MCU_DM_MISO. If the "PHY Ready Bit" is set to 1 and there is no error flag, the PHY module initialization is complete, and the Ethernet integrated chip U3 enters the physical layer test state. Next, data transmission begins. Specifically, the PHY module receives parallel digital data from external devices, such as parallel digital data from a switch, and encodes and converts it to obtain a differential analog signal. This differential analog signal is then transmitted to the Ethernet twisted pair via the network transformer through the PHY module's output interface TX+ / TX-. During transmission, the PHY module monitors the signal output status; if a drive abnormality occurs, it flags the status register. After the differential analog signal is completely transmitted, the PHY module notifies the status register via an internal signal. The control chip U12 can read this register through the master-slave pin MCU_DM_MISO to confirm the transmission result and complete the data transmission. Next, data reception proceeds. Specifically, the PHY module receives the differential analog signal from the Ethernet twisted-pair cable via the input interfaces RX+ / RX- through a network transformer. Optionally, the validity of the differential analog signal is first detected and noise is filtered out. Then, the differential analog signal is converted into a digital signal by an internal decoder, and the length of the Ethernet twisted-pair cable is measured based on the digital signal. During the Ethernet twisted-pair cable length measurement process, if a fault exists in the twisted-pair cable, the fault location can be determined simultaneously based on the digital signal. The processed digital data, including the length of the Ethernet twisted-pair cable and further, the fault location, is then output to the external device. Simultaneously, a "reception complete" flag is displayed in the status register. If an interrupt function is configured, an interrupt can be triggered to notify the external device to read the data.

[0045] For the MAC module, when switching to MAC function is required, such as when a communication request is detected during length measurement, it is first initialized. Specifically: the control chip U12 pulls the RSTB pin of the Ethernet integrated chip U3's reset module low for a first preset duration, such as 10ms, and then pulls the RSTB pin high. The MAC module resets along with the Ethernet integrated chip U3 and enters standby mode, restoring its internal registers to default values. Immediately afterwards, the control chip U12 pulls the MCU_DM_CSN pin of the Ethernet integrated chip U3 low, and then sends a command to the MAC module's mode control register via the master transmit / slave receive pin MCU_DM_MOSI to activate the MAC module separately. At this time, the unassociated PHY module automatically enters low-power sleep mode. The control chip U12 then sends configuration commands to the MAC module via the master-slave transmit / slave receive pin MCU_DM_MOSI. These commands include: writing network layer parameters such as the local IP address, subnet mask, and gateway to the "IP Configuration Related Register"; enabling preamble, automatic SFD addition, and automatic 32-bit CRC checksum generation to the "Frame Processing Register"; and configuring the start addresses of the transmit and receive buffers to the "Buffer Register." The control chip U12 reads the MAC module's "Ready Status Register" via the master-slave transmit / slave receive pin MCU_DM_MISO. If the "MAC Ready Bit" in the register is set to 1, the MAC module initialization is complete. If not, the control chip U12 re-executes the configuration commands sent to the MAC module via the master-slave transmit / slave receive pin MCU_DM_MOSI until the MAC module initialization is complete. After initialization, data transmission proceeds. Specifically, the control chip U12 pulls the chip select pin MCU_DM_CSN low and writes the raw data to be transmitted into the MAC module's transmit buffer according to the SPI interface timing via the master-slave transmit / slave receive pin MCU_DM_MOSI to achieve data writing. Next, the MAC module reads the raw data from the transmit buffer, completes frame encapsulation according to the IEEE 802.3 standard, adds a preamble and SFD to the data header, and automatically generates a CRC checksum at the data tail. If the data length is less than the minimum frame length, padding bytes are automatically added. At this time, the control chip U12 sends a trigger command to the MAC module's "transmit control register" through the master transmit / slave receive pin MCU_DM_MOSI. The MAC module begins to transmit the encapsulated frame data outward through the shared output interface TX+ / TX- via the network cable transformer, such as transmitting temperature and humidity sensor data from the network cable to the router, and then uploading it to the gateway. During the transmission process, the MAC module monitors the transmission status in real time. If an abnormality such as buffer overflow occurs, it will mark the corresponding bit in the status register.After the encapsulated frame is completely transmitted, the MAC module triggers an interrupt via the MCU_DM_INT interrupt pin. The control chip U12 pulls the MCU_DM_CSN chip select pin low and then reads the data from the MAC module's status register via the MCU_DM_MISO master transmit / receive pin to confirm successful data transmission. After successful data transmission, data reception begins. Specifically: after initialization, the MAC module continuously monitors the receive buffer, waiting for incoming digital frame data. When a digital frame enters the receive buffer, the MAC module first performs frame header parsing, extracting the preamble and verifying its validity; then it performs a CRC check, discarding the frame if the check fails; simultaneously, it filters invalid frames with mismatched MAC addresses. If both frame parsing and verification pass, the MAC module temporarily stores the valid data in the receive buffer and triggers an interrupt via the MCU_DM_INT interrupt pin, notifying the control chip U12 to read the data. After receiving the notification, the control chip U12 pulls the chip select pin MCU_DM_CSN low and reads the valid data in the receive buffer according to the timing of the SPI interface module through the master transmit / receive pin MCU_DM_MISO. After the data reading is completed, the MAC module automatically clears the receive buffer and prepares to receive the next frame. This process is repeated until the communication ends.

[0046] In an optional embodiment, the test circuit may further include a display circuit, wherein the display circuit includes a display driver module, wherein the display driver module is electrically connected to the control circuit and is used to display the length measurement result and / or fault location of the Ethernet twisted pair.

[0047] Optionally, the display driver module can be as follows: Figure 6 As shown, it specifically consists of a liquid crystal display chip CN1, such as the ST7567 LCM, and its peripheral electronic components, wherein, combined with Figure 3 The liquid crystal display chip is electrically connected to the control chip U12 via transmission pins BD0~BD7, reset pin RESET, data / command selection pin A0, read / write control pin RW, and enable pin E. For details regarding the specific types of peripheral electronic components of the liquid crystal display chip and their corresponding electrical connections, please refer to [link to relevant documentation]. Figure 6 This will not be elaborated upon here.

[0048] Furthermore, the display circuit also includes a display backlight module, wherein the display backlight module can specifically be as follows: Figure 7 As shown, it specifically consists of resistors R85-R87, transistor Q9, and interface P2, wherein, combined with Figure 3One end of resistor R85 is electrically connected to the control chip U12 via pin CPU_BL, and the other end is electrically connected to resistor R86 and the base of transistor Q9. The collector of transistor Q9 is electrically connected to one end of resistor R87 via interface P2. The other end of resistor R87 is electrically connected to the power supply, such as a 3.3V power supply. The emitter of transistor Q9 and the other end of resistor R86 are grounded.

[0049] Specifically, the control chip U12 sends a reset signal via the RESET pin to initialize the LCD chip, and uses the A0 pin to distinguish whether the transmitted data is a command (e.g., display on, contrast adjustment) or data (e.g., length measurement result). The control chip U12 sends the character / graphic data to be displayed, such as a length of 5m, to the LCD chip via the BD0~BD7 parallel bus. The LCD chip converts this data into pixel drive signals, controlling the alignment of the liquid crystal molecules to achieve pattern display. The control chip U12 controls the backlight switch via the CPU_BL pin and adjusts the backlight brightness using a voltage divider circuit composed of resistors R85 and R86 to adapt to different ambient light conditions. By providing a display driver module, the results of network cable length measurement and internet access can be fed back in real time, allowing users to intuitively view the cable length and test status. In case of faults, no external equipment is required, improving operational convenience. Furthermore, by adopting the ST7567 to support low-power mode, and in conjunction with the on / off control of the display backlight module, it ensures that users can clearly read information such as the network cable length and device status displayed on the screen under different ambient light conditions, such as strong light and weak light, thereby improving the ease of use and readability of the device, and turning off the backlight when there is no operation to extend the lithium battery life.

[0050] In another alternative embodiment, the test circuit may further include a function key circuit, wherein the function key circuit is electrically connected to the control circuit and is used for user touch to control the Ethernet integrated chip to switch between PHY and MAC functions via the control circuit.

[0051] Optionally, the function key circuit consists of at least one function key module. The number of function key modules can be one, two, or other numbers, determined by the specific implementation requirements. Each function key module consists of a function resistor unit and a key connected in series. The function resistor unit can contain one resistor, or other numbers in other embodiments, depending on the requirements. The following description uses four function key modules, each with a function resistor unit consisting of one resistor. Figure 8As shown, the first function key module consists of K2 and resistor R24 ​​connected in series; the second function key module consists of K3 and resistor R27 connected in series; the third function key module consists of K4 and resistor R30 connected in series; and the fourth function key module consists of K5 and resistor R31 connected in series. The other ends of keys K2-K5 are grounded. The other ends of resistors R24, R27, R30, and R31 are each electrically connected to a power supply, such as a 3.3V power supply. Figure 3 Buttons K2-K5 are electrically connected to the control chip U12 via button pins KEY2-KEY5 in sequence.

[0052] Specifically, when a user presses a button, the voltage level of any of the button pins KEY2-KEY5 changes, such as from high to low or from low to high, generating a voltage level transition signal. The control chip U12 identifies the button action by detecting the voltage level transition and interprets the button function, such as switching between PHY and MAC functions or resetting. Specifically, different functions can be triggered based on the duration of the button press or the number of times it is pressed within a short period. For example, a short press switches the PHY function for length measurement, while a long press switches the MAC function for internet access. This provides buttons for user touch control, improving the flexibility of human-machine interaction and the ease of use of the tester; and by achieving button detection through direct connection of the button pins, no additional dedicated chip is required, simplifying circuit design and reducing costs.

[0053] In yet another alternative embodiment, the test circuit may further include a power circuit, which is electrically connected to a control circuit and a multi-functional circuit, the power circuit being used to power the test circuit.

[0054] In one optional embodiment, the power circuit includes a lithium battery, a power management module, and a power detection module. Further, it may also include a charging module, wherein: The lithium battery, power management module, and power detection module are electrically connected in sequence. The power detection module and power management module are electrically connected to the control circuit, and the power management module is electrically connected to the multi-function circuit. The charging module is electrically connected to the lithium battery and the TYPE-C charging interface. Furthermore, the power circuit also includes a power control module. This power control module is electrically connected to the control circuit, lithium battery, power detection module, and power management module.

[0055] Optionally, the power detection module can be as follows: Figure 9 As shown, it specifically consists of transistor Q6, resistors R75, R76, R82, R7, R15, MOSFET Q2 (such as LP2301), and capacitor C10. The power management module can be configured as follows: Figure 10 As shown, it is specifically composed of a power management chip IC5 (such as TPS63802) and peripheral electronic components; the charging module can be as follows: Figure 11 As shown, it is specifically composed of a charging chip IC1 (such as TC4056A) and peripheral electronic components. The TYPE-C charging interface can be used as follows: Figure 11 As shown, it specifically consists of an interface chip USB1 (such as SMT TYPE-C 16P) and peripheral electronic components. The power control module can be as follows: Figure 12 As shown, it is specifically composed of button K1, diode D2, diode D3, transistor Q1, transistor Q12, MOSFET Q13, MOSFET Q23 and their corresponding pull-up or pull-down resistors, specifically resistors R22, R41, R42, R39 and R73.

[0056] Furthermore, the power module may also include an interface insertion detection module; optionally, the interface insertion detection module may be as follows: Figure 13 As shown, it specifically consists of two resistors, R16 and R17, connected in series. Figure 3 Both are electrically connected to the control chip U12 via the MCU_USB_DET pin. The other end of the resistor R16 is electrically connected to the TYPE-C charging interface and the charging module via the USB_5V pin, which is used to detect whether a charging interface is inserted.

[0057] Specifically, in combination Figures 2-13 Resistor R15 is electrically connected to control chip U12 via pin MCU_BAT_ADC. Resistor R82, the source of MOSFET Q2, the BAT pin of charging chip IC1, and the source of MOSFET Q23 are all electrically connected to the lithium battery. One end of resistor R75, pin PG of power management chip IC5, and pins VIN / EN of power management chip IC5 are all electrically connected to the source of MOSFET Q13 via POWER_IN. The base of transistor Q12 is electrically connected to control chip U12 via pin POWER_CTRL via resistor R41. The anode of diode D3 is electrically connected to control chip U12 via pin KEY1. Pin GND of interface chip USB1, pin VBUS, pin VCC of charging chip IC1, and pin CE are all electrically connected to the gate of MOSFET Q23 and the anode of diode D2 via resistor R32. For details on the specific types of peripheral electronic components of power management chip IC5 and their corresponding electrical connections, please refer to [link to relevant documentation]. Figure 6 For details on the specific types of peripheral electronic components of charging chip IC1 and their corresponding electrical connections, please refer to [link / reference needed]. Figure 6 Details will not be elaborated here; for the specific types of peripheral electronic components of the USB1 interface chip and their corresponding electrical connections, please refer to [link to relevant documentation]. Figure 6 The lithium battery is an existing type of battery and will not be discussed further here.

[0058] Specifically, the power management module uses the power management chip IC5 to convert the lithium battery voltage into a stable voltage, such as 3.3V, required by the test circuit. This provides power to modules such as the control chip U12, the Ethernet integrated chip U3, and the display screen, ensuring a precise and stable 3.3V voltage for each module. This prevents device crashes or data errors caused by voltage fluctuations and improves system stability. Furthermore, when charging via an external TYPE-C charging port, the module automatically switches to external power to supply power to modules such as the control chip U12 and the Ethernet integrated chip U3, as well as to charge the lithium battery. Once charging is complete, the module reverts to battery power, achieving seamless switching.

[0059] Specifically, during length measurement or internet browsing, lithium batteries (see details) Figure 11 The BAT1 voltage is divided by the series resistors R7 and R15 in the power detection circuit. The resulting voltage is then input to the control chip U12 through the MCU_BAT_ADC pin. The control chip U12 converts the analog voltage signal into a digital value through the ADC module. It calculates the current voltage of the lithium battery based on the voltage division coefficient and converts it into the remaining power percentage according to the voltage-power relationship. This percentage is displayed to the user through the display driver module, such as "Power: 75%", so that the user can intuitively understand the remaining power of the lithium battery. This avoids the impact of sudden power outages on the test line and improves the reliability of use. When the voltage is detected to be lower than the threshold, a low power alarm or automatic shutdown is triggered to prevent the lithium battery from being damaged by over-discharge and extend the battery life.

[0060] Specifically, during length measurement or internet access, the charging module employs a constant current-constant voltage charging strategy, converting the 5V input from the TYPE-C charging interface into a suitable charging current and voltage for the lithium battery. This charges the lithium battery, enabling it to power modules such as the control chip U12, the Ethernet integrated chip U3, and the display screen, thus facilitating the switching between length measurement and internet access. Furthermore, the TYPE-C charging interface uses a configured CC pin for reversible insertion, eliminating the need for user orientation and providing convenient blind insertion, thus improving the user experience. The CC pin also negotiates protocols with the charging module, such as USB 2.0 / 3.0, to select the appropriate charging protocol for the lithium battery, shortening charging time and improving charging stability, ensuring sufficient power for the switching between length measurement and internet access.

[0061] The cable detector and other related circuit structures described above are merely illustrative. The electronic components described as separate parts may or may not be physically separate, and the components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0062] Finally, it should be noted that the network cable tester and its test circuit disclosed in this utility model embodiment are merely preferred embodiments of this utility model, and are only used to illustrate the technical solutions of this utility model, not to limit it; although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of this utility model.

Claims

1. A test circuit for a network cable tester, characterized in that, The test circuit includes a multi-functional circuit, a control circuit, and an interface circuit, wherein: The multifunctional circuit includes an Ethernet integrated chip, on which a PHY module and a MAC module are integrated; The interface circuit is electrically connected to the multifunctional circuit, and the interface circuit is used to connect a network cable. The control circuit is electrically connected to the multifunctional circuit, and the control circuit is used to control the PHY module to be connected to the interface circuit, or the MAC module to be connected to the interface circuit.

2. The test circuit according to claim 1, characterized in that, The Ethernet integrated chip also integrates a communication interface module; The Ethernet integrated chip is electrically connected to the control circuit through the communication interface module, wherein: The communication interface module is used by the control circuit to activate the MAC module or PHY module of the Ethernet integrated chip.

3. The test circuit according to claim 2, characterized in that, The communication interface module includes an SPI interface module or an I2C bus interface. The SPI interface module consists of a chip select pin, a serial clock pin, a master transmit / slave receive pin, a master receive / slave transmit pin, and resistors connected in series with each pin.

4. The test circuit according to any one of claims 1-3, characterized in that, The multifunctional circuit also includes a reset module: The Ethernet integrated chip is electrically connected to the control circuit through the reset module, wherein: The reset module is used to reset the state of the Ethernet integrated chip when the control circuit switches between the length measurement function and the communication function.

5. The test circuit according to claim 4, characterized in that, The reset module includes an MCU reset module and a chip reset module, wherein: The control circuit, the MCU reset module, the chip reset module, and the Ethernet integrated chip are electrically connected in sequence. The MCU reset module is used to reset the state of the control circuit, and the chip reset module is used to reset the state of the Ethernet integrated chip.

6. The test circuit according to any one of claims 1-3, characterized in that, The Ethernet integrated chip also integrates an interrupt control module; The Ethernet integrated chip is electrically connected to the control circuit through the interrupt control module, wherein: The interrupt control module is used to enable the Ethernet integrated chip to trigger the interrupt service routine of the control circuit through the MAC module or the PHY module when preset data conditions are met.

7. The test circuit according to any one of claims 1-3, characterized in that, The multifunctional circuit further includes a filtering circuit, which comprises a VDD power filter module and a VCC filter module. The VDD power filter module and the VCC filter module are electrically connected to the Ethernet integrated chip, respectively. The VDD power filtering module is used to filter the digital signal power voltage supplied to the Ethernet integrated chip. The VCC filtering module is used to filter the analog signal power supply voltage provided to the Ethernet integrated chip.

8. The test circuit according to any one of claims 1-3, characterized in that, The interface circuit includes a network transformer module and an interface module, wherein: The network transformer module is electrically connected to the Ethernet integrated chip and the interface module. The network transformer module is used to realize signal coupling between the MAC module or the PHY module and the interface module.

9. The test circuit according to any one of claims 1-3 and 8, characterized in that, The test circuit also includes a power circuit, a display circuit, and a function key circuit; The power circuit is electrically connected to the control circuit and the multifunctional circuit, and is used to supply power to the test circuit. The display circuit is electrically connected to the control circuit and is used to display the data output by the control circuit. The function key circuit is electrically connected to the control circuit and is used for user touch control to enable the PHY module to connect to the interface circuit, or the MAC module to connect to the interface circuit.

10. A network cable tester, characterized in that, The network cable tester includes a tester body and a test circuit as described in any one of claims 1-9 disposed on the tester body.

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