Circuit board

Abstract

The application relates to the technical field of electronic circuit boards, in particular to a circuit board which comprises a circuit board body, a first filling body and a metallization structure; the circuit board body comprises an external base copper, the circuit board body is provided with a through hole and a blind hole penetrating through the external base copper, and the first filling body is fixed in the blind hole; the metallization structure comprises a first copper-plate electrode layer, a plating layer and a second copper-plate electrode layer; the inner circumferential sidewall of the blind hole is deposited with the first copper-plate electrode layer, and the inner circumferential sidewall of the through hole is deposited with the second copper-plate electrode layer; the external base copper is sequentially and superimposedly deposited with the first copper-plate electrode layer and the second copper-plate electrode layer, and the first copper-plate electrode layer and the second copper-plate electrode layer are further provided with a plating layer, a filling body polishing loss structure and a micro-etching loss structure. The circuit board deposits the plating layer between the first copper-plate electrode layer and the second copper-plate electrode layer, ensures that the second copper-plate electrode layer can be reliably combined with the underlying structure, and effectively avoids delamination and blistering caused by poor combination.

Description

Technical Field

[0001] This application relates to the field of electronic circuit board technology, and in particular to a circuit board. Background Technology

[0002] Currently, after reflow soldering, circuit boards with blind vias and through vias often experience copper blistering, which has a serious negative impact on product reliability.

[0003] Therefore, it is urgent to analyze the causes of this defect and solve the problem of delamination and blistering after reflow of circuit boards with blind and through holes. Utility Model Content

[0004] The purpose of this application is to provide a circuit board that can, to some extent, solve the technical problem of copper blistering on the surface of circuit boards with blind vias and through vias after reflow.

[0005] This application provides a circuit board, including a circuit board body, a first filler, and a metallization structure; The circuit board body includes an outer base copper, and the circuit board body is provided with through holes and blind holes that penetrate the outer base copper, and the first filler is fixed in the blind hole; The metallization structure includes a first copper plating layer, an additional plating layer, and a second copper plating layer. The inner peripheral sidewall of the blind hole is deposited with the first copper plating electrode layer, and the inner peripheral sidewall of the through hole is deposited with the second copper plating electrode layer. The external base copper is sequentially deposited with the first copper plating electrode layer and the second copper plating electrode layer. Between the first copper plating electrode layer and the second copper plating electrode layer, there are also plating layers, filler polishing defect structures and micro-etching defect structures.

[0006] In the above technical solution, the plating layer is further deposited on the surface of the first copper plating electrode layer, and the filler polishing defect structure and the micro-etching defect structure are formed between the plating layer and the second copper plating electrode layer.

[0007] In any of the above technical solutions, the filler polishing defect structure and the micro-etching defect structure are formed between the surface of the first copper plating electrode layer and the plating layer, and the second copper plating electrode layer is deposited on the plating layer.

[0008] In any of the above technical solutions, the total thickness of the first copper plating electrode layer, the filler polishing defect structure, and the micro-etching defect structure is further 3-4µm.

[0009] In any of the above technical solutions, the thickness of the first copper plating electrode layer is further 8-12µm; The thickness of the coating is 5-7µm.

[0010] In any of the above technical solutions, the thickness of the defect in the filler grinding defect structure is further 2-3µm; The defect thickness of the micro-etched defect structure is 3-5µm.

[0011] In any of the above technical solutions, the circuit board body further includes a first layer board assembly, a second layer board assembly, and an insulating board laminated between the first layer board assembly and the second layer board assembly. The outer base copper of the first layer board assembly facing away from the insulating board is the first outer base copper, and the outer base copper of the second layer board assembly facing away from the insulating board is the second outer base copper. The blind hole includes a first blind hole and a second blind hole, the first blind hole penetrating the first layer assembly and the second blind hole penetrating the second layer assembly.

[0012] In any of the above technical solutions, the first layer board assembly further includes a first internal base copper, which is disposed opposite to the first external base copper along the thickness direction of the circuit board body. The circuit board body is also provided with a stepped hole at its edge. The stepped hole penetrates the second layer board assembly and the insulating plate so that the first internal base copper of the first layer board assembly is exposed through the stepped hole. The inner peripheral sidewall of the stepped hole is deposited with the second copper plating electrode layer.

[0013] In any of the above technical solutions, a second filler is further provided in the stepped hole.

[0014] In any of the above technical solutions, the first filler is further defined as a cured resin; The second filler is a Teflon gasket.

[0015] Compared with the prior art, the beneficial effects of this application are as follows: The circuit board provided in this application has a first copper plating electrodeposition layer and a second copper plating electrodeposition layer sequentially deposited on the outer base copper. Between the first and second copper plating electrodeposition layers, there are additional plating layers, filler polishing defects, and micro-etching defects. By depositing an additional plating layer between the first and second copper plating electrodeposition layers, the exposed outer base copper due to defects can be avoided. This prevents the formation of other impurities due to micro-etching of the exposed outer base copper, which could affect the roughening and activation of the board surface during through-hole copper plating. Furthermore, this ensures that the second copper plating electrodeposition layer can reliably bond with its underlying structure, effectively preventing delamination and blistering due to poor bonding. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the circuit board structure provided in an embodiment of this application.

[0018] Figure label: 10-Insulating board; 20-First layer board assembly; 201-First outer base copper; 202-First core board; 203-First inner base copper; 30-Through hole; 401-First blind hole; 402-Second blind hole; 50-Second filler; 60-Stepped hole; 70-Second layer board assembly; 701-Second outer base copper; 702-Second core board; 703-Second inner base copper. Detailed Implementation

[0019] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0020] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0022] An analysis of delamination and bubbling defects in related technologies, from the perspectives of defect location and process flow, revealed that bubbling often occurs between the electroplated copper layer and the base copper in through-holes. In the processing of circuit boards with blind vias and through-holes, a separate mounting process is performed first, followed by a final mounting process. In the separate mounting process, blind vias are first electroplated with copper plating, ensuring that both the base copper and the blind vias receive the copper plating layer. Then, the blind vias are plugged and polished. In the final mounting process, brown plating is applied followed by lamination, micro-etching to remove the brown plating, drilling of through-holes, and finally, copper plating is applied to the through-holes, ensuring that both the base copper and the through-holes receive the copper plating layer.

[0023] Analysis of the defect location and process flow revealed that the base copper was exposed because the electrical layer of the blind via copper plating board was lost during subsequent polishing and micro-etching to remove brown residue. The exposed base copper, after micro-etching, generated other impurities, affecting the roughening and activation of the board surface during through-hole copper plating. This resulted in poor bonding between the electrical layer and the base copper in the through-hole copper plating board, leading to delamination and blistering.

[0024] Based on the above analysis results, see Figure 1 As shown, an embodiment of this application provides a circuit board to solve the problem of delamination and bubbling in circuit boards.

[0025] The circuit board provided in this embodiment includes a circuit board body, a first filler, and a metallized structure.

[0026] The circuit board body has an external base copper, and the circuit board body is provided with a through hole 30 that penetrates the external base copper and a blind hole, with the first filler fixed in the blind hole.

[0027] The metallization structure includes a first copper plating layer, an additional plating layer, and a second copper plating layer.

[0028] The inner peripheral sidewalls of the blind via are deposited with a first copper plating electrodeposition layer. Specifically, blind vias are first fabricated on the circuit board body, and then copper plating electrodeposition is performed on the blind vias, so that the outer base copper and the inner peripheral sidewalls of the blind vias are both deposited with the first copper plating electrodeposition layer. See [link to relevant documentation]. Figure 1 Points A and B in the diagram indicate localized areas of the copper plating electrode layer deposited on the inner peripheral sidewall of the blind via. See [link to diagram]. Figure 1 Points D and E in the diagram indicate local areas of the copper plating electrode layer deposited on the outer base copper substrate.

[0029] After the copper plating process of blind vias is completed, the first filler is filled into the blind via. After filling, the via is polished, which will produce a damaged structure of the filler and cause copper loss.

[0030] Optionally, the first filler is a cured resin, specifically, it is obtained by filling the blind hole with resin and then curing it.

[0031] A second copper plating layer is deposited on the inner peripheral sidewall of the through-hole 30. Since the blind via is filled with the first filler, no further copper plating layer will be deposited on the inner peripheral sidewall of the blind via during the copper plating process. (See also...) Figure 1 The indication at point C indicates that a second copper plating electrode layer is deposited on the inner peripheral sidewall of via 30. Meanwhile, see [reference needed]. Figure 1 Points D and E indicate that a second copper plating electrode layer is deposited on the first copper plating electrode layer of the outer base copper, thereby the outer base copper is sequentially stacked with the first copper plating electrode layer and the second copper plating electrode layer.

[0032] Before machining the through-hole 30, the process includes browning and micro-etching to remove the browning, which results in micro-etching defects that cause copper loss. Consequently, filler grinding defects and micro-etching defects are formed between the first and second copper plating layers. To prevent insufficient adhesion between the first and second copper plating layers due to these defects, an additional plating layer is applied between them.

[0033] Specifically, after the first copper plating electrodeposition is completed, an additional plating layer is deposited, on which filler grinding defect structures and micro-etched defect structures are sequentially formed; or, filler grinding defect structures and micro-etched defect structures are sequentially formed on the first copper plating electrodeposition layer, and then an additional plating layer is deposited. By depositing an additional plating layer between the first and second copper plating electrodeposition layers, the exposed external base copper due to defect structures can be avoided. This prevents the formation of other impurities due to micro-etching of the exposed external base copper, which would affect the roughening and activation of the board surface during copper plating of the vias 30. This ensures that the second copper plating electrodeposition layer can reliably bond with its underlying structure, effectively preventing delamination and blistering due to poor bonding.

[0034] Tests have verified that no blistering was found on the copper surface after three reflow soldering cycles, and no delamination of the plating was found when the external base copper with the metallized structure was etched to a depth of 35-38µm.

[0035] In this embodiment, the thickness of the first copper plating electrode layer is 8-12µm, optionally 8µm, 9µm, 10µm, 11µm, or 12µm. Specifically, the first copper plating electrode layer can be deposited according to the copper plating electrode parameters of 2.4ASD*18min.

[0036] The thickness of the defect in the filler grinding structure is 2-3µm, for example, 2µm or 3µm. Specifically, the filler grinding defect structure can be obtained by grinding with a ceramic brush current of 0.6A, a non-woven brush current of 1.5A, and a linear speed of 2m / min.

[0037] The defect thickness of the micro-etched defect structure is 3-5µm, for example, 3µm, 4µm or 5µm. Specifically, the micro-etched defect structure can be obtained by micro-etching and removing browning at a micro-etching rate of 2-3µm and a de-browning line speed of 2-3m / min.

[0038] The thickness of the plating layer is 5-7µm, for example, 5µm, 6µm, or 7µm. Optionally, the plating layer is deposited according to the electrical parameters of the copper plating board: 2.4ASD*10min. Further, the thickness of the plating layer can be 3-4µm.

[0039] Based on the order in which the plating layer is formed relative to the micro-etched structure, there are two possible implementation schemes. In the first implementation scheme, the plating layer is deposited on the surface of the first copper plating electrode layer, and the filler polishing defect structure and the micro-etched defect structure are formed between the plating layer and the second copper plating electrode layer. That is, the plating layer is formed first, and then the micro-etched structure is formed.

[0040] Alternatively, as a second implementation, the filler grinding defect structure and the micro-etching defect structure are formed between the surface of the first copper plating electrode layer and the plating layer, and the second copper plating electrode layer is deposited on the plating layer, so that the plating layer is deposited after the filler grinding defect structure and the micro-etching defect structure are formed.

[0041] In the second embodiment described above, the total thickness of the first copper plating electrode layer, the filler polishing defect structure, and the micro-etched defect structure is 3-4 µm. Specifically, after forming the filler polishing defect structure and the micro-etched defect structure, a copper surface test is performed. It is necessary to ensure that the total thickness of the first copper plating electrode layer, the filler polishing defect structure, and the micro-etched defect structure meets the requirement of 3-4 µm to avoid the risk of blistering due to excessively thin total thickness.

[0042] In an optional embodiment, the circuit board body includes a first layer board assembly 20, a second layer board assembly 70, and an insulating board 10 laminated between the first layer board assembly 20 and the second layer board assembly 70. The insulating board 10 may be, for example, a PP board.

[0043] The outer base copper of the first layer board assembly 20, which is opposite to the insulating plate 10, is the first outer base copper 201. The first layer board assembly 20 also includes a first inner base copper 203 and a first core board 202. The first inner base copper 203 and the first outer base copper 201 are arranged opposite to each other along the thickness direction of the circuit board body. The first core board 202 is laminated between the first inner base copper 203 and the first outer base copper 201.

[0044] The outer base copper of the second layer board assembly 70, which is opposite to the insulating plate 10, is the second outer base copper 701. The second layer board assembly 70 also includes a second inner base copper 703 and a second core board 702. The second inner base copper 703 and the second outer base copper 701 are arranged opposite each other along the thickness direction of the circuit board body. The second core board 702 is laminated between the second inner base copper 703 and the second outer base copper 701.

[0045] The blind vias include a first blind via 401 and a second blind via 402. The first blind via 401 penetrates the first layer assembly 20, specifically, it penetrates the first outer base copper 201, the first core board 202, and the first inner base copper 203. The second blind via 402 penetrates the second layer assembly 70, specifically, it penetrates the second outer base copper 701, the second core board 702, and the second inner base copper 703. In other words, blind vias, namely the first blind via 401 and the second blind via 402, are provided on both sides of the thickness direction of the circuit board body.

[0046] A stepped hole 60 is also provided at the edge of the circuit board body. The stepped hole 60 penetrates the second layer board assembly 70 and the insulating plate 10 so that the first internal base copper 203 of the first layer board assembly 20 is exposed through the stepped hole 60. The stepped area of ​​the first internal base copper 203 corresponds to the stepped hole 60 and is provided with a plug-in hole, for example. A second copper plating electrode layer is deposited on the inner peripheral sidewall of the stepped hole 60.

[0047] In the processing of the circuit board body, the first and second sub-carding processes are completed separately. In the first sub-carding process, a first blind via 401 is formed on the first layer board assembly 20, a first copper plating electrode is deposited on the first blind via 401 and the first external base copper 201, a first filler is filled into the first blind via 401, and the filler is formed and the defect structure is polished. In the second sub-carding process, a second blind via 402 is formed on the second layer board assembly 70, a first copper plating electrode is deposited on the second blind via 402 and the second external base copper 701, the second blind via 402 is filled with the first filler, and the filler is formed and the defect structure is polished.

[0048] Then, the overall carding process is carried out. In the overall carding process, the insulating board 10 is first machined to prepare the stepped hole 60 structure. After browning, the insulating board 10, the first layer board assembly 20 and the second layer board assembly 70 are laminated and connected to fix the second filler 50. Then, the browning is removed to form a micro-etched defect structure and through holes 30 are drilled. After drilling the through holes 30, the second filler 50 in the stepped hole 60 is removed to prevent the plug-in holes in the stepped hole 60 from bursting. Finally, the second copper plating electrodeposition layer is deposited on the stepped hole 60 and the through hole 30, so that the inner peripheral sidewall of the stepped hole 60 is also deposited with the second copper plating electrodeposition layer.

[0049] Optionally, the second filler 50 is a Teflon gasket.

[0050] The plating deposition step can be performed in the first and second sub-card processes, specifically after depositing the first copper plating electrode and before filling the first filler. Alternatively, the plating deposition step can be performed in the overall card process, specifically after forming the micro-etched defect structure and before drilling the through-hole 30.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model. In addition, those skilled in the art can understand that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments means that they are within the scope of this utility model and form different embodiments. For example, any one of the claimed embodiments can be used in any combination. The information disclosed in this background section is only intended to deepen the understanding of the overall background technology of this utility model, and should not be regarded as an admission or in any form implying that the information constitutes prior art known to those skilled in the art.

Claims

1. A circuit board, characterized in that, Includes the circuit board body, the first filler, and the metallization structure; The circuit board body includes an outer base copper, and the circuit board body is provided with through holes and blind holes that penetrate the outer base copper, and the first filler is fixed in the blind hole; The metallization structure includes a first copper plating layer, an additional plating layer, and a second copper plating layer. The inner peripheral sidewall of the blind hole is deposited with the first copper plating electrode layer, and the inner peripheral sidewall of the through hole is deposited with the second copper plating electrode layer. The external base copper is sequentially deposited with the first copper plating electrode layer and the second copper plating electrode layer. Between the first copper plating electrode layer and the second copper plating electrode layer, there are also plating layers, filler polishing defect structures and micro-etching defect structures.

2. The circuit board according to claim 1, characterized in that, The plating layer is deposited on the surface of the first copper plating electrode layer, and the filler polishing defect structure and the micro-etching defect structure are formed between the plating layer and the second copper plating electrode layer.

3. The circuit board according to claim 1, characterized in that, The filler polishing defect structure and the micro-etching defect structure are formed between the surface of the first copper plating electrode layer and the plating layer, and the second copper plating electrode layer is deposited on the plating layer.

4. The circuit board according to claim 3, characterized in that, The total thickness of the first copper plating electrode layer, the filler polishing defect structure, and the micro-etched defect structure is 3-4µm.

5. The circuit board according to claim 1, characterized in that, The thickness of the first copper plating electrode layer is 8-12µm; The thickness of the coating is 5-7µm.

6. The circuit board according to claim 1, characterized in that, The thickness of the defect in the filler-polished defect structure is 2-3µm; The defect thickness of the micro-etched defect structure is 3-5µm.

7. The circuit board according to claim 1, characterized in that, The circuit board body includes a first layer board assembly, a second layer board assembly, and an insulating board laminated between the first layer board assembly and the second layer board assembly. The outer base copper of the first layer board assembly facing away from the insulating board is the first outer base copper, and the outer base copper of the second layer board assembly facing away from the insulating board is the second outer base copper. The blind hole includes a first blind hole and a second blind hole, the first blind hole penetrating the first layer assembly and the second blind hole penetrating the second layer assembly.

8. The circuit board according to claim 7, characterized in that, The first layer assembly also includes a first inner base copper, which is disposed opposite to the first outer base copper along the thickness direction of the circuit board body; The circuit board body is also provided with a stepped hole at its edge. The stepped hole penetrates the second layer board assembly and the insulating plate so that the first internal base copper of the first layer board assembly is exposed through the stepped hole. The inner peripheral sidewall of the stepped hole is deposited with the second copper plating electrode layer.

9. The circuit board according to claim 8, characterized in that, The stepped hole is detachably filled with a second filler.

10. The circuit board according to claim 9, characterized in that, The first filler is a cured resin; The second filler is a Teflon gasket.

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