Transmit receive assembly packaging structure

Abstract

The utility model discloses a TR assembly packaging structure, including first base plate, second base plate and third base plate that set up interval in proper order, be provided with the upper dam between first base plate and second base plate and be connected, be provided with the lower dam between second base plate and third base plate and be connected, the area between first base plate and second base plate is formed first airtight cavity by the upper dam, the area between second base plate and third base plate is formed second airtight cavity by the lower dam, wherein, at least part upper dam and / or part lower dam set up on second base plate. The utility model discloses by making at least part upper dam and / or part lower dam set up on second base plate, can scatter or offset stress to reduce the stress between single base plate and dam and then reduce the cracking risk between dam and corresponding base plate, can improve the air tightness of TR assembly while making high dam.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a TR component packaging structure. Background Technology

[0002] In the manufacturing of TR module packaging structures, the dam, as a key component for achieving module sealing and structural support, directly affects the overall performance and reliability of the packaging structure. In existing technologies, the dam formed by further plating on the lower substrate circuit layer in TR module packaging structures typically has a height in the range of 650μm to 800μm. This height is generally higher than the critical threshold of 500μm, and this relatively high dam height has caused a series of technical challenges in practical applications. In the welding process between the dam and the intermediate connecting plate, the excessive height of the dam results in a large overall volume, making it difficult to achieve a good match between the thermal expansion coefficients of the dam and the lower substrate. This mismatch in thermal expansion coefficients leads to significant stress between the dam and the lower substrate during welding and subsequent use. As stress accumulates, the lower substrate is highly susceptible to cracking. Cracks in the substrate directly damage the sealing structure of the TR module, severely affecting the hermeticity of the packaging structure. This, in turn, allows the internal components of the module to be affected by external environmental factors, reducing the module's operational stability and lifespan. Summary of the Invention

[0003] The purpose of this utility model is to provide a TR component packaging structure to solve the problem of substrate cracking caused by excessive stress on the substrate where the dam is located due to excessive dam height during welding.

[0004] The objective of this utility model is achieved through the following technical solution: This utility model provides a TR component packaging structure, including a first substrate, a second substrate and a third substrate arranged sequentially at intervals. An upper dam is provided between the first substrate and the second substrate, and a lower dam is provided between the second substrate and the third substrate. The upper dam encloses the area between the first substrate and the second substrate to form a first sealed cavity, and the lower dam encloses the area between the second substrate and the third substrate to form a second sealed cavity. Wherein, at least part of the upper dam and / or part of the lower dam are disposed on the second substrate.

[0005] As a further improvement of one embodiment of the present invention, at least a portion of the lower dam is integrally formed on the first circuit layer on the lower surface of the second substrate, and at least a portion of the upper dam is integrally formed on the second circuit layer on the upper surface of the second substrate.

[0006] As a further improvement of one embodiment of the present invention, the TR component packaging structure further includes a first welding layer and a second welding layer, wherein the first welding layer connects the upper dam and the first substrate, and the second welding layer connects the lower dam and the third substrate.

[0007] As a further improvement of one embodiment of the present utility model, the lower dam includes a first lower dam and a second lower dam, wherein the first lower dam is disposed above the second lower dam; The first lower dam is integrally formed on the first circuit layer on the lower surface of the second substrate; The second lower dam is integrally formed on the third circuit layer on the upper surface of the third substrate.

[0008] As a further improvement of one embodiment of the present invention, the TR component packaging structure further includes a third welding layer, which connects the first lower dam and the second lower dam.

[0009] As a further improvement of one embodiment of the present utility model, the upper dam is integrally formed on the fourth circuit layer on the lower surface of the first substrate, and the heights of the first lower dam and the second lower dam are respectively less than or equal to 500μm. The TR component packaging structure also includes a fourth welding layer, which connects the upper dam and the second substrate.

[0010] As a further improvement of one embodiment of the present invention, the upper dam is integrally formed on the second circuit layer on the upper surface of the second substrate; The TR component packaging structure also includes a first welding layer, which connects the upper dam and the first substrate.

[0011] As a further improvement of one embodiment of the present invention, the height of the upper dam is less than or equal to 500 μm, and the height of the lower dam is greater than 500 μm.

[0012] As a further improvement of one embodiment of the present invention, the first substrate, the second substrate and the third substrate are all ceramic plates; And / or, both the upper and lower dams are copper pillars.

[0013] As a further improvement of one embodiment of the present invention, a first semiconductor device is disposed on the lower surface of the first substrate, and the first semiconductor device is located in the first sealed cavity. A second semiconductor device is disposed on the upper surface of the third substrate, and the second semiconductor device is located in the second sealed cavity.

[0014] Compared with the prior art, the beneficial effects of this utility model include at least the following: Compared with the prior art in which the upper dam is entirely set on the first substrate and the lower dam is entirely set on the third substrate (i.e. the lower substrate mentioned above), when the stress between at least one of the upper dam and / or the lower dam and the corresponding substrate is too large, cracks may occur between the upper dam and / or the lower dam and the corresponding substrate. This application, by setting at least part of the upper dam and / or part of the lower dam on the second substrate, can disperse or cancel the stress, thereby reducing the stress between a single substrate and the dam and thus reducing the risk of cracking between the dam and the corresponding substrate. It can improve the airtightness of the TR module while making a high dam. Attached Figure Description

[0015] Figure 1 This is an exploded view of the packaging structure of a TR component according to Embodiment 1 of this utility model; Figure 2 This is a schematic diagram of a TR component packaging structure according to Embodiment 1 of this utility model; Figure 3 This is an exploded view of the TR component packaging structure in Embodiment 2 of this utility model; Figure 4 This is a schematic diagram of a TR component packaging structure according to Embodiment 2 of this utility model; Figure 5 This is an exploded view of the packaging structure of a TR component according to Embodiment 3 of this utility model; Figure 6 This is a schematic diagram of a TR component packaging structure in Embodiment 3 of this utility model.

[0016] In the figure: 1. First substrate; 2. Second substrate; 3. Third substrate; 4. Upper dam; 5. Lower dam; 61. First sealed cavity; 62. Second sealed cavity; 71. First circuit layer; 72. Second circuit layer; 73. Third circuit layer; 74. Fourth circuit layer; 81. First solder layer; 82. Second solder layer; 83. Third solder layer; 84. Fourth solder layer; 91. First semiconductor device; 92. Second semiconductor device. Detailed Implementation

[0017] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0018] The terms used to describe position and direction in this utility model are illustrated with the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this utility model.

[0019] like Figures 1-6 As shown, this utility model provides a TR component packaging structure, including a first substrate 1, a second substrate 2 and a third substrate 3 arranged sequentially at intervals. An upper dam 4 is provided between the first substrate 1 and the second substrate 2, and a lower dam 5 is provided between the second substrate 2 and the third substrate 3. The upper dam 4 encloses the area between the first substrate 1 and the second substrate 2 to form a first sealed cavity 61, and the lower dam 5 encloses the area between the second substrate 2 and the third substrate 3 to form a second sealed cavity 62.

[0020] In this embodiment, at least a portion of the upper dam 4 and / or a portion of the lower dam 5 can be disposed on the second substrate 2. Compared to the prior art where the upper dam 3 is entirely disposed on the first substrate 1 and the lower dam 5 is entirely disposed on the third substrate 3, when the stress between at least one of the upper dam 4 and / or the lower dam 5 and the corresponding substrate is too high, cracking may occur between the upper dam 4 and / or the lower dam 5 and the corresponding substrate. In this application, by disposing at least a portion of the upper dam 4 and / or a portion of the lower dam 5 on the second substrate 2, the stress can be dispersed or offset, thereby reducing the stress between a single substrate and the dam and reducing the risk of cracking between the dam and the corresponding substrate. This allows for the improvement of the hermeticity of the TR module while manufacturing a high dam.

[0021] As a preferred method, the height of the lower dam 5 is greater than the height of the upper dam 4. Example 1

[0022] See Figure 1 and Figure 2 Example 1 provides a TR component packaging structure, including a first substrate 1, a second substrate 2 and a third substrate 3 arranged sequentially at intervals. The second substrate 2 is located between the first substrate 1 and the third substrate 3. The first substrate 1 is located directly above the second substrate 2 and the third substrate 3 is located directly below the second substrate 2.

[0023] The first substrate 1 has an upper surface and a lower surface opposite to the upper surface. The upper surface and the lower surface of the first substrate 1 are two opposite side surfaces of the first substrate 1 along its thickness direction, and are also the two side surfaces of the first substrate 1 with the largest area. Specifically, the lower surface of the first substrate 1 is the side surface of the first substrate 1 facing the second substrate 2, and the upper surface of the first substrate 1 is the side surface of the first substrate 1 away from the second substrate 2.

[0024] The second substrate 2 has an upper surface and a lower surface opposite to the upper surface. The upper and lower surfaces of the second substrate 2 are two opposing side surfaces along its thickness direction, and are also the two side surfaces of the second substrate 2 with the largest area. Specifically, the upper surface of the second substrate 2 is the side surface of the second substrate 2 facing the first substrate 1, and the lower surface of the second substrate 2 is the side surface of the second substrate 2 away from the first substrate 1. In other words, the upper surface of the second substrate 2 is the side surface of the second substrate 2 away from the third substrate 3, and the lower surface of the second substrate 2 is the side surface of the second substrate 2 facing the third substrate 3.

[0025] The third substrate 3 has an upper surface and a lower surface opposite to the upper surface. The upper and lower surfaces of the third substrate 3 are two opposite side surfaces of the third substrate 3 along its thickness direction, and are also the two side surfaces of the third substrate 3 with the largest area. Specifically, the upper surface of the third substrate 3 is the side surface of the third substrate 3 facing the second substrate 2, and the lower surface of the third substrate 3 is the side surface of the third substrate 3 away from the second substrate 2.

[0026] An upper dam 4 is provided between the first substrate 1 and the second substrate 2, and the upper dam 4 encloses the area between the first substrate 1 and the second substrate 2 to form a first sealed cavity 61. Specifically, the two ends of the upper dam 4 along the height direction are respectively connected to the lower surface of the first substrate 1 and the upper surface of the second substrate 2, and the upper dam 4 is located in the peripheral area of ​​the lower surface of the first substrate 1 and the upper surface of the second substrate 2.

[0027] A lower enclosure 5 is provided between the second substrate 2 and the third substrate 3, forming a second sealed cavity 62 by enclosing the area between the second substrate 2 and the third substrate 3. Specifically, the two ends of the lower enclosure 5 along the height direction are respectively connected to the lower surface of the second substrate 2 and the upper surface of the third substrate 3, and the lower enclosure 5 is located in the peripheral area of ​​the lower surface of the second substrate 2 and the upper surface of the third substrate 3.

[0028] The first substrate 1, the second substrate 2, and the third substrate 3 are all ceramic plates. Of course, this utility model does not limit this, and the first substrate 1, the second substrate 2, and the third substrate 3 can also be metal substrates, epoxy resin substrates, ceramic-metal composite substrates, etc.

[0029] Specifically, the lower dam 5 is higher than the upper dam 4, and the upper dam 4 and the lower dam 5 are set in the same height direction.

[0030] More specifically, at least a portion of the lower dam 5 is integrally formed on the first circuit layer 71 on the lower surface of the second substrate 2, and at least a portion of the upper dam 4 is integrally formed on the second circuit layer 72 on the upper surface of the second substrate 2. In this embodiment, all lower dams 5 are integrally formed on the first circuit layer 71 on the lower surface of the second substrate 2, and all upper dams 4 are integrally formed on the second circuit layer 72 on the upper surface of the second substrate 2.

[0031] Specifically, the upper dam 4 is deposited on the second circuit layer 72 on the upper surface of the second substrate 2 by plating. That is, after the second circuit layer 72 is first formed on the upper surface of the second substrate 2 by electroplating, sputtering, or a combination of sputtering and electroplating, the upper dam 4 is formed by electroplating to thicken the second circuit layer 72 on the side facing away from the second substrate 2. The upper dam 4 and the second circuit layer 72 are integrally formed on the second substrate 2. Of course, the upper dam 4 can be made of the same material as or different from the second circuit layer 72.

[0032] Preferably, the second line layer 72 includes a copper layer, and the upper dam 4 is a copper pillar.

[0033] Specifically, the lower dam 5 is deposited on the first circuit layer 71 on the lower surface of the second substrate 2 by plating. That is, after the first circuit layer 71 is first formed on the lower surface of the second substrate 2 by electroplating, sputtering, or a combination of sputtering and electroplating, the lower dam 5 is formed by electroplating to thicken the first circuit layer 71 on the side facing away from the second substrate 2. The lower dam 5 and the first circuit layer 71 are integrally formed on the second substrate 2. Of course, the lower dam 5 can be made of the same material as or different from the first circuit layer 71.

[0034] Preferably, the first line layer 71 includes a copper layer, and the lower dam 5 is a copper pillar.

[0035] In other embodiments, a portion of the lower dam 5 may be integrally formed on the first circuit layer 71, and a portion of the upper dam 4 may be integrally formed on the second circuit layer 72; or, one of the upper dam 4 and the lower dam 5 may be entirely integrally formed on the corresponding circuit layer, and the other may be partially integrally formed on the corresponding circuit layer. For example, all of the upper dam 4 may be integrally formed on the second circuit layer 72, and a portion of the lower dam 5 may be integrally formed on the first circuit layer 71; or, a portion of the upper dam 4 may be integrally formed on the second circuit layer 72, and all of the lower dam may be integrally formed on the first circuit layer 71. By integrally forming at least a portion of the dams on opposite sides of the second substrate 2, stress is generated between the upper dam 4 and the upper surface of the second substrate 2, and stress is generated between the lower dam 5 and the lower surface of the second substrate 2. The stresses on the upper and lower sides of the second substrate 2 are in opposite directions and thus cancel each other out. After the stresses on both sides of the second substrate 2 are at least partially canceled out, the actual stress that the second substrate 2 needs to bear is smaller, which can reduce the risk of cracking between the dams and the second substrate 2.

[0036] Furthermore, the TR component packaging structure also includes a first solder layer 81 and a second solder layer 82. The first solder layer 81 connects the upper cofferdam 4 and the first substrate 1, and the second solder layer 82 connects the lower cofferdam 5 and the third substrate 3. Specifically, when the upper cofferdam 4 and the lower cofferdam 5 are respectively disposed on opposite sides of the second substrate 2, the first solder layer 81 connects the upper cofferdam 4 and the fourth circuit layer 74 on the lower surface of the first substrate 1, and the second solder layer 82 connects the lower cofferdam 5 and the third circuit layer 73 on the upper surface of the third substrate 3.

[0037] Preferably, the material used to make the first solder layer 81 and the second solder layer 82 is lead-free solder, such as tin.

[0038] In this embodiment, the height of the upper dam 4 is less than or equal to 500 μm, and the height of the lower dam 5 is greater than 500 μm. Thus, during the soldering of the TR assembly, specifically when the first substrate 1 and the third substrate 3 are soldered to the upper end of the upper dam 4 and the lower end of the lower dam 5 respectively using lead-free solder, the stress between the upper dam 4 and the lower dam 5, respectively located on the upper and lower surfaces of the second substrate 2, and the second substrate 2 can partially cancel each other out. This balances the stress generated by the higher lower dam 5, keeping the stress between the lower dam 5 and the third substrate 3, and between the lower dam 5 and the second substrate 2, within a controllable range. This prevents excessive stress on the third substrate 3 and the second substrate 2 due to the higher height of the lower dam 5 during soldering, which could cause cracking of the third substrate 3 and the second substrate 2, thereby improving the airtightness of the TR assembly.

[0039] Furthermore, a first semiconductor device 91 connected to the fourth circuit layer 74 is disposed on the lower surface of the first substrate 1, and the first semiconductor device 91 is located inside the first sealed cavity 61. A second semiconductor device 92 connected to the third circuit layer 73 is disposed on the upper surface of the third substrate 3, and the second semiconductor device 92 is located inside the second sealed cavity 62.

[0040] The first semiconductor device 91 and the second semiconductor device 92 are specifically chips. Example 2

[0041] See Figure 3 and Figure 4 Unlike Embodiment 1, in this embodiment, part of the lower dam 5 is integrally formed on the first circuit layer 71 on the lower surface of the second substrate 2, and another part of the lower dam 5 is integrally formed on the third circuit layer 73 on the upper surface of the third substrate 3. The two parts of the lower dam 5 are connected by solder.

[0042] Specifically, the lower dam 5 includes a first lower dam 51 and a second lower dam 52, with the first lower dam 51 positioned above the second lower dam 52. The first lower dam 51 is integrally formed on the first circuit layer 71 on the lower surface of the second substrate 2, and the second lower dam 52 is integrally formed on the third circuit layer 73 on the upper surface of the third substrate 3. By dividing the lower dam 5 into two parts, and with both the first lower dam 51 and the second lower dam 52 having relatively low heights, excessive stress caused by dams connected to the same side of the substrate can be prevented. In this application, after the lower dam 5 is set separately, the first lower dam 51 is positioned on the first circuit layer 71 of the second substrate 2. Due to the lower height of the first lower dam 51, the stress between the first lower dam 51 and the second substrate 2 is relatively low; the second lower dam 52 is positioned on the third circuit layer 73 of the third substrate 3. Due to the lower height of the second lower dam 52, the stress between the second lower dam 52 and the third substrate 3 is also relatively low.

[0043] It is understandable that when the height of the lower dam 5 is relatively high, the lower dam 5 is set in two parts to avoid stress concentration. If the height of the upper dam 4 is relatively high, the upper dam 4 can also be set in two parts, with one part of the upper dam 4 integrally formed on the first substrate 1 and the other part integrally formed on the second substrate 2.

[0044] Specifically, the first lower dam 51 is deposited on the first circuit layer 71 on the lower surface of the second substrate 2 by plating. That is, after the first circuit layer 71 is first formed on the lower surface of the second substrate 2 by electroplating, sputtering, or a combination of sputtering and electroplating, the first lower dam 51 is formed by electroplating to thicken the first circuit layer 71 on the side of the first circuit layer 71 away from the second substrate 2. The first lower dam 51 and the first circuit layer 71 are integrally formed on the second substrate 2. Of course, the first lower dam 51 can be made of the same material as or different from the first circuit layer 71.

[0045] Preferably, the first line layer 71 includes a copper layer, and the first lower dam 51 is a copper pillar.

[0046] Specifically, the second lower dam 52 is deposited on the third circuit layer 73 on the upper surface of the third substrate 3 by plating. That is, after the third circuit layer 73 is first formed on the upper surface of the third substrate 3 using electroplating, sputtering, or a combination of both, the second lower dam 52 is formed by plating on the side of the third circuit layer 73 away from the third substrate 3. The second lower dam 52 and the third circuit layer 73 are integrally formed on the third substrate 3. Of course, the second lower dam 52 can be made of the same or different material as the third circuit layer 73.

[0047] Preferably, the third line layer 73 includes a copper layer, and the second lower dam 52 is a copper pillar.

[0048] Preferably, the lower dam 5 is divided into two parts, namely, the first lower dam 51 and the second lower dam 52 are of equal height. Of course, in other embodiments, the heights of the first lower dam 51 and the second lower dam 52 may not be equal, with the height of the first lower dam 51 being greater than the height of the second lower dam 52, or the height of the first lower dam 51 being less than the height of the second lower dam 52.

[0049] Furthermore, the TR component encapsulation structure also includes a third welding layer 83, which connects the first lower cofferdam 51 and the second lower cofferdam 52.

[0050] Preferably, the material used to make the third solder layer 83 is lead-free solder, such as tin.

[0051] In this embodiment, the upper dam 4 is integrally formed on the second circuit layer 72 on the upper surface of the second substrate 2. Specifically, the upper dam 4 is formed on the second circuit layer 72 on the upper surface of the second substrate 2 by plating. That is, after forming the second circuit layer 72 on the upper surface of the second substrate 2 by electroplating, sputtering, or a combination of sputtering and electroplating, the upper dam 4 is formed by electroplating to thicken the second circuit layer 72 on the side facing away from the second substrate 2. The upper dam 4 and the second circuit layer 72 are integrally formed on the second substrate 2. Of course, the upper dam 4 can be made of the same material as or different from the second circuit layer 72.

[0052] Preferably, the second line layer 72 includes a copper layer, and the upper dam 4 is a copper pillar.

[0053] Furthermore, the TR component packaging structure also includes a first solder layer 81, which connects the upper dam 4 and the first substrate 1. Specifically, the first solder layer 81 connects the upper dam 4 and the fourth circuit layer 74 on the lower surface of the first substrate 1.

[0054] Preferably, the material used to make the first solder layer 81 is lead-free solder, such as tin.

[0055] Thus, the higher lower dam 5 in the packaging structure is divided into a first lower dam 51 and a second lower dam 52, and the height of both the first lower dam 51 and the second lower dam 52 is no higher than 500μm. The first lower dam 51 is deposited on the first circuit layer 71 on the lower surface of the second substrate 2 by plating, and the second lower dam 52 is deposited on the third circuit layer 73 on the upper surface of the third substrate 3 by plating. This disperses the stress generated by the lower dam 5. When the packaging structure is soldered, the stress between the first lower dam 51 on the second substrate 2 and the second substrate 2 is small, which can also appropriately balance the stress applied by the upper dam 4 on the upper surface of the second substrate 2. At the same time, the stress between the second lower dam 52 on the third substrate 3 and the third substrate 3 is small, which can prevent the risk of cracking or breaking of the second substrate 2 and the third substrate 3, and improve the hermeticity of the TR component. Example 3

[0056] See Figure 5 and Figure 6 Unlike Embodiment 2, in this embodiment, the upper dam 4 is integrally formed on the fourth circuit layer 74 on the lower surface of the first substrate 1.

[0057] Specifically, the upper dam 4 is deposited on the fourth circuit layer 74 on the lower surface of the first substrate 1 by plating. That is, after the fourth circuit layer 74 is first formed on the lower surface of the first substrate 1 by electroplating, sputtering, or a combination of sputtering and electroplating, the upper dam 4 is formed by electroplating to thicken the fourth circuit layer 74 on the side facing away from the first substrate 1. The upper dam 4 and the fourth circuit layer 74 are integrally formed on the first substrate 1. Of course, the upper dam 4 can be made of the same material as or different from the fourth circuit layer 74.

[0058] Preferably, the fourth line layer 74 includes a copper layer, and the upper dam 4 is a copper pillar.

[0059] Furthermore, the TR component packaging structure also includes a fourth bonding layer 84, which connects the upper containment dam 4 and the second substrate 2. Specifically, the fourth bonding layer 84 connects the upper containment dam 4 and the second circuit layer 72 on the upper surface of the second substrate 2.

[0060] Preferably, the material used to make the fourth solder layer 84 is lead-free solder, such as tin.

[0061] In this embodiment, since the height of the upper dam 4 is no higher than 500μm, even if the upper dam 4 is fixedly set on the first substrate 1 by plating, the stress between the upper dam 4 and the first substrate 1 is small during welding, and there is basically no risk of the first substrate 1 cracking or breaking.

[0062] In summary, this utility model provides a TR component packaging structure. Compared with the prior art where the upper dam 3 is entirely disposed on the first substrate 1 and the lower dam 5 is entirely disposed on the third substrate 3, when the stress between at least one of the upper dam 4 and / or the lower dam 5 and the corresponding substrate is too high, cracks may occur between the upper dam 4 and / or the lower dam 5 and the corresponding substrate. This application, by distributing at least part of the upper dam 4 and / or part of the lower dam 5 on the second substrate 2, can disperse or cancel the stress, thereby reducing the stress between a single substrate and the dam and thus reducing the risk of cracking between the dam and the corresponding substrate. It can improve the airtightness of the TR component while manufacturing a high dam.

[0063] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and alterations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention, and all such changes should fall within the protection scope of the claims of the present invention.

Claims

1. A TR component encapsulation structure, characterized in that, It includes a first substrate, a second substrate, and a third substrate arranged at intervals in sequence. An upper dam is provided between the first substrate and the second substrate, and a lower dam is provided between the second substrate and the third substrate. The upper dam encloses the area between the first substrate and the second substrate to form a first sealed cavity, and the lower dam encloses the area between the second substrate and the third substrate to form a second sealed cavity. Wherein, at least part of the upper dam and / or part of the lower dam are disposed on the second substrate.

2. The TR component encapsulation structure according to claim 1, characterized in that, At least a portion of the lower dam is integrally formed on the first circuit layer on the lower surface of the second substrate, and at least a portion of the upper dam is integrally formed on the second circuit layer on the upper surface of the second substrate.

3. The TR component encapsulation structure according to claim 2, characterized in that, The TR component packaging structure further includes a first welding layer and a second welding layer, wherein the first welding layer connects the upper dam and the first substrate, and the second welding layer connects the lower dam and the third substrate.

4. The TR component encapsulation structure according to claim 1, characterized in that, The lower dam includes a first lower dam and a second lower dam, with the first lower dam located above the second lower dam; The first lower dam is integrally formed on the first circuit layer on the lower surface of the second substrate; The second lower dam is integrally formed on the third circuit layer on the upper surface of the third substrate.

5. The TR component encapsulation structure according to claim 4, characterized in that, The TR component encapsulation structure also includes a third welding layer, which connects the first lower dam and the second lower dam.

6. The TR component encapsulation structure according to claim 4, characterized in that, The upper dam is integrally formed on the fourth circuit layer on the lower surface of the first substrate, and the heights of the first lower dam and the second lower dam are respectively less than or equal to 500μm; The TR component packaging structure also includes a fourth welding layer, which connects the upper dam and the second substrate.

7. The TR component encapsulation structure according to claim 4, characterized in that, The upper dam is integrally formed on the second circuit layer on the upper surface of the second substrate; The TR component packaging structure also includes a first welding layer, which connects the upper dam and the first substrate.

8. The TR component encapsulation structure according to any one of claims 1-7, characterized in that, The height of the upper dam is less than or equal to 500 μm, and the height of the lower dam is greater than 500 μm.

9. The TR component encapsulation structure according to any one of claims 1-7, characterized in that, The first substrate, the second substrate, and the third substrate are all ceramic plates; And / or, both the upper and lower dams are copper pillars.

10. The TR component packaging structure according to any one of claims 1-7, characterized in that, A first semiconductor device is disposed on the lower surface of the first substrate, and the first semiconductor device is located in the first sealed cavity; A second semiconductor device is disposed on the upper surface of the third substrate, and the second semiconductor device is located in the second sealed cavity.

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