Semiconductor device structure

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor layer, a second semiconductor layer, a gate dielectric layer, an n-type work function layer, a p-type work function layer, and a bulk metal fill. The first semiconductor layer is disposed in an NMOS region of a substrate. The second semiconductor layer is disposed in a PMOS region of the substrate. The gate dielectric layer surrounds at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer. The n-type work function layer surrounds the gate dielectric layer in the NMOS region. The p-type work function layer is disposed around the n-type work function layer in the NMOS region. The p-type work function layer surrounds the gate dielectric layer in the PMOS region. The bulk metal fill is disposed on the p-type work function layer in the NMOS region and the PMOS region.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spawned generations of ICs, each with circuits that are smaller and more complex than the previous generation. In IC development, functional density (i.e., the number of interconnects per wafer area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) decreases. This scaling down process usually provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Utility Model Content

[0004] According to some embodiments disclosed herein, a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor layer, a second semiconductor layer, a gate dielectric layer, an n-type work function layer, a p-type work function layer, and a body metal filler. The first semiconductor layer is disposed in an n-type metal-oxide-semiconductor region of a substrate. The second semiconductor layer is disposed in a p-type metal-oxide-semiconductor region of the substrate. The gate dielectric layer surrounds at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer. The n-type work function layer surrounds the gate dielectric layer in the n-type metal-oxide-semiconductor region. The p-type work function layer surrounds the n-type work function layer in the n-type metal-oxide-semiconductor region. The p-type work function layer surrounds the gate dielectric layer in the p-type metal-oxide-semiconductor region. The body metal filler is disposed on the n-type metal-oxide-semiconductor region and the p-type work function layer in the p-type metal-oxide-semiconductor region.

[0005] According to some embodiments disclosed herein, a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor layer, a second semiconductor layer, a gate dielectric layer, a first work function layer, a second work function layer, a body metal filler, and an interface layer. The first semiconductor layer is disposed in a first region of a substrate. The second semiconductor layer is disposed in a second region of the substrate. The gate dielectric layer surrounds the first semiconductor layer and the second semiconductor layer. The first work function layer surrounds the gate dielectric layer in the first region. The second work function layer is disposed around the first work function layer in the first region, wherein the second work function layer surrounds the gate dielectric layer in the second region. The body metal filler is disposed on the second work function layer in the first region and the second region. The interface layer is located between the first semiconductor layer and the gate dielectric layer and between the second semiconductor layer and the gate dielectric layer.

[0006] According to some embodiments disclosed herein, a semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and source / drain regions. The first gate structure includes a first semiconductor layer, a first gate dielectric layer, and a first gate electrode. The first gate dielectric layer surrounds the first semiconductor layer. The first gate electrode includes a first work function layer, a second work function layer, and a body metal filler. The first work function layer surrounds the first gate dielectric layer in a first region. A second work function layer is disposed around the first work function layer in the first region, such that the first work function layer is located between the second work function layer and the first gate dielectric layer. The body metal filler is disposed on the second work function layer. The second gate structure is disposed in a second region of a substrate, the second region being adjacent to the first region. The second gate structure includes a second semiconductor layer, a second gate dielectric layer, and a second gate electrode. The second gate dielectric layer surrounds the second semiconductor layer. The second gate electrode includes a second work function layer and a body metal filler. The second work function layer surrounds the second gate dielectric layer in the second region, wherein the second work function layer and the second gate dielectric layer are in direct contact. The body metal filler is disposed on the second work function layer. The source / drain regions are adjacent to the first gate structure and the second gate structure. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 Perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments;

[0009] Figure 7A According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line AA.

[0010] Figure 7B According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line BB.

[0011] Figure 7C According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by the CC line.

[0012] Figure 8A According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line AA.

[0013] Figure 8B According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line BB.

[0014] Figure 8C According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by the CC line.

[0015] Figure 9A According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line AA.

[0016] Figure 9B According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line BB.

[0017] Figure 9C According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by the CC line.

[0018] Figure 10A According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line AA.

[0019] Figure 10B According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line BB.

[0020] Figure 10C According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by the CC line.

[0021] Figure 11A According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line AA.

[0022] Figure 11B According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line BB.

[0023] Figure 11C According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by the CC line.

[0024] Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 12F , Figure 12G , Figure 12H and Figure 12I A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments;

[0025] Figure 13 According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure, taken by line AA.

[0026] [Symbol Explanation]

[0027] 100: Semiconductor Device Structure

[0028] 101:Substrate

[0029] 104: Semiconductor layer stacking

[0030] 106: First semiconductor layer

[0031] 108: Second semiconductor layer

[0032] 112: Fin-shaped structure

[0033] 114: Trench

[0034] 116: Substrate portion

[0035] 118: Insulating materials

[0036] 120: Isolation Area

[0037] 130: Sacrificial gate structure

[0038] 132: Sacrificial gate dielectric layer

[0039] 134: Sacrificial gate electrode layer

[0040] 136: Masking layer

[0041] 138: Gate spacer

[0042] 144: Dielectric spacer

[0043] 146: Source / Drain Region / S / D Region

[0044] 162: Contact Etching Termination Layer / CESL

[0045] 164: Interlayer Dielectric Layer / ILD Layer

[0046] 169: Interface Layer / IL

[0047] 170: Gate dielectric layer

[0048] 172: Gate electrode layer

[0049] 174: Gate Structure

[0050] 200: Sacrifice Layer

[0051] 202: Barrier Layer

[0052] 204: Patterned mask layer

[0053] 210: n-type work function layer

[0054] 212: p-type work function layer

[0055] 214: Main metal filler

[0056] AA, BB, CC: lines

[0057] T1, T2, T3, T4, T5: Thickness

[0058] X, Y, Z: Direction Detailed Implementation

[0059] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0060] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0061] While the embodiments of this disclosure discuss nanostructured channel FETs, such as gate all-around (GAA) FETs, such as horizontal gate all-around (HGAA) FETs or vertical gate all-around (VGAA) FETs, implementations of certain forms of this disclosure can be used with other processes and / or other devices, such as planar FETs, fin FETs, and other suitable devices. Other modifications that may be considered within the scope of this disclosure will be readily apparent to those skilled in the art. In the case of a gate all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern these structures, including dual-patterning processes or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine lithography and self-alignment processes to allow the creation of patterns, for example, with a pitch smaller than that obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacers can be used to pattern the GAA structure.

[0062] Figures 1 to 13 This illustration depicts an exemplary process for manufacturing a semiconductor device structure 100 according to embodiments of this disclosure. It will be understood that... Figures 1 to 13 Additional operations may be provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limited and is interchangeable.

[0063] Figures 1 to 6 This is a perspective view of various stages in manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate, wherein an insulating layer (not shown) is disposed between two silicon layers for reinforcement. On one hand, the insulating layer is an oxygen-containing layer.

[0064] The substrate 101 may include various regions that are doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for n-type field-effect transistors (NFETs) and boron for p-type field-effect transistors (PFETs).

[0065] Semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels, such as nanostructured channel FETs, in multi-gate devices. In some embodiments, semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some instances, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0066] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0067] The first semiconductor layer 106, or portions thereof, may form nanostructured channels of the semiconductor device structure 100 in subsequent fabrication stages. The term nanostructure is used herein to designate any material portion having nanoscale or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of such portions. Thus, this term refers to elongated material portions with circular and substantially circular cross-sections, and beam-like or strip-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gate electrodes around the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0068] Each first semiconductor layer 106 may have a thickness ranging from about 3 nm to about 9 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 may have a thickness ranging from about 4 nm to about 14 nm. Figure 1 The alternating arrangement of three first semiconductor layers 106 and three second semiconductor layers 108 is for illustrative purposes only and is not intended to limit the specific content described in the claims. It is understood that any number of first semiconductor layers 106 and any number of second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100. In some embodiments, the number of first semiconductor layers 106 ranges from 2 to 10.

[0069] exist Figure 2In this embodiment, fin structures 112 are formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including a first semiconductor layer 106 and a second semiconductor layer 108, and a substrate portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using multiple patterning operations including lithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process may include the following steps: forming a photoresist layer (not shown) on the hard mask layer; exposing the photoresist layer to the pattern; performing a post-exposure baking process; and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, an electron beam lithography process may be used to pattern the photoresist layer to form the mask element. The etching process forms trenches 114 in unprotected areas, through a hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. Dry etching (e.g., RIE), wet etching, and / or combinations thereof can be used to etch the trenches 114.

[0070] exist Figure 3 In this process, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching back, is performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorosilicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0071] exist Figure 4In this process, insulating material 118 is recessed to form isolation region 120. The recessed insulating material 118 exposes a portion of the fin structure 112, such as a semiconductor layer stack 104. The recessed insulating material 118 also exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using suitable processes, such as dry etching, wet etching, or a combination thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108, the surface of which contacts a substrate portion 116 formed from substrate 101.

[0072] exist Figure 5 In this embodiment, one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 can be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and then patterning these layers into the sacrificial gate structure 130. Then, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 can be formed by conformally depositing one or more layers and anisotropically etching one or more layers. In some embodiments, the gate spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. In some embodiments, while one sacrificial gate structure 130 is shown, two or more sacrificial gate structures 130 may be arranged along the X direction.

[0073] The sacrificial gate dielectric layer 132 may include one or more dielectric material layers, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbide, SiOCN, and / or combinations thereof.

[0074] A portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100.

[0075] exist Figure 6In this process, a portion of the fin structure 112 not covered by the sacrificial gate structure 130 and gate spacer 138 is recessed above, below, or above the top surface of the isolation region 120. The recess of the fin structure 112 can be achieved through an etching process, an isotropic or anisotropic etching process, and the etching process can be selective relative to the first semiconductor layer 106 and the second semiconductor layer 108. The etching process can be dry etching, such as RIE, NBE, etc., or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0076] Figure 7A , Figure 7B and Figure 7C respectively along Figure 6 A cross-sectional side view of the semiconductor device structure 100 taken by lines AA, BB and CC.

[0077] Figure 8A , Figure 8B and Figure 8C According to some embodiments, respectively along Figure 6 A cross-sectional side view of one of the various manufacturing stages of the semiconductor device structure 100, taken from lines AA, BB, and CC. (See attached image.) Figure 8A As shown, the edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms cavities. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0078] After removing the edge portions of each of the second semiconductor layers 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 may be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 can be formed by first forming a conformal dielectric layer, such as ALD, using a conformal deposition process, and then anisotropically etching to remove portions of the conformal dielectric layer outside the dielectric spacers 144. In the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers the spacers 144 along the X-direction.

[0079] Figure 9A , Figure 9B and Figure 9C According to some embodiments, respectively along Figure 6 A cross-sectional side view of one of the various manufacturing stages of the semiconductor device structure 100, taken from lines AA, BB, and CC. (See attached image.) Figure 9A and Figure 9C As shown, the source / drain (S / D) region 146 is formed from the substrate portion 116. The S / D region 146 can be grown vertically and horizontally to form facets that correspond to the crystal planes of the material used for the substrate portion 116. In this disclosure, the source region and drain region are used interchangeably and have substantially the same structure. Furthermore, the source / drain region can refer individually or collectively to the source or drain, depending on the context. The S / D region 146 can consist of one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or one or more layers of Si, SiGe, and Ge for p-channel FETs. For p-channel FETs, p-type dopants, such as boron (B), may also be included in the S / D region 146. The S / D region 146 can be formed using epitaxial growth methods such as CVD, ALD, or MBE.

[0080] Figure 10A , Figure 10B and Figure 10C According to some embodiments, respectively along Figure 6 A cross-sectional side view of one of the various manufacturing stages of the semiconductor device structure 100, taken from lines AA, BB, and CC. Figure 10A , Figure 10B and Figure 10C In this process, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D region 146. CESL 162 may comprise oxygen-containing or nitrogen-containing materials, such as silicon nitride, carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, carbon oxide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. An interlayer dielectric (ILD) layer 164 is then formed on the CESL 162 of the semiconductor device structure 100. Materials used for the ILD layer 164 may include compounds (including Si, O, C, and / or H), such as silicon oxide, SiCOH, or SiOC. Organic materials, such as polymers, may also be used for the ILD layer 164. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 164 is formed, the semiconductor device structure 100 may be subjected to heat treatment to anneal the ILD layer 164.

[0081] After forming the ILD layer 164, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown below. Figure 10A and Figure 10B As shown.

[0082] Figure 11A , Figure 11B and Figure 11C According to some embodiments, respectively along Figure 6 A cross-sectional side view of one of the various manufacturing stages of the semiconductor device structure 100, taken from lines AA, BB, and CC. (See attached image.) Figure 11A and Figure 11B As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. Removal of the sacrificial gate structure 130 and the second semiconductor layer 108 forms openings between the gate spacers 138 and between the first semiconductor layer 106. The ILD layer 164 protects the S / D region 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable method, such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 can be removed by any suitable method, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the ILD layer 164, and the CESL 162.

[0083] The second semiconductor layer 108 can be removed using a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemical composition used in the selective wet etching process removes SiGe without substantially affecting the dielectric materials of Si, gate spacer 138, and dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be etched using a wet etchant, such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant, such as a fluorine-based (e.g., F2) or chlorine-based gas (e.g., Cl2), or any suitable isotropic etchant.

[0084] Figures 12A to 12I This is a cross-sectional side view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 12AAs shown, after forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), an interface layer (IL) 169 is formed to surround the first semiconductor layer 106 and the exposed portion of the substrate portion 116, and a gate dielectric layer 170 is formed on the IL 169. In some embodiments, the IL 169 is selectively formed on the semiconductor material of the first semiconductor layer 106 and the substrate portion 116, and the gate dielectric layer 170 is also formed on the insulating material 118. In some embodiments, the IL 169 is an oxide layer, such as silicon oxide. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD, or any suitable deposition technique. In some embodiments, the thickness of the gate dielectric layer 170 ranges from about 0.5 nm to about 3 nm.

[0085] In some embodiments, located at Figure 12A The first semiconductor layer 106 on the left is the channel for the NMOS device, which is located in the NMOS region and is situated within the NMOS region. Figure 12A The first semiconductor layer 106 on the right is a channel for a PMOS device adjacent to the NMOS device. The PMOS device is located in the PMOS region.

[0086] In some embodiments, a dipole process is performed to introduce a dipole material into the gate dielectric layer 170. The dipole process may include depositing a dipole layer (not shown) on the gate dielectric layer 170 and performing a thermal process to drive the dipole material in the dipole layer into the gate dielectric layer 170. In some embodiments, different dipole layers are formed for NMOS and PMOS devices. For example, dipole materials suitable for NMOS devices may include lanthanide oxides (La₂O₃), yttrium oxide (Y₂O₃), titanium oxide (TiO₂), other n-type dipole materials, or combinations thereof; and dipole materials suitable for PMOS devices may include aluminum oxide (Al₂O₃), TiO₂, other p-type dipole materials, or combinations thereof. After thermal treatment, the dipole layer is removed to expose the gate dielectric layer 170.

[0087] In some embodiments, after forming the gate dielectric layer 170 (and in some embodiments, the dipole process), a sacrificial layer 200 is deposited on the gate dielectric layer 170, such as... Figure 12AAs shown. The sacrificial layer 200 is made of or comprises a material different from the material of the gate dielectric layer 170. In some embodiments, the sacrificial layer 200 comprises a metal oxide, such as aluminum oxide (Al₂O₃). x ), where x is an integer or non-integer. Ammonia solution can be used as an etchant to remove aluminum oxide via a wet etching process, and the ammonia solution does not affect the gate dielectric layer 170. In some embodiments, the ammonia solution is ammonium hydroxide having about 1 to about 2 wt% ammonia. Other materials, such as zinc oxide, gallium oxide, or titanium nitride, can be used for the sacrificial layer 200. The sacrificial layer 200 can be formed by any suitable process. In some embodiments, the sacrificial layer 200 is formed by a conformal process, such as ALD. The sacrificial layer 200 is formed to fill the gap between vertically adjacent first semiconductor layers 106. Therefore, in some embodiments, the thickness of the sacrificial layer 200 is greater than about 2 nm, such as about 2.5 nm to about 4 nm. If the thickness of the sacrificial layer 200 is less than about 2 nm, a gap may be formed between vertically adjacent first semiconductor layers 106, and the subsequently formed barrier layer 202 ( Figure 12C It may form in the gaps and be difficult to remove. On the other hand, if the thickness of the sacrificial layer 200 is greater than about 4 nm, the subsequent removal of the sacrificial layer 200 may take an unnecessarily long time.

[0088] exist Figure 12B In this process, an etch-back process is performed on the sacrificial layer 200. In some embodiments, a wet etching process is performed to etch back the sacrificial layer 200. The wet etching process reduces the thickness of the portion of the sacrificial layer 200 located above the topmost first semiconductor layer 106 and the insulating material 118. The thickness of the portion of the sacrificial layer 200 located near the sidewalls of the first semiconductor layer 106 may also be reduced. The wet etching process does not remove the portion of the sacrificial layer 200 located between vertically adjacent first semiconductor layers 106. In some embodiments, the thickness T1 of the portion of the sacrificial layer 200 above the topmost first semiconductor layer 106 is reduced to about 1.2 to about 1.8 nm. Therefore, the duration of subsequent removal of the sacrificial layer 200 can be reduced.

[0089] exist Figure 12CIn this process, a barrier layer 202 is formed on the sacrificial layer 200. In some embodiments, the barrier layer 202 is a self-assembled monolayer (SAM) comprising a polymer having silicon, carbon, nitrogen, oxygen, or combinations thereof. In some embodiments, the SAM comprises a backbone containing benzyl or epoxy groups, and the molecular weight of the backbone is between about 30 and about 100. The SAM also includes terminal functional groups, such as benzyl, amine, hydroxyl, sulfone, or phosphorus. The terminal functional groups are functionalized to enhance the deposition selectivity of subsequent deposition processes. For example, the terminal functional groups prevent precursors of subsequent deposition processes from adhering thereto. In some embodiments, the subsequent deposition process is the deposition of an n-type work function layer, and the barrier layer 202 prevents the formation of an n-type work function layer thereon.

[0090] exist Figure 12D In this process, a patterned mask layer 204 is formed to cover a portion of the barrier layer 202 located in the PMOS region, and a portion of the barrier layer 202 located in the NMOS region and a portion of the sacrificial layer 200 located below it are removed. In some embodiments, the patterned mask layer 204 is a patterned photoresist layer. The patterned mask layer 204 can be formed by first forming a mask layer in both the NMOS and PMOS regions, and then removing a portion of the mask layer located in the NMOS region to expose a portion of the barrier layer 202 located in the NMOS region. The exposed portion of the barrier layer 202 can be removed by any suitable process. In some embodiments, a dry etching process, such as a plasma etching process, is performed to remove the exposed portion of the barrier layer 202. If the gate dielectric layer 170 is exposed, the plasma etching process may damage the gate dielectric layer 170, and the sacrificial layer 200 protects the gate dielectric layer 170 during the plasma etching process. As described above, the sacrificial layer 200 fills the gap between vertically adjacent first semiconductor layers 106 to prevent the barrier layer 202 from forming in the gap. If the barrier layer 202 is formed in the gap between vertically adjacent first semiconductor layers 106, it is difficult to remove it using a plasma etching process.

[0091] A portion of the barrier layer 202 on the NMOS device is removed, exposing a portion of the sacrificial layer 200 beneath it. Next, the exposed portion of the sacrificial layer 200 is removed. The exposed portion of the sacrificial layer 200 can be removed using any suitable process. In some embodiments, the exposed portion of the sacrificial layer 200 is removed using a wet etching process with ammonia as the etchant. The wet etching process does not affect the gate dielectric layer 170 located beneath the exposed portion of the sacrificial layer 200. During the removal of portions of the barrier layer 202 and the sacrificial layer 200, the portion of the barrier layer 202 located in the PMOS region is protected by a patterned masking layer 204.

[0092] exist Figure 12EIn this process, the patterned masking layer 204 is removed to expose a portion of the barrier layer 202 located in the PMOS region. In some embodiments, the patterned masking layer 204 is removed using an oxygen-containing plasma through a plasma ashing process. The oxygen-containing plasma can oxidize either the n-type or p-type work function layer. Therefore, in some embodiments, the patterned masking layer 204 is removed even when no work function layer is present. The plasma ashing process does not affect the exposed gate dielectric layer 170 located on the NMOS device.

[0093] exist Figure 12F In this process, an n-type work function layer 210 is selectively deposited on the NMOS device. The n-type work function layer 210 may comprise any suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or combinations thereof. In some embodiments, the n-type work function layer 210 is made of or comprises an aluminum-containing material, such as TiAl, TiAlC, TaAl, TaAlC, or TiAlN. In some embodiments, the thickness of the n-type work function layer 210 ranges from about 0.5 nm to about 20 nm. The n-type work function layer 210 is not formed in the PMOS region. As described above, the barrier layer 202 inhibits the deposition of the precursor of the n-type work function layer 210. The n-type work function layer 210 may be a conformal layer formed by a conformal process (such as ALD).

[0094] In some embodiments, after forming the n-type work function layer 210, an optional cap layer (not shown) may be selectively formed on the n-type work function layer 210. The cap layer may comprise any suitable material. In some embodiments, the cap layer is made of or comprises the same material as the p-type work function layer 212. Figure 12H The barrier layer 202 prevents the cap layer from depositing on it.

[0095] exist Figure 12G In the process, the barrier layer 202 and sacrificial layer 200 located in the PMOS region are removed. The barrier layer 202 can be... Figure 12D The plasma etching process described herein can be used to remove the sacrificial layer 200, and the sacrificial layer 200 can be removed through... Figure 12D The wet etching process described herein removes the n-type work function layer 210 (or cap layer). Both the plasma etching process and the wet etching process have virtually no impact on the n-type work function layer 210. Therefore, there is no need to form a patterned mask layer on the n-type work function layer 210. Thus, in the plasma ashing process for removing the patterned mask layer, the oxygen-containing plasma will not damage the n-type work function layer 210. The barrier layer 202 and sacrificial layer 200 are removed, exposing the gate dielectric layer 170, as described above. Figure 12G As shown.

[0096] exist Figure 12HIn this configuration, a p-type work function layer 212 is deposited on the exposed gate dielectric layer 170 and an n-type work function layer 210 (or cap layer). The p-type work function layer 212 may comprise any suitable p-type work function material, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials, or combinations thereof. In some embodiments, the p-type work function layer 212 is made of TiN or comprises TiN. The p-type work function layer 212 may be formed by any suitable process, such as PVD or ALD. In some embodiments, a portion of the p-type work function layer 212 deposited on the horizontal surface of the gate dielectric layer 170 has a thickness T2, a portion of the p-type work function layer 212 deposited on the vertical surface of the gate dielectric layer 170 has a thickness T3, a portion of the p-type work function layer 212 deposited on the horizontal surface of the n-type work function layer 210 (or cap layer) has a thickness T4, and a portion of the p-type work function layer 212 deposited on the vertical surface of the n-type work function layer 210 (or cap layer) has a thickness T5. In some embodiments, the thickness T2 ranges from about 0.7 nm to about 5 nm, the thickness T3 ranges from about 0.5 nm to about 5 nm, the thickness T4 ranges from about 0.5 nm to about 5 nm, and the thickness T5 ranges from about 0.3 nm to about 5 nm. In some embodiments, the thickness T4 is greater than the thickness T5, and the difference between the thicknesses T4 and T5 can be in the range of 0 to about 0.2 nm. In some embodiments, the thickness T2 is greater than the thickness T3, and the difference between the thicknesses T2 and T3 can be in the range of 0 to about 0.2 nm. In some embodiments, the thickness T2 is greater than the thickness T4, and the difference between the thicknesses T2 and T4 can be in the range of 0 to about 0.2 nm.

[0097] In some embodiments, the p-type work function layer 212 deposited in the PMOS region is aluminum-free because the p-type work function layer 212 is deposited after the n-type work function layer 210. In other words, the n-type work function layer 210 is not deposited after the p-type work function layer 212. PMOS devices with an aluminum-free p-type work function layer 212 have improved threshold voltage tuning.

[0098] exist Figure 12IIn the NMOS and PMOS regions, a main metal filler 214 is formed above the p-type work function layer 212. The main metal filler 214 is made of or includes aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, combinations thereof, or other suitable metals. The main metal filler 214 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The n-type work function layer 210, p-type work function layer 212, and main metal filler 214 located in the NMOS region can be referred to as the gate electrode layer 172, and the p-type work function layer 212 and main metal filler 214 located in the PMOS region can also be referred to as the gate electrode layer 172. The gate electrode layer can also be deposited above the upper surface of the ILD layer 164. Figure 11A Then, the gate electrode layer formed above the ILD layer 164 is removed using, for example, CMP, until the upper surface of the ILD layer 164 is exposed.

[0099] Figure 13 According to some embodiments along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100, taken by line AA. (See also...) Figure 13 As shown, a gate electrode layer 172 is disposed on a gate dielectric layer 170. The gate electrode layer 172 includes an n-type work function layer 210, a p-type work function layer 212, and a main metal filler 214 located in the NMOS region, or a p-type work function layer 212 and a main metal filler 214 located in the PMOS region. For clarity, Figure 13 IL 169 is omitted. IL 169 (not shown), gate dielectric layer 170 and gate electrode layer 172 can be collectively referred to as gate structure 174.

[0100] Embodiments of this disclosure provide a method for forming a semiconductor device structure 100. The method includes the following steps: depositing a sacrificial layer 200 on a gate dielectric layer 170 in an NMOS region and a PMOS region; depositing a barrier layer 202 on the sacrificial layer 200 in the NMOS region and the PMOS region; removing portions of the barrier layer 202 and the sacrificial layer 200 in the NMOS region; selectively depositing an n-type work function layer 210 in the NMOS region; removing the barrier layer 202 and the sacrificial layer 200 in the PMOS region; and depositing a p-type work function layer 212 in the PMOS region and the NMOS region. Some embodiments offer advantages. For example, the sacrificial layer 200 protects the gate dielectric layer 170 when a portion of the barrier layer 202 in the NMOS region is removed. Furthermore, by depositing the p-type work function layer 212 after depositing the n-type work function layer, the p-type work function layer 212 is aluminum-free. Therefore, improved tuning of the threshold voltage is achieved.

[0101] Some embodiments are methods for forming a semiconductor device structure. The method includes the steps of: forming first and second fin structures from a substrate, the first fin structure including a plurality of first semiconductor layers, and the second fin structure including a plurality of second semiconductor layers. The method further includes the steps of: depositing a gate dielectric layer around a portion of each of the plurality of first and second semiconductor layers; depositing a sacrificial layer on the gate dielectric layer; removing a first portion of the sacrificial layer disposed on a first portion of the gate dielectric layer surrounding the plurality of first semiconductor layers; selectively depositing a first work function layer on the first portion of the gate dielectric layer; removing a second portion of the sacrificial layer disposed on a second portion of the gate dielectric layer surrounding the plurality of second semiconductor layers; depositing a second work function layer over the first work function layer and the second portion of the gate dielectric layer; and depositing a body metal filler on the second work function layer.

[0102] In some embodiments, the sacrificial layer comprises a metal oxide. In some embodiments, the metal oxide comprises aluminum oxide, zinc oxide, or gallium oxide. In some embodiments, the step of selectively depositing the first work function layer comprises: depositing a barrier layer on the sacrificial layer. In some embodiments, the barrier layer comprises a self-assembled monolayer. In some embodiments, the step of selectively depositing the first work function layer further comprises: forming a patterned mask layer on a first portion of the barrier layer, the first portion being disposed around the second semiconductor layer. In some embodiments, the step of selectively depositing the first work function layer further comprises: removing a second portion of the barrier layer, the second portion being disposed on the first portion of the sacrificial layer. In some embodiments, the step further comprises: removing the patterned mask layer by a plasma ashing process.

[0103] Other embodiments are methods for forming a semiconductor device structure. The method includes the following steps: forming a first fin structure in an NMOS region of a substrate and a second fin structure in a PMOS region, the first fin structure including a plurality of first semiconductor layers and the second fin structure including a plurality of second semiconductor layers. The method further includes the following steps: depositing a gate dielectric layer around a portion of each of the plurality of first and second semiconductor layers in the NMOS and PMOS regions; depositing a sacrificial layer on the gate dielectric layer in the NMOS and PMOS regions; forming a barrier layer on the sacrificial layer in the PMOS region; removing the sacrificial layer in the NMOS region to expose the gate dielectric layer in the NMOS region; selectively depositing an n-type work function layer on the exposed gate dielectric layer in the NMOS region; depositing a p-type work function layer over the n-type work function layer in the NMOS region and over the gate dielectric layer in the PMOS region; and depositing a body metal filler over the p-type work function layer.

[0104] In some embodiments, the sacrificial layer comprises a metal oxide. In some embodiments, the metal oxide comprises aluminum oxide. In some embodiments, the n-type work function layer comprises TiAlC, and the p-type work function layer comprises TiN. In some embodiments, the barrier layer comprises a self-assembled monolayer. In some embodiments, the process further includes: etching back the sacrificial layer before forming the barrier layer. In some embodiments, the thickness of the sacrificial layer ranges from about 2.5 nm to about 4 nm before etching back, and the thickness is reduced to about 1.2 nm to about 1.8 nm after etching back. In some embodiments, the process further includes: removing the sacrificial layer in the PMOS region before depositing the p-type work function layer.

[0105] Other embodiments are semiconductor device structures. The structure includes: a first semiconductor layer disposed in an NMOS region of a substrate; a second semiconductor layer disposed in a PMOS region of the substrate; a gate dielectric layer surrounding at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer; an n-type work function layer surrounding the gate dielectric layer in the NMOS region; and a p-type work function layer surrounding the n-type work function layer in the NMOS region. The p-type work function layer surrounds the gate dielectric layer in the PMOS region and does not contain aluminum. The structure further includes: a body metal filler disposed on the p-type work function layer in both the NMOS and PMOS regions.

[0106] In some embodiments, the n-type work function layer comprises TiAlC, and the p-type work function layer comprises TiN. In some embodiments, the p-type work function layer has: a first portion disposed on a horizontal surface of the gate dielectric layer in the PMOS region; a second portion disposed on a vertical surface of the gate dielectric layer in the PMOS region; a third portion disposed on a horizontal surface of the n-type work function layer; and a fourth portion disposed on a vertical surface of the n-type work function layer. In some embodiments, the first portion has a first thickness, the second portion has a second thickness, the third portion has a third thickness, and the fourth portion has a fourth thickness, and the first thickness is different from the second thickness.

[0107] According to some embodiments disclosed herein, a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor layer, a second semiconductor layer, a gate dielectric layer, an n-type work function layer, a p-type work function layer, and a body metal filler. The first semiconductor layer is disposed in an n-type metal-oxide-semiconductor region of a substrate. The second semiconductor layer is disposed in a p-type metal-oxide-semiconductor region of the substrate. The gate dielectric layer surrounds at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer. The n-type work function layer surrounds the gate dielectric layer in the n-type metal-oxide-semiconductor region. The p-type work function layer surrounds the n-type work function layer in the n-type metal-oxide-semiconductor region. The p-type work function layer surrounds the gate dielectric layer in the p-type metal-oxide-semiconductor region. The body metal filler is disposed on the n-type metal-oxide-semiconductor region and the p-type work function layer in the p-type metal-oxide-semiconductor region.

[0108] In some embodiments, the p-type work function layer includes a first portion and a second portion. The first portion is disposed on a horizontal surface of the gate dielectric layer in the p-type metal-oxide-semiconductor region. The second portion is disposed on a vertical surface of the gate dielectric layer in the p-type metal-oxide-semiconductor region. The first portion has a first thickness, and the second portion has a second thickness, wherein the first thickness and the second thickness are different. In some embodiments, the p-type work function layer includes a third portion and a fourth portion. The third portion is disposed on a horizontal surface of the n-type work function layer. The fourth portion is disposed on a vertical surface of the n-type work function layer. The third portion has a third thickness, and the fourth portion has a fourth thickness, wherein the fourth thickness is greater than the third thickness.

[0109] According to some embodiments disclosed herein, a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor layer, a second semiconductor layer, a gate dielectric layer, a first work function layer, a second work function layer, a body metal filler, and an interface layer. The first semiconductor layer is disposed in a first region of a substrate. The second semiconductor layer is disposed in a second region of the substrate. The gate dielectric layer surrounds the first semiconductor layer and the second semiconductor layer. The first work function layer surrounds the gate dielectric layer in the first region. The second work function layer is disposed around the first work function layer in the first region, wherein the second work function layer surrounds the gate dielectric layer in the second region. The body metal filler is disposed on the second work function layer in the first region and the second region. The interface layer is located between the first semiconductor layer and the gate dielectric layer and between the second semiconductor layer and the gate dielectric layer.

[0110] In some embodiments, the second work function layer has a first portion and a second portion. The first portion is disposed on a horizontal surface of the first work function layer. The second portion is disposed on a horizontal surface of the gate dielectric layer in the second region. The first portion has a first thickness, the second portion has a second thickness, and the first thickness is greater than the second thickness.

[0111] According to some embodiments disclosed herein, a semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and source / drain regions. The first gate structure includes a first semiconductor layer, a first gate dielectric layer, and a first gate electrode. The first gate dielectric layer surrounds the first semiconductor layer. The first gate electrode includes a first work function layer, a second work function layer, and a body metal filler. The first work function layer surrounds the first gate dielectric layer in a first region. A second work function layer is disposed around the first work function layer in the first region, such that the first work function layer is located between the second work function layer and the first gate dielectric layer. The body metal filler is disposed on the second work function layer. A second gate structure is disposed in a second region of a substrate, the second region being adjacent to the first region. The second gate structure includes a second semiconductor layer, a second gate dielectric layer, and a second gate electrode. The second gate dielectric layer surrounds the second semiconductor layer. The second gate electrode includes a second work function layer and a body metal filler. The second work function layer surrounds the second gate dielectric layer in the second region, wherein the second work function layer and the second gate dielectric layer are in direct contact. The body metal filler is disposed on the second work function layer. The source / drain regions are adjacent to the first gate structure and the second gate structure.

[0112] In some embodiments, the semiconductor device structure includes a dielectric spacer. The dielectric spacer is located between a first gate structure and a source / drain region, and between a second gate structure and a source / drain region.

[0113] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, characterized in that, Include: A first semiconductor layer is disposed in an n-type metal-oxide-semiconductor region of a substrate; A second semiconductor layer is disposed in a p-type metal-oxide-semiconductor region of the substrate; A gate dielectric layer surrounds at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer; An n-type work function layer, the gate dielectric layer surrounding the n-type metal-oxide-semiconductor region; A p-type work function layer is disposed around the n-type work function layer in the n-type metal-oxide-semiconductor region, wherein the p-type work function layer surrounds the gate dielectric layer of the p-type metal-oxide-semiconductor region; and A main metal filler is disposed on the p-type work function layer in the n-type metal-oxide-semiconductor region and the p-type metal-oxide-semiconductor region.

2. The semiconductor device structure as described in claim 1, characterized in that, This p-type work function layer has: A first part is disposed on a horizontal surface of the gate dielectric layer in the p-type metal-oxide-semiconductor region; and A second part is disposed on a vertical surface of the gate dielectric layer in the p-type metal-oxide-semiconductor region.

3. The semiconductor device structure as described in claim 2, characterized in that, The first part has a first thickness, the second part has a second thickness, and the first thickness is different from the second thickness.

4. The semiconductor device structure as described in claim 1, characterized in that, This p-type work function layer has: A third part is disposed on a horizontal surface of the n-type work function layer; and The fourth part is set on a vertical surface of the n-type work function layer.

5. The semiconductor device structure as described in claim 4, characterized in that, The third part has a third thickness, the fourth part has a fourth thickness, and the fourth thickness is greater than the third thickness.

6. A semiconductor device structure, characterized in that, Include: A first semiconductor layer is disposed in a first region of a substrate; A second semiconductor layer is disposed in a second region of the substrate; A gate dielectric layer surrounds the first semiconductor layer and the second semiconductor layer; A first work function layer, and the gate dielectric layer surrounding the first region; A second work function layer is disposed around the first work function layer in the first region, wherein the second work function layer surrounds the gate dielectric layer in the second region; A main metal filler is disposed on the second work function layer in the first region and the second region; and An interface layer is located between the first semiconductor layer and the gate dielectric layer and between the second semiconductor layer and the gate dielectric layer.

7. The semiconductor device structure as described in claim 6, characterized in that, The second work function layer has: A first part is disposed on a horizontal surface of the first work function layer; and A second part is disposed on a horizontal surface of the gate dielectric layer in the second region.

8. The semiconductor device structure as described in claim 7, characterized in that, The first part has a first thickness, the second part has a second thickness, and the first thickness is greater than the second thickness.

9. A semiconductor device structure, characterized in that, Include: A first gate structure is disposed in a first region of a substrate, comprising: A first semiconductor layer; A first gate dielectric layer surrounds the first semiconductor layer; and A first gate electrode, comprising: A first work function layer surrounding the first gate dielectric layer in the first region; A second work function layer is disposed around the first work function layer in the first region, such that the first work function layer is located between the second work function layer and the first gate dielectric layer; and A main metal filler is disposed on the second work function layer; and A second gate structure is disposed in a second region of the substrate, the second region being adjacent to the first region, the second gate structure comprising: A second semiconductor layer; A second gate dielectric layer surrounds the second semiconductor layer; and A second gate electrode, comprising: The second work function layer surrounds the second gate dielectric layer in the second region, wherein The second work function layer is in direct contact with the second gate dielectric layer; and The main metal filler is disposed on the second work function layer; and A source / drain region is adjacent to the first gate structure and the second gate structure.

10. The semiconductor device structure as claimed in claim 9, characterized in that, Further includes: A dielectric spacer is located between the first gate structure and the source / drain region, and between the second gate structure and the source / drain region.

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