Ultra-low capacitance esd protection device

Abstract

The utility model provides a kind of ESD protection device of ultralow capacitance.The device, first epitaxial layer and second epitaxial layer are stacked in substrate in turn, buried layer is between first epitaxial layer and second epitaxial layer, first doped region extends from the surface of second epitaxial layer to second epitaxial layer, second doped region extends from the surface of the first doped region of first region to the first doped region of first region, third doped region extends from the surface of the first doped region of first region to the first doped region of first region, third doped region and second doped region are separated from each other, fourth doped region extends from the surface of the first doped region of second region to the first doped region of second region, substrate, first epitaxial layer, second epitaxial layer, second doped region are first doped type, buried layer, first doped region, third doped region, fourth doped region are second doped type.ESD protection device can reduce device capacitance value while ensuring low clamping voltage in this way.

Description

Technical Field

[0001] This utility model relates to the field of electronic components technology, and in particular to an ultra-low capacitance ESD protection device. Background Technology

[0002] As electronic chips evolve towards smaller size, higher density, and lower power consumption, integrated circuits are becoming increasingly smaller in area. Consequently, they are becoming more sensitive to electrostatic discharge (ESD), which can easily damage electronic devices, especially at the interfaces of some electronic products. To protect sensitive electronic components from ESD events, ESD protection devices are being used more and more extensively.

[0003] ESD protection devices typically use ordinary PN diodes, but ordinary diodes have relatively large capacitance values ​​(usually between tens and hundreds of picofarads) and high clamping voltages, making them unsuitable for high-speed signal lines and low-voltage equipment. To achieve high-speed communication, diode capacitance needs to be reduced. Common approaches include reducing the PN diode area or increasing the reverse breakdown voltage, but either method leads to a decrease in ESD immunity. When two diodes are connected in series, their combined capacitance decreases. Therefore, methods to reduce capacitance by connecting two diodes in series through packaging or chip integration have begun to be used. However, this method requires a large area and is costly, making it unsuitable for small packages. For this reason, bipolar junction transistors (BJTs) have also begun to be used as ESD protection devices. However, BJT-structured ESD protection devices still have insufficient capacitance for high-speed communication, and are prone to deep flyback latch-up due to amplification gain limitations. Utility Model Content

[0004] One of the objectives of this invention is to provide an ultra-low capacitance ESD protection device that can reduce the device capacitance value while ensuring a low clamping voltage, and can avoid the latch-up effect caused by the large sweep of BJT structure transistors.

[0005] To achieve the above objectives, the ultra-low capacitance ESD protection device provided by this utility model includes one or more cells, each cell comprising: a substrate, wherein the substrate is of a first doping type; a first epitaxial layer, wherein the first epitaxial layer is located on the substrate and is of a first doping type; a buried layer, wherein the buried layer is located on a portion of the first epitaxial layer and is of a second doping type; a second epitaxial layer, wherein the second epitaxial layer is located on the portion of the first epitaxial layer not covered by the buried layer and the buried layer, and the second epitaxial layer is of a first doping type; a first doped region, wherein the first doped region extends from the surface of the second epitaxial layer into the second epitaxial layer and is of a second doping type; and a plurality of isolation structures, wherein the isolation structures extend from the surface of the second epitaxial layer. The isolation structure extends into the first epitaxial layer, with a portion of the isolation structure passing through the buried layer to form a first region, and a portion of the isolation structure not passing through the buried layer to form a second region; a second doped region extends from the surface of the first doped region in the first region to the first doped region in the first region, and the second doped region is of a first doping type; a third doped region extends from the surface of the first doped region in the first region to the first doped region in the first region, and the third doped region is of a second doping type, and the third doped region is separated from the second doped region; a fourth doped region extends from the surface of the first doped region in the second region to the first doped region in the second region, and the fourth doped region is of a second doping type.

[0006] Optionally, the isolation structure includes four isolation structures: the buried layer, the second epitaxial layer, and the first doped region between the first isolation structure and the second isolation structure, the first isolation structure, and the second isolation structure form the first region; the second epitaxial layer and the first doped region between the third isolation structure and the fourth isolation structure, the third isolation structure, and the fourth isolation structure form the second region.

[0007] Optionally, the doping concentration of the first epitaxial layer is less than the doping concentration of the substrate and the second doped region, the doping concentration of the first epitaxial layer is greater than the doping concentration of the third doped region, and the doping concentration of the buried layer is greater than the doping concentration of the first doped region.

[0008] Optionally, the width of the second doped region is smaller than the width of the third doped region.

[0009] Optionally, the width of the second doped region is smaller than the width of the fourth doped region.

[0010] Optionally, the width of the second doped region is smaller than the width of the fourth doped region and smaller than the width of the third doped region.

[0011] Optionally, the depth of the second doped region is less than the depth of the third doped region and less than the depth of the fourth doped region, wherein the depths of the third doped region and the fourth doped region are equal.

[0012] Optionally, the third doped region is located within the second epitaxial layer and on top of the first doped region, and the doping concentration of the third doped region is greater than the doping concentration of the first doped region.

[0013] Optionally, the first epitaxial layer covers the front side of the substrate; the second epitaxial layer has a front metal layer, and the ultra-low capacitance ESD protection device further includes a back metal layer located on the back side of the substrate.

[0014] Optionally, the second epitaxial layer has an interlayer dielectric layer, the interlayer dielectric layer having a first contact hole corresponding to the location of the second doped region and a second contact hole corresponding to the location of the fourth doped region, the front metal layer being located on the interlayer dielectric layer and filling the first contact hole and the second contact hole.

[0015] Optionally, the series circuit formed by the second doped region, the first doped region, the second epitaxial layer below the first doped region, the buried layer, and the first epitaxial layer in the first region is connected in parallel with the second reverse diode formed by connecting the first doped region and the second epitaxial layer below the first doped region in the second region.

[0016] Optionally, multiple cells are arranged in parallel in sequence. The substrate has multiple first regions and multiple second regions, with one first region corresponding to one second region. The second doped region of the first region and the fourth doped region in the corresponding second region are interconnected. The ultra-low capacitance ESD protection device has multiple first input / output ports, with one first input / output port connected to one second doped region and one corresponding fourth doped region.

[0017] Optionally, the second doped region and the first doped region are connected to form a first forward diode, the first doped region and the second epitaxial layer below the first doped region are connected to form a first reverse diode, the second epitaxial layer below the first doped region and the buried layer are connected to form a second forward diode, the first epitaxial layer and the buried layer are connected to form a Zener diode, and the first forward diode, the first reverse diode, the second forward diode and the Zener diode are connected in series.

[0018] Optionally, the ultra-low capacitance ESD protection device has a first input / output port and a second input / output port, the second doped region and the fourth doped region are both connected to the first input / output port, and the substrate is connected to the second input / output port.

[0019] Optionally, when the first input / output port is connected to a high potential and the second input / output port is connected to a low potential, the current flows into the ESD protection device through the front metal layer. In the first region, the current reaches the second input / output port through the first forward diode, the first reverse diode, the transistor composed of the second forward diode and the Zener diode, and the substrate.

[0020] In the ultra-low capacitance ESD protection device provided by this invention, the second epitaxial layer, the buried layer, and the first epitaxial layer below the first doped region can be connected to form two diodes, and these two diodes can be combined to form a vertical transistor. This vertical transistor has a lower capacitance than a single diode. The second doped region, the first doped region, and the second epitaxial layer below the first doped region can be connected to form two diodes connected in series with the vertical transistor. The area of ​​the second doped region is smaller than that of the other doped regions. The smaller area of ​​the second doped region determines the final capacitance of the entire ESD protection device, which can further reduce the capacitance of the ESD protection device and meet the requirements of higher speed signal communication. The circuit imposes stringent requirements on ESD protection devices. By setting the concentration and positional relationship of the second epitaxial layer below the first doped region, the first doped region, and the buried layer, the low operating voltage and low clamping voltage of the ESD protection device during ESD events are ensured. Due to the presence of the highly doped buried layer, the gain of the vertical transistor is very small, and the vertical transistor operates in the shallow scan region, avoiding the latch-up effect caused by the large scan of conventional transistors. The first epitaxial layer, the buried layer, the second epitaxial layer below the first doped region, and the first to second doped regions are stacked sequentially on the substrate, resulting in a smaller chip area occupied by the ESD protection device, which can meet the miniaturization requirements of the chip. Attached Figure Description

[0021] Figure 1 A schematic diagram of the structure of an ultra-low capacitance ESD protection device provided in an embodiment of this utility model.

[0022] Figure 2 This is a schematic diagram of the internal circuit of an ESD protection device with unidirectional single-channel ultra-low capacitance provided in an embodiment of the present invention.

[0023] Figure 3 A circuit diagram of an ESD protection device with unidirectional single-channel ultra-low capacitance provided in an embodiment of this utility model.

[0024] Figure 4 A circuit diagram of an ultra-low capacitance ESD protection device with unidirectional four channels provided in an embodiment of this utility model.

[0025] Figures 5 to 9 This is a schematic diagram illustrating the manufacturing process of an ultra-low capacitance ESD protection device provided in one embodiment of the present invention.

[0026] Figure descriptions: 10-Substrate; 21-First epitaxial layer; 22-Second epitaxial layer; 202-Buried layer; 204-First doped region; 205-Second doped region; 206-Third doped region; 207-Fourth doped region; 301-First isolation structure; 302-Second isolation structure; 303-Third isolation structure; 304-Fourth isolation structure; 41-First dielectric layer; 42-Interlayer dielectric layer; 401-First contact hole; 402-Second contact hole; 51-Front-side metal layer; 52-Back-side metal layer. Detailed Implementation

[0027] The ultra-low capacitance ESD protection device proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0028] Figure 1 This is a schematic diagram of the structure of an ultra-low capacitance ESD protection device provided in one embodiment of the present invention. Figure 1As shown, the ultra-low capacitance ESD protection device (hereinafter referred to as "ESD protection device") provided in this application includes one or more cells, wherein the cells include a substrate 10, a first epitaxial layer 21, a buried layer 202, a second epitaxial layer 22, a first doped region 204, several isolation structures, a second doped region 205, a third doped region 206 and a fourth doped region 207. Substrate 10 is of a first doping type; a first epitaxial layer 21 is located on substrate 10, and the first epitaxial layer 21 is of the first doping type; a buried layer 202 is located on a portion of the first epitaxial layer 21, and the buried layer 202 is of the second doping type 202; a second epitaxial layer 22 is located on the first epitaxial layer 21 and the buried layer 202 not covered by the buried layer 202, and the second epitaxial layer 22 is of the first doping type; a first doped region 204 extends from the surface of the second epitaxial layer 22 into the second epitaxial layer 22, and the first doped region 204 is of the second doping type; several isolation structures extend from the surface of the first doped region 204 into the first epitaxial layer 21, some of the isolation structures pass through the buried layer 202 and form a first region I, and some isolation... The structure does not penetrate the buried layer 202 and forms a second region II; a second doped region 205 extends from the surface of the first doped region 204 in the first region I into the first doped region 204 in the first region I, and the second doped region 205 is of the first doping type; a third doped region 206 extends from the surface of the first doped region 204 in the first region I into the first doped region 204 in the first region I, and the third doped region 206 is of the second doping type, and the third doped region 206 is separated from the second doped region 205; a fourth doped region 207 extends from the surface of the first doped region 204 in the second region II into the first doped region 204 in the second region II, and the fourth doped region 207 is of the second doping type.

[0029] In this embodiment, the doping concentration of the first epitaxial layer 21 is less than the doping concentration of the substrate 10 and the second doped region 205, and the doping concentration of the first epitaxial layer 21 is greater than the doping concentration of the second epitaxial layer 22 below the first doped region 204.

[0030] The doping concentration of the buried layer 202 is greater than the doping concentration of the first doped region 204.

[0031] For example, the projected area of ​​the second doped region 205 on the substrate 10 is smaller than the projected area of ​​the first epitaxial layer 21, the buried layer 202 and the first doped region 204 on the substrate 10.

[0032] The following description uses P-type as the first conductivity type and N-type as the second conductivity type as an example. However, in some other embodiments of this application, the first conductivity type can be N-type and the second conductivity type can be P-type.

[0033] Specifically, the substrate 10 may be made of materials including but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors.

[0034] In this embodiment, the substrate 10 can be a P+ type low-resistivity substrate, and the resistivity of the substrate 10 can be greater than or equal to 0.001 Ω·cm and less than or equal to 0.09 Ω·cm, but is not limited thereto.

[0035] The first epitaxial layer 21 is located on the substrate 10, and the first epitaxial layer 21 can cover the front side of the substrate 10. The material of the first epitaxial layer 21 includes, but is not limited to, silicon. The thickness of the first epitaxial layer 21 can be greater than or equal to 5µm and less than or equal to 15µm, but is not limited thereto.

[0036] The buried layer 202 is located on a portion of the first epitaxial layer 21. For example, the original first epitaxial layer 21 can be entirely used as a P-type well region, and an N+ type buried layer 202 is subsequently formed by implanting N-type dopant into a portion of the top region of the first epitaxial layer 21. The N-type dopant of the buried layer 202 includes, but is not limited to, antimony, arsenic, and / or phosphorus. The buried layer 202 is in contact with the first epitaxial layer 21.

[0037] In this embodiment, the first epitaxial layer 21 and the substrate 10 have the same conductivity type, and the P-type doping concentration of the first epitaxial layer 21 is less than the P-type doping concentration of the substrate 10. For example, the resistivity of the first epitaxial layer 21 can be greater than or equal to 0.01 Ω·cm and less than or equal to 0.09 Ω·cm, but is not limited thereto.

[0038] The second epitaxial layer 22 is located on the first epitaxial layer 21 and covers the buried layer 202. The material of the second epitaxial layer 22 includes, but is not limited to, silicon. The thickness of the second epitaxial layer 22 can be greater than or equal to 5µm and less than or equal to 20µm, but is not limited thereto.

[0039] The second epitaxial layer 22 has a first doped region 204, which extends from the surface of the second epitaxial layer 22 into the second epitaxial layer 22.

[0040] In this embodiment, several isolation structures extend from the surface of the second epitaxial layer 22 into the first epitaxial layer 21.

[0041] like Figure 1As shown, the isolation structures may include a first isolation structure 301, a second isolation structure 302, a third isolation structure 303, and a fourth isolation structure 304. The first and second isolation structures 301 and 302 both penetrate the buried layer 202 and define a first region I. The third and fourth isolation structures 303 and 304 do not penetrate the buried layer 202 and define a second region II. The buried layer 202, the second epitaxial layer 22, and the first doped region 204 between the first and second isolation structures 301 and 302 are located within the first region I. The second doped region 205 and the third doped region 206 are also located within the first region I. The second epitaxial layer 22 and the first doped region 204 between the third and fourth isolation structures 303 and 304 are located within the second region II. The fourth doped region 207 is also located within the second region II. By using isolation structures that penetrate the second epitaxial layer 22 and extend into the first epitaxial layer 21, the chip can be divided into multiple independent regions, avoiding the parasitic effects of active regions on device performance and improving chip area utilization.

[0042] In this embodiment, the area of ​​the buried layer 202 is larger than the area of ​​the first region I in which it is located, but the buried layer 202 does not extend into the second region II. The portion of the buried layer 202 that extends beyond the first region I and the portion located within the first region I can be separated by the isolation structure 30.

[0043] In one embodiment of this application, the isolation structure may include a trench, an insulating oxide layer covering the inner surface of the trench, and undoped polysilicon located on the insulating oxide layer and filling the trench. In another embodiment of this application, the trench within the isolation structure may be filled with an insulating oxide layer and / or an insulating material such as silicon nitride.

[0044] Continue to refer to Figure 1 As shown, the first epitaxial layer 21, the first doped region 204, and the second epitaxial layer below the first doped region 204 all cover the first region I and the second region II, and can also cover the region between the first region I and the second region II. The diode formed by the second epitaxial layer below the first doped region 204 in the second region II and the structure formed by the first epitaxial layer 21 to the second doped region 205 in the first region I are connected in parallel between the two input and output ports of the ESD protection device.

[0045] The fourth doped region 207 is of the second conductivity type and has a doping concentration greater than that of the first doped region 204. The fourth doped region 207 is used to reduce the lead-out resistance of the first doped region 204 in the second region II. The second doped region 205 and the fourth doped region 207 are connected by a front metal layer 51 located on the second epitaxial layer 22.

[0046] refer to Figure 1As shown, the buried layer 202 is an N+ type buried layer located between the first epitaxial layer 21 and the second epitaxial layer 22.

[0047] In this embodiment, the second epitaxial layer below the first doped region 204 is a P-type doped region. The doping concentration of the second epitaxial layer below the first doped region 204 is less than the doping concentration of the first epitaxial layer 21 and less than the doping concentration of the substrate 10. The P-type dopant material of the second epitaxial layer below the first doped region 204 and the first epitaxial layer 21 can be the same, but is not limited to this.

[0048] For example, such as Figure 1 As shown, the projected areas of the first epitaxial layer 21 and the second epitaxial layer 22 on the substrate 10 can be the same, and the projected areas of the first epitaxial layer 21 and the second epitaxial layer 22 on the substrate 10 are both greater than the projected area of ​​the buried layer 202 on the substrate 10.

[0049] The first doped region 204 can be an N-type doped region, and the N-type doping concentration of the first doped region 204 is less than the N-type doping concentration of the buried layer 202. The projected areas of the second epitaxial layer 22, the first epitaxial layer 21, and the first doped region 204 on the substrate 10 can be the same, but are not limited to this.

[0050] The second doped region 205 can be a P+ type doped region. The doping concentration of the second doped region 205 is greater than the doping concentration of the second epitaxial layer 22 below the first doped region 204 and greater than the doping concentration of the first epitaxial layer 21. The projected area of ​​the second epitaxial layer, the first epitaxial layer 21, the buried layer 202, and the first doped region 204 on the substrate 10 is greater than the projected area of ​​the second doped region 205 on the substrate 10. The second doped region 205, which has the smallest area in the first region I and the second region II, determines the final capacitance of the entire ESD protection device. Setting the second doped region 205 can significantly reduce the capacitance of the ESD protection device.

[0051] like Figure 1 As shown, the third doped region 206 has a second conductivity type and a doping concentration greater than that of the first doped region 204, meaning the third doped region 206 can be an N+ doped region. The third doped region 206 is connected to the first doped region 204. The third doped region 206 acts as a current shunt during the operation of the ESD protection device, resulting in a more uniform current distribution and improved IPP capability. This compensates for the reduced IPP caused by the small diode area between the second doped region 205 and the first doped region 204.

[0052] In this embodiment, the third doped region 206 and the second doped region 205 are spaced apart, i.e., separated from each other. Specifically, the third doped region 206 and the second doped region 205 can be separated by a portion of the first doped region 204. The projected area of ​​the third doped region 206 on the substrate 10 can be larger than the projected area of ​​the second doped region 205 on the substrate 10.

[0053] refer to Figure 1 As shown, the width of the second doped region 205 is smaller than the width of the third doped region 206. The width of the second doped region 205 is smaller than the width of the fourth doped region 207. The width of the second doped region 205 is smaller than the width of the fourth doped region 207 and smaller than the width of the third doped region 206. The depth of the second doped region 205 is smaller than the depth of the third doped region 206 and smaller than the depth of the fourth doped region 207, while the depths of the third doped region 206 and the fourth doped region 207 can be equal.

[0054] For example, the thickness of the front metal layer 51 may be greater than or equal to 1 µm and less than or equal to 8 µm, but is not limited thereto. The front metal layer 51 may include a front metal electrode.

[0055] like Figure 1 As shown, the second epitaxial layer 22 has an interlayer dielectric layer 42, which has a first contact hole 401 corresponding to the position of the second doped region 205 and a second contact hole 402 corresponding to the position of the fourth doped region 207. The front metal layer 51 is located on the interlayer dielectric layer 42 and fills the first contact hole 401 and the second contact hole 402.

[0056] like Figure 1 As shown, the ultra-low capacitance ESD protection device may further include a back metal layer 52 located on the back side of the substrate 10. The thickness of the back metal layer 52 may be greater than or equal to 0.5µm and less than or equal to 5µm, but is not limited thereto. The back metal layer 52 may include a back metal electrode.

[0057] The ultra-low capacitance ESD protection device also has a first input / output port I / O1 and a second input / output port I / O2. The second doped region 205 and the fourth doped region 207 are both connected to the first input / output port I / O1 through the front metal layer 51, and the substrate 10 is connected to the second input / output port I / O2 through the back metal layer 52.

[0058] Figure 2 This is a schematic diagram of the internal circuit of an ESD protection device with unidirectional single-channel ultra-low capacitance provided in an embodiment of the present invention. Figure 3 A circuit diagram of an ultra-low capacitance ESD protection device with unidirectional single-channel design, provided as an embodiment of the present invention. In this embodiment of the ultra-low capacitance ESD protection device, reference... Figure 2 and Figure 3 As shown, in the first region I, the second doped region 205 and the first doped region 204 are connected to form a first forward diode D1. The first doped region 204 and the second epitaxial layer below the first doped region 204 are connected to form a first reverse diode D2. The second epitaxial layer below the first doped region 204 and the buried layer 202 are connected to form a second forward diode D3. The first epitaxial layer 21 and the buried layer 202 are connected to form a Zener diode D4. The first forward diode D1, the first reverse diode D2, the second forward diode D3 and the Zener diode D4 are connected in series. The second forward diode D3 and the Zener diode D4 are connected to form a vertical transistor.

[0059] refer to Figure 1 and Figure 3 As shown, in the second region II, the first doped region 204 and the second epitaxial layer below the first doped region 204 are connected to form the second reverse diode D5. The second doped region 205, the first doped region 204, the second epitaxial layer below the first doped region 204, the buried layer 202 and the first epitaxial layer 21 in the first region I are connected to form a series circuit including D1, D2, D3 and D4, which is connected in parallel with D5.

[0060] refer to Figure 2 and Figure 3 As shown, when the first input / output port I / O1 on the front side is connected to a high potential and the second input / output port I / O2 on the back side is connected to a low potential, current flows into the ESD protection device through the front metal layer 51. In the first region I, the current flows through the first forward diode D1, the first reverse diode D2, the transistor composed of D3 and D4, and the substrate 10 to reach the second input / output port I / O2, thus achieving ESD protection. At this time, the operating voltage of the ESD protection device is jointly determined by the second doped region 205, the first doped region 204, the second epitaxial layer below the first doped region 204, the buried layer 202, the first epitaxial layer 21, and the substrate 10. D5 in the second region II is in a high-voltage state and is cut off and does not work.

[0061] Continue to refer to Figure 2 and Figure 3 As shown, when the first input / output port I / O1 on the front is connected to a low potential and the second input / output port I / O2 on the back is connected to a high potential, the structure composed of the second doped region 205, the first doped region 204, the second epitaxial layer below the first doped region 204, the buried layer 202, the first epitaxial layer 21 and the substrate 10 in the first region I is in a high voltage state and is cut off and does not work, while D5 in the second region II is in a forward conduction state.

[0062] Figure 4 A circuit diagram of an ultra-low capacitance ESD protection device with unidirectional four channels is provided as an embodiment of this utility model. (See diagram below.) Figure 4As shown, in some embodiments of this application, the ultra-low capacitance ESD protection device may also have multiple channels. Specifically, multiple cells are arranged in parallel in sequence, and the substrate 10 may have multiple first regions I and multiple second regions II. One first region I corresponds to one second region II, that is, one first region I and one second region II form a group. The doped regions in each first region I are arranged in the same way, and the doped regions in each second region II are arranged in the same way. The second doped region 205 in the first region I and the fourth doped region 207 in the same group of second regions II are interconnected through the front metal layer 51. The ultra-low capacitance ESD protection device may have multiple first input / output ports I / O1, and one first input / output port I / O1 connects one second doped region 205 and the fourth doped region 207 in the same group.

[0063] For example, the ultra-low capacitance ESD protection device provided in this application can be used to protect high-speed data interfaces, such as USB, DVI, and HDMI. The ultra-low capacitance ESD protection device can be used to protect sensitive components connected to data and transmission lines from electrostatic discharge (ESD) events and overvoltages caused by electrical fast transients (EFT).

[0064] This application also provides a method for manufacturing an ultra-low capacitance ESD protection device, which can be used to manufacture the aforementioned ultra-low capacitance ESD protection device.

[0065] Figures 5 to 9 This is a schematic diagram illustrating the fabrication process of an ultra-low capacitance ESD protection device according to an embodiment of the present invention. The following is in conjunction with... Figure 1 , Figures 5 to 9 The method for manufacturing the ultra-low capacitance ESD protection device provided in this application is described.

[0066] like Figure 5 As shown, a substrate 10 is provided, which is of a first conductivity type and has opposing front and back sides.

[0067] For example, the substrate 10 can be a P+ type low-resistivity substrate, and the resistivity of the substrate 10 can be greater than or equal to 0.001 Ω·cm and less than or equal to 0.09 Ω·cm, but is not limited thereto.

[0068] like Figure 5 As shown, a first epitaxial layer 21 with a first conductivity type is formed on the front side of the substrate 10 by an epitaxial process.

[0069] For example, the first epitaxial layer 21 can be a P-type epitaxial layer, that is, the first epitaxial layer 21 itself can serve as a well region with a first conductivity type, and the doping concentration of the first epitaxial layer 21 is less than the doping concentration of the substrate 10. The resistivity of the first epitaxial layer 21 can be greater than or equal to 0.01 Ω·cm and less than or equal to 0.09 Ω·cm, but is not limited thereto.

[0070] The thickness of the first epitaxial layer 21 can be greater than or equal to 5µm and less than or equal to 15µm, but is not limited to this.

[0071] like Figure 6 As shown, a buried layer 202 of the second conductivity type is formed on top of a portion of the first epitaxial layer 21 by an ion implantation process.

[0072] For example, an N-type dopant such as antimony, arsenic, or phosphorus can be implanted into the first epitaxial layer 21 to form a buried layer 202. The implanted N-type dopant inverts a portion of the top of the first epitaxial layer 21 into an N+ type. The implantation energy can be greater than or equal to 60 keV and less than or equal to 150 keV; the implantation dose can be greater than or equal to 1E14 cm⁻¹. -2 And less than or equal to 1E16cm -2 After the ion implantation process is completed, an annealing process at a temperature of 900℃~1250℃ can be used for 10min~50min to make the junction depth of the buried layer 202 greater than or equal to 0.5µm and less than or equal to 5µm.

[0073] like Figure 7 As shown, a second epitaxial layer 22 is formed on the first epitaxial layer 21 by an epitaxial process.

[0074] In this embodiment, the buried layer 202 is formed by antimony implantation, and the P-type dopant in the first epitaxial layer 21 is boron; the second epitaxial layer 22 is an N-type epitaxial layer, and the doping concentration in the second epitaxial layer 22 is less than the doping concentration in the buried layer 202. After the formation of the second epitaxial layer 22, in subsequent high-temperature processes such as annealing, due to the large atomic volume of antimony atoms and the slow high-temperature diffusion rate, the width of the N+ type buried layer 202 formed after antimony diffusion is very narrow, while the high-temperature diffusion rate of boron in the first epitaxial layer 21 under the buried layer 202 is very fast. Boron diffuses through the buried layer 202 through high-temperature diffusion and forms a P-type doped region in the second epitaxial layer 22 above the buried layer 202. That is, the part of the second epitaxial layer 22 close to the first epitaxial layer 21 is the first doped region of the first doping type, and the part far away from the first epitaxial layer 21 is the first doped region 204 of the second doping type. This ensures the device parameter performance while simplifying the process steps. Of course, the P-type doping concentration of the second epitaxial layer below the first doped region 204 is less than the P-type doping concentration of the first epitaxial layer 21.

[0075] In another embodiment of this application, arsenic or phosphorus implantation can be used to form the buried layer 202, and then a P-epitaxial layer can be formed on the first epitaxial layer 21 to form the second epitaxial layer below the first doped region 204. Then, N-epitaxial layer is formed on the P-epitaxial layer to form the second epitaxial layer 22 as the first doped region 204.

[0076] It should be noted that by using a double-layer epitaxial design, especially by forming a high-resistivity N-type second epitaxial layer 22 (more precisely, forming a high-resistivity N-type first doped region 204), the parasitic capacitance of the device can be reduced.

[0077] refer to Figure 8 As shown, multiple isolation structures are formed in the first epitaxial layer 21 and the second epitaxial layer 22. The multiple isolation structures may include a first isolation structure 301, a second isolation structure 302, a third isolation structure 303 and a fourth isolation structure 304. The first isolation structure 301 and the second isolation structure 302 define a first region I, and the third isolation structure 303 and the fourth isolation structure 304 define a second region II.

[0078] In one embodiment, the method for forming multiple isolation structures may include: forming a hard mask layer on the second epitaxial layer 22, the material of the hard mask layer including but not limited to SiO2; removing a portion of the hard mask layer to form a patterned hard mask layer, the patterned hard mask layer opening up the isolation structure formation region; using the patterned hard mask layer as a mask, dry etching the second epitaxial layer 22 and the first epitaxial layer 21 and stopping in the first epitaxial layer 21 to form multiple trenches; removing the patterned hard mask layer by a wet etching process or the like; forming an insulating oxide layer on the inner surface of the trenches by a thermal oxidation process or the like, for example, growing silicon dioxide on the inner surface of the trenches using a thermal oxidation process at a temperature of 900°C to 1250°C, the thickness of the silicon dioxide being, for example, 500 Å to 5000 Å; continuing to form polysilicon material on the substrate 10, the polysilicon material filling the trenches and covering the surface of the second epitaxial layer 22; removing the polysilicon material outside the trenches by a chemical mechanical polishing process or a dry etching process while retaining the polysilicon material inside the trenches to form isolation structures.

[0079] In one embodiment, when fabricating the isolation structure, the trench can be directly filled with an insulating oxide layer to form the isolation structure.

[0080] refer to Figure 8 As shown, the second epitaxial layer below the first epitaxial layer 21 and the first doped region 204, as well as the first doped region 204, both cover the first region I and the second region II and can cover the region between the first region I and the second region II. The second epitaxial layer below the first doped region 204 in the first region I and the second region II are both isolated by the isolation structure.

[0081] The area of ​​the buried layer 202 is larger than the area of ​​the first region I, but the buried layer 202 does not extend into the second region II. The part of the buried layer 202 that extends beyond the first region I and the part that is located in the first region I can be separated by an isolation structure.

[0082] refer to Figure 9 As shown, after forming multiple isolation structures 30, a second doped region 205, a third doped region 206 and a fourth doped region 207 are formed on top of the second epitaxial layer 22.

[0083] For details, please refer to Figure 8 and Figure 9 As shown, a first dielectric layer 41 is formed on the second epitaxial layer 22. The material of the first dielectric layer 41 includes, but is not limited to, silicon dioxide, and the thickness of the first dielectric layer 41 is, for example, 5000 Å to 30000 Å. The first dielectric layer 41 is selectively etched to expose the formation regions of the second doped region 205, the third doped region 206, and the fourth doped region 207. Under the protection of the first dielectric layer 41 and the first patterned photoresist layer, a P+ type second doped region 205 is formed on the top of the second epitaxial layer 22 by ion implantation. The first patterned photoresist layer is removed. A second patterned photoresist layer is formed on the first dielectric layer 41. Under the protection of the first dielectric layer 41 and the second patterned photoresist layer, an N+ type third doped region 206 and a fourth doped region 207 are formed on the top of the second epitaxial layer 22 by ion implantation. The second patterned photoresist layer and the first dielectric layer 41 are removed. Removing the first dielectric layer 41 provides a flat growth surface for the subsequently formed interlayer dielectric layer, facilitating subsequent processes.

[0084] For example, an N+ type third doped region 206 and a fourth doped region 207 can be formed in the second epitaxial layer 22 using an antimony, phosphorus, or arsenic implantation process. The implantation energy can be 60 keV to 150 keV, and the implantation dose can be 2E14cm. -2 ~2E16cm -2 After the ion implantation process to form the third doped region 206 and the fourth doped region 207 is completed, an annealing process at a temperature of 900℃~1250℃ can be used to diffuse the third doped region 206 and the fourth doped region 207 within the second epitaxial layer 22, forming the third doped region 206 and the fourth doped region 207 with a junction depth of 1µm~10µm.

[0085] For example, a P+ type second doped region 205 can be formed on top of the second epitaxial layer 22 using BF2 implantation, wherein the implantation energy can be 80 keV to 150 keV and the implantation dose can be 2E14cm. -2 ~2E16cm -2However, this is not the only possibility. After the ion implantation process forming the second doped region 205, a high-temperature annealing process at a temperature of 800°C to 1000°C can be used to advance the junction depth between the second doped region 205 and the first doped region 204. For example, the depth of the second doped region 205 is less than the depth of the third doped region 206 and the fourth doped region 207.

[0086] refer to Figure 9 As shown, the second doped region 205 and the third doped region 206 are formed in the first region I, and the fourth doped region 207 is formed in the second region II; the second doped region 205, the third doped region 206 and the fourth doped region 207 can all be formed by replacing part of the first doped region 204.

[0087] Next, refer to Figure 9 As shown, a second dielectric layer is formed on the second epitaxial layer 22. The second dielectric layer is selectively etched to form a first contact hole 401 that exposes the second doped region 205 and a second contact hole 402 that exposes the fourth doped region 207. At this time, the second dielectric layer serves as an interlayer dielectric layer 42.

[0088] In another embodiment of this application, after forming the second doped region 205, the third doped region 206 and the fourth doped region 207, the first dielectric layer 41 may not be removed. Instead, a second dielectric layer covering the first dielectric layer 41 may be formed directly on the first dielectric layer 41, and then the second dielectric layer may be etched to form the first contact hole 401 and the second contact hole 402. In this case, the first dielectric layer 41 and the second dielectric layer together serve as the interlayer dielectric layer 42.

[0089] For example, the thickness of the interlayer dielectric layer 42 can be 3000 Å to 8000 Å, but is not limited thereto.

[0090] like Figure 1 As shown, a front metal layer 51 is formed on the front side of the substrate 10. The front metal layer 51 is located on the interlayer dielectric layer 42 and fills the first contact hole 401 and the second contact hole 402. The front metal layer 51 connects the second doped region 205 and the fourth doped region 207.

[0091] Specifically, the method for forming the front metal layer 51 may include: growing a front metal material layer on the interlayer dielectric layer 42, and etching the front metal material layer by wet etching or dry etching process to form a front metal layer 51 including a front metal electrode.

[0092] For example, the thickness of the front metal layer 51 can be 1µm to 8µm, but is not limited thereto.

[0093] After the front metal layer is formed, a passivation layer can be formed on the front metal layer 51 as needed to protect the front metal layer 51.

[0094] Subsequently, the substrate 10 can be thinned on the back side, and then a back metal layer 52 can be grown on the back side of the substrate 10 as a back metal electrode. For example, the thickness of the back metal layer 52 can be 0.5µm to 5µm, but is not limited thereto.

[0095] In the ultra-low capacitance ESD protection device provided by this utility model, the second epitaxial layer, the buried layer 202, and the first epitaxial layer 21 below the first doped region 204 can be connected to form two diodes, and these two diodes can be combined to form a vertical transistor. This vertical transistor has a lower capacitance than a single diode. The second doped region 205, the first doped region 204, and the second epitaxial layer below the first doped region 204 can be connected to form two diodes connected in series with the vertical transistor. The area of ​​the second doped region 205 is smaller than that of the other doped regions. The smaller area of ​​the second doped region 205 determines the final capacitance of the entire ESD protection device, which can further reduce the capacitance of the ESD protection device and meet the requirements of higher speed signal communication lines. The stringent requirements of ESD protection devices are addressed by setting the concentration and positional relationship of the second epitaxial layer below the first doped region 204, the first doped region 204, and the buried layer 202, ensuring low operating voltage and low clamping voltage during ESD events. Due to the presence of the highly doped buried layer 202, the gain of the vertical transistor is very small, and the vertical transistor operates in the shallow scan region, avoiding the latch-up effect caused by the large scan of conventional transistors. The first epitaxial layer 21, the buried layer 202, the second epitaxial layer below the first doped region 204, and the first doped region 204 to the second doped region 205 are sequentially stacked on the substrate 10, resulting in a smaller chip area occupied by the ESD protection device, which can meet the miniaturization requirements of the chip.

[0096] Furthermore, a third doped region 206 is also provided within the second epitaxial layer 22, located on the first doped region 204. The third doped region 206 has a second conductivity type and a doping concentration greater than that of the first doped region 204. The third doped region 206 can uniformly distribute the current of the ESD protection device, improve the IPP (Instantaneous Power Peak) capability of the ESD protection device, and compensate for the drawback of reduced IPP caused by the small diode area between the second doped region 205 and the first doped region 204.

[0097] Furthermore, the second epitaxial layer below the first doped region 204 and the first doped region 204 both cover the first region I and the second region II. A fourth doped region 207 is provided on the first doped region 204 in the second region II on the substrate 10. The fourth doped region 207 is of the second conductivity type and its doping concentration is greater than that of the first doped region 204. The second doped region 205 and the fourth doped region 207 are connected by the front metal layer 51 located on the second epitaxial layer 22. In this way, the diode formed by the second epitaxial layer below the first doped region 204 and the first doped region 204 in the second region II can reduce the forward voltage drop of the ESD protection device and reduce the forward power consumption.

[0098] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.

Claims

1. An ultra-low capacitance ESD protection device, characterized in that, include: One or more cells, the cells comprising: Substrate, wherein the substrate is of the first doping type; A first epitaxial layer, located on the substrate, wherein the first epitaxial layer is of a first doping type; A buried layer, wherein the buried layer is located on a portion of the first epitaxial layer, and the buried layer is of a second doping type; The second epitaxial layer is located on the first epitaxial layer and the buried layer that are not covered by the buried layer, and the second epitaxial layer is of the first doping type; A first doped region extends from the surface of the second epitaxial layer into the second epitaxial layer, and the first doped region is of the second doping type; A plurality of isolation structures, wherein the isolation structures extend from the surface of the second epitaxial layer into the first epitaxial layer, wherein a portion of the isolation structures penetrates the buried layer and forms a first region, and a portion of the isolation structures do not penetrate the buried layer and form a second region; The second doped region extends from the surface of the first doped region in the first region into the first doped region in the first region, and the second doped region is of the first doping type. The third doped region extends from the surface of the first doped region in the first region into the first doped region in the first region. The third doped region is of the second doping type and is separated from the second doped region. The fourth doped region extends from the surface of the first doped region in the second region into the first doped region in the second region, and the fourth doped region is of the second doping type.

2. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, The isolation structure includes four isolation structures, and the first region is formed by the buried layer, the second epitaxial layer and the first doped region, the first isolation structure and the second isolation structure between the first isolation structure and the second isolation structure. The second region is formed by the second epitaxial layer and the first doped region between the third isolation structure and the fourth isolation structure, the third isolation structure, and the fourth isolation structure.

3. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, The doping concentration of the first epitaxial layer is less than that of the substrate and the second doped region, the doping concentration of the first epitaxial layer is greater than that of the third doped region, and the doping concentration of the buried layer is greater than that of the first doped region.

4. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, The width of the second doped region is smaller than the width of the third doped region.

5. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, The width of the second doped region is smaller than the width of the fourth doped region.

6. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, The width of the second doped region is smaller than the width of the fourth doped region and smaller than the width of the third doped region 2.

7. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, The depth of the second doped region is less than the depth of the third doped region and less than the depth of the fourth doped region, and the depths of the third doped region and the fourth doped region are equal.

8. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, The third doped region is located within the second epitaxial layer and on top of the first doped region, and the doping concentration of the third doped region is greater than that of the first doped region.

9. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, The first epitaxial layer covers the front side of the substrate; the second epitaxial layer has a front metal layer, and the ultra-low capacitance ESD protection device also includes a back metal layer located on the back side of the substrate.

10. The ultra-low capacitance ESD protection device as described in claim 9, characterized in that, The second epitaxial layer has an interlayer dielectric layer, which has a first contact hole corresponding to the location of the second doped region and a second contact hole corresponding to the location of the fourth doped region. The front metal layer is located on the interlayer dielectric layer and fills the first contact hole and the second contact hole.

11. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, The series circuit consisting of the second doped region, the first doped region, the second epitaxial layer below the first doped region, the buried layer, and the first epitaxial layer in the first region is connected in parallel with the second reverse diode formed by connecting the first doped region and the second epitaxial layer below the first doped region in the second region.

12. The ultra-low capacitance ESD protection device as described in claim 1, characterized in that, Multiple cells are arranged in parallel in sequence. The substrate has multiple first regions and multiple second regions. One first region corresponds to one second region. The second doped region of the first region and the fourth doped region in the corresponding second region are interconnected. The ultra-low capacitance ESD protection device has multiple first input / output ports. One first input / output port is connected to one second doped region and one corresponding fourth doped region.

13. The ultra-low capacitance ESD protection device according to any one of claims 1 to 12, characterized in that, The second doped region and the first doped region are connected to form a first forward diode, the first doped region and the first doped region are connected to form a first reverse diode, the second epitaxial layer below the first doped region and the buried layer are connected to form a second forward diode, the first epitaxial layer and the buried layer are connected to form a Zener diode, and the first forward diode, the first reverse diode, the second forward diode and the Zener diode are connected in series.

14. The ultra-low capacitance ESD protection device as described in claim 13, characterized in that, The ultra-low capacitance ESD protection device has a first input / output port and a second input / output port. The second doped region and the fourth doped region are both connected to the first input / output port, and the substrate is connected to the second input / output port.

15. The ultra-low capacitance ESD protection device as described in claim 14, characterized in that, When the first input / output port is connected to a high potential and the second input / output port is connected to a low potential, current flows into the ESD protection device through the front metal layer. In the first region, the current reaches the second input / output port through the first forward diode, the first reverse diode, the transistor composed of the second forward diode and the Zener diode, and the substrate.

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