A silicon wafer, cell and photovoltaic module

Abstract

The embodiment of the present application provides a kind of silicon wafer, cell piece and photovoltaic module, silicon wafer includes first side, second side and silicon wafer surface, first side extends along first direction, second side extends along second direction, first direction and second direction intersect;The ratio of the length of first side and the length of second side is 1.5-3, there is line mark on the surface of silicon wafer, and the line mark extends along the second direction;The surface of silicon wafer includes first area, second area and third area arranged in second direction in turn, first area and third area are close to two first sides of silicon wafer respectively, and the roughness Ra of first area or the roughness Ra of third area is less than the roughness Ra of second area.The probability of being scratched in the cleaning process of the silicon wafer of the embodiment of the present application is relatively low, and the bending degree in the middle of the silicon wafer is small, which reduces the probability of fragment or card between adjacent silicon wafers.

Description

Technical Field

[0001] This application belongs to the field of photovoltaic technology, specifically relating to a silicon wafer, a solar cell, and a photovoltaic module. Background Technology

[0002] Photovoltaic cells typically require laser dicing of silicon wafers to form half-wafers. The edges of the silicon wafers after laser dicing will have burrs, which affects the subsequent passivation effect of the cell and seriously restricts the improvement of cell efficiency.

[0003] To improve the edge morphology of silicon wafers and further enhance cell efficiency, the industry has proposed using diamond wire to cut silicon wafers into half-wafers during the wafer slicing process, and then using these half-wafers to fabricate solar cells.

[0004] When silicon wafers are cut into halves, the interaction between the diamond wire and the silicon wafer surface usually creates cutting marks. During the cleaning process after the silicon wafer is cut, the silicon wafer comes into contact with the basket toother. Scratches will occur at the points on the silicon wafer that come into contact with the basket toother. As the cleaning process continues, too much liquid usually accumulates in the middle of the silicon wafer at the points that do not come into contact with the basket toother. This can cause fragments or jams to form between adjacent silicon wafers during cleaning, reducing the production efficiency of silicon wafers and increasing the production cost. Utility Model Content

[0005] This application aims to provide a silicon wafer, a solar cell, and a photovoltaic module to solve the problem that in existing silicon wafers, liquid tends to pool in the middle of the wafer during cleaning, causing the wafer to bend and resulting in wafer fragments or clipping during the cleaning process.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows: In a first aspect, this application discloses a silicon wafer, the silicon wafer including a first edge, a second edge, and a silicon wafer surface, the first edge extending along a first direction, the second edge extending along a second direction, the first direction intersecting the second direction; the ratio of the length of the first edge to the length of the second edge is 1.5-3, the silicon wafer surface has line marks, the line marks extending along the second direction; the silicon wafer surface includes a first region, a second region, and a third region arranged sequentially along the second direction, the first region and the third region being respectively close to the two first edges of the silicon wafer, the roughness Ra of the first region or the roughness Ra of the third region being less than the roughness Ra of the second region; The first region is a region located along the second direction at a distance of less than 15 mm from the nearest first side; the third region is a region located along the second direction at a distance of less than 15 mm from the nearest other first side; the second region is located between the first region and the third region.

[0007] Optionally, the ratio of the roughness of the second region to the roughness of the first region is greater than 1 and less than or equal to 2; or the ratio of the roughness of the second region to the roughness of the third region is greater than 1 and less than or equal to 2. Optionally, the roughness Ra of the first region and the third region satisfies: 0.3um≤Ra≤1.2um, and / or the roughness Ra of the second region satisfies: 0.4um≤Ra≤1.3um.

[0008] Optionally, the silicon wafer surface is provided with a fourth region, a fifth region and a sixth region arranged sequentially along the first direction, the fourth region being closer to the second side, and the line mark density of the fourth region being greater than that of the fifth region; The fourth region is a region whose distance from the nearest second side along the first direction is less than or equal to 15 mm, the sixth region is a region whose distance from the nearest other second side along the first direction is less than or equal to 15 mm, and the fifth region is located between the fourth region and the sixth region.

[0009] Optionally, the spacing S1 between adjacent line marks in the fourth region satisfies: 0.2mm ≤ S1 ≤ 1.5mm; And / or, the spacing S2 between adjacent line marks in the fifth region satisfies: 0.5mm ≤ S2 ≤ 2.2mm; And / or, the spacing S3 between adjacent line marks in the sixth region satisfies: 0.2mm≤S3≤1.8mm.

[0010] Optionally, the depth D of the line mark satisfies: 1um ≤ D ≤ 7um.

[0011] Optionally, the line extends in an arc shape on the silicon wafer surface, the endpoint of the line is located on the first side, and the vertex of the line is located between the two first sides; the distance L between the vertex and the endpoint along the first direction satisfies: 1mm≤L≤2mm.

[0012] Optionally, the thickness of the silicon wafer is 100 μm - 145 μm.

[0013] Secondly, this application also discloses a solar cell comprising a silicon wafer as described in any of the preceding claims.

[0014] Thirdly, this application also discloses a photovoltaic module, which includes a silicon wafer or a solar cell as described in any of the preceding claims.

[0015] In this embodiment, the ratio of the length of the first side to the length of the second side of the silicon wafer is 1.5-3. The lines on the surface of the silicon wafer extend along the direction of the second side. The surface of the silicon wafer includes a first region, a second region, and a third region arranged sequentially along the second direction. The roughness of the first region and the roughness of the third region are less than the roughness of the second region. During the cleaning process, the first region of the silicon wafer surface contacts the basket tooth rod. Since the direction of the lines on the silicon wafer surface is parallel to the direction of the extension of the basket tooth rod, and the roughness of the first and third regions (i.e., the regions in contact with the basket tooth rod) is small, the probability of the silicon wafer surface being scratched at the contact point with the basket tooth rod is reduced. At the position on the silicon wafer that does not contact the basket tooth rod, since the ratio of the length of the first side to the length of the second side of the silicon wafer is 1.5-3, the length of the silicon wafer in the suspended state is small. The roughness of the second region at the suspended position is greater than that of other regions, which reduces the accumulation of liquid. This results in less deflection caused by liquid accumulation, less bending in the middle of the silicon wafer, and reduces the probability of fragmentation or chipping between adjacent silicon wafers.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure and cleaning process of a silicon wafer in related technologies; Figure 2 This is a schematic diagram of the structure when the basket toothed rod contacts the silicon wafer; Figure 3 This is a schematic diagram of the structure and cleaning process of the silicon wafer in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of the flower basket carrying the silicon wafer in the embodiments of this application; Figure 5 This is a schematic diagram of the silicon wafer structure in the embodiments of this application; Figure 6 This is a side view of the silicon wafer in an embodiment of this application; Figure 7 This is a schematic diagram of the silicon wafer cutting direction in an embodiment of this application.

[0018] Reference numerals: 10-Silicon wafer, 100-Silicon wafer surface, 101-First region, 102-Second region, 103-Third region, 104-Fourth region, 105-Fifth region, 106-Sixth region, 107-Exit region, 108-Inlet region, 11-First side, 12-Second side, 13-Line mark, 20-Tooth bar, 30-Half bar, 40-Cut wire mesh, X-First direction, Y-Second direction. Detailed Implementation

[0019] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0021] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0022] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0023] In this application, Ra represents the arithmetic mean roughness, which is the arithmetic mean of the absolute values ​​of the profile offsets within the sampling length. The surface roughness of the silicon wafers in this application is measured using a stylus-type roughness meter, such as the SJ-210 portable roughness meter or the FTAD3000 integrated roughness and profile measurement device.

[0024] A measurement segment is selected on the surface of the silicon wafer. For example, the first region, the second region, and the third region arranged sequentially along the second direction on the surface of the silicon wafer are selected as measurement segments, i.e., three measurement segments. The roughness value Ra of at least one measurement point on the three measurement segments is detected by a roughness measuring device. If only one value is measured for each selected measurement segment, the tester can directly give the corresponding roughness Ra value. If multiple values ​​are measured, the average roughness Ra corresponding to the three measurement segments can be obtained by calculating the average value.

[0025] In the production process of solar cells, processing the silicon wafer 10 into half-wafers of unequal lengths on both sides before preparing the cells can reduce the internal resistance of the cells, reduce the power loss of the cells, and increase the power generation of the modules.

[0026] In such Figure 1 In the silicon wafer 10 shown, the line mark 13 extends along the long side of the silicon wafer 10. During the cleaning and insertion process of this type of silicon wafer 10, such as... Figure 1 As shown by the middle arrow, silicon wafer 10 is inserted into the basket with its long side facing forward. Further, after silicon wafer 10 is inserted into the basket, as... Figure 2 As shown, the two short sides of the silicon wafer 10 are respectively attached to the left and right toothed rods 20 of the basket to support the silicon wafer 10. The silicon wafer 10 between the left and right toothed rods 20 of the basket is in a suspended state. Under this support structure, the part of the silicon wafer 10 that is in a suspended state is relatively long and heavy. During cleaning, the liquid will converge towards the middle of the silicon wafer 10, resulting in insufficient distance between adjacent silicon wafers 10 in the basket. The silicon wafers 10 are prone to interference and collision with each other, resulting in fragments or cards, which affects the processing yield of the silicon wafer 10.

[0027] Based on the above problems, this application provides a silicon wafer 10, such as... Figure 3As shown, the silicon wafer 10 includes a silicon wafer surface 100, a first side 11 extending along a first direction X, and a second side 12 extending along a second direction Y. The ratio of the length of the first side 11 to the length of the second side 12 is 1.5-3. The silicon wafer surface 100 has a line mark 13 extending along the second direction Y, where the first direction X intersects the second direction Y. The silicon wafer surface 100 includes a first region 101, a second region 102, and a third region 103 arranged sequentially along the second direction Y. The first region 101 and the third region 103 are respectively close to the two first edges 11 of the silicon wafer 10. The roughness of the first region 101 and the roughness of the third region 103 are both less than the roughness of the second region 102. The first region 101 is the region whose distance from the nearest first edge 11 along the second direction Y is less than 15mm. The third region 103 is the region whose distance from the nearest other first edge along the second direction Y is less than 15mm. The second region 102 is located between the first region 101 and the third region 103.

[0028] In this embodiment, the ratio of the length of the first side 11 to the length of the second side 12 of the silicon wafer 10 is between 1.5 and 3. The line marks 13 on the surface 100 of the silicon wafer extend along the direction of the second side 12. The surface of the silicon wafer 10 includes a first region 101, a second region 102 and a third region 103 arranged sequentially along the second direction Y. The roughness of the first region 101 and the roughness of the third region 103 are less than the roughness of the second region 102. During the cleaning process, the first region 101 and the third region 103 of the silicon wafer surface 100 contact the basket tooth rod 20. Since the direction of the line marks 13 on the silicon wafer surface 100 is parallel to the direction of extension of the basket tooth rod 20, and the roughness of the first region 101 and the third region 103 in the area in contact with the basket tooth rod 20 is small, the probability of the silicon wafer surface 100 being scratched at the contact point with the basket tooth rod 20 is reduced. At the position on the silicon wafer 10 that does not contact the basket tooth rod 20, since the ratio of the length of the first side 11 to the length of the second side 12 of the silicon wafer 10 is 1.5-3, the length of the suspended silicon wafer 10 is small. The roughness of the second region 102 at the suspended position is greater than that of other regions, which can reduce the accumulation of liquid, resulting in small deflection caused by liquid accumulation and small bending in the middle of the silicon wafer 10, thus reducing the probability of fragmentation or clipping between adjacent silicon wafers 10.

[0029] It should be noted that in this application, the ratio of the length of the first side 11 and the second side 12 of the silicon wafer 10 is between 1.5 and 3. When the ratio of the first side 11 and the second side 12 is greater than 3, bending will also occur along the direction of the first side 11 of the silicon wafer 10 during the cleaning process, increasing the fragmentation rate of the silicon wafer 10. When the ratio of the first side 11 and the second side 12 is less than 1.5, more gaps will be left between the cells or between the cells and the module frame at the photovoltaic module end, reducing the output power of the module.

[0030] In specific applications, the silicon wafer 10 can be produced using diamond wire cutting. When cutting the silicon wafer 10, the silicon rod can first be cut into the following shapes: Figure 7 The half-bar 30 shown is then sliced. For example... Figure 7 As shown, the cut half-rod 30 has intersecting length direction a, width direction b, and height direction c. When cutting the half-rod 30, the surface where the length direction a and width direction b intersect is used as the surface in contact with the cutting wire mesh 40. The cutting wire mesh 40 continuously rubs against the surface of the half-rod 30, and the half-rod 30 continuously feeds downwards in the direction indicated by arrow Z until it is completely cut through. Then, the half-rod 30 is removed from the cutting wire mesh 40 to obtain the silicon wafer of this application. The first side 11 of the cut silicon wafer 10 is the side of the half-rod 30 in the height direction c, and the second side 12 is the side of the half-rod 30 in the width direction b. Multiple lines 13 are formed on the cut silicon wafer 10. It is understood that when the lines 13 on the silicon wafer surface 100 extend based on the short side of the silicon wafer 10, during the cleaning process of such silicon wafer 10, if... Figure 3 As indicated by the middle arrow, silicon wafer 10 is inserted into the basket with its shorter second side 12 facing forward. Further, after silicon wafer 10 is inserted into the basket, as... Figure 4 As shown, the two longer first sides 11 of the silicon wafer 10 are respectively attached to the left and right toothed rods 20 of the basket to support the silicon wafer 10. The silicon wafer 10 suspended between the left and right toothed rods 20 is shorter, and the deflection of the silicon wafer 10 caused by gravity is smaller, which reduces the probability of the silicon wafer 10 bending. It can be placed more flatly, reducing the risk of fragments or clips between adjacent silicon wafers 10 during cleaning, improving the production efficiency of the silicon wafer 10, and effectively controlling the production cost of the silicon wafer 10.

[0031] Furthermore, in this silicon wafer 10 structure, the roughness of the silicon wafer surface 100 can be adjusted by modifying the cutting process. In practical applications, during the process of cutting a silicon ingot into a silicon wafer 10, the roughness of the silicon wafer surface 100 can be adjusted by controlling cutting process parameters such as the feed rate of the silicon ingot. For example, in this application, during the cutting process, because the load on the half-ingot 30 is small, the feed rate of the silicon ingot is set to 3 mm / min to improve processing efficiency. During the cutting of the half rod 30, the flow rate of the slurry pipe is set to 150L / min~200L / min due to the short travel distance of the cutting line. This prevents excessive flow from affecting the stability of the cutting line and ensures the liquid carrying capacity of the cutting line in the middle of the silicon wafer. This controls the roughness of the first region 101 and the third region 103 of the silicon wafer surface 100 along the first direction X, which are less than 15mm from the first edge 11, to be less than the roughness of the second region 102. This reduces scratches at the first region 101 and the third region 103 where the silicon wafer 10 contacts the basket toothed rod 20 during the cleaning process. At the same time, it ensures that the roughness of the second region 102 is relatively large, increasing the surface area of ​​the second region 102 of the silicon wafer surface 100. This reduces the amount of cleaning liquid converging towards the middle of the silicon wafer 10 within the same cleaning time, reducing the probability of fragments or clips between adjacent silicon wafers 10 and improving processing efficiency.

[0032] It is understandable that during the cleaning process, liquid will converge towards the central area of ​​silicon wafer 10. In this embodiment, the second region 102 is located between the first region 101 and the third region 103, that is, the middle region of silicon wafer 10 along the second direction Y. Designing the roughness of this region to be greater than that of the first region 101 and the third region 103 can slow down the rate at which liquid converges towards the center of silicon wafer 10, thereby reducing the rate at which liquid converges towards the center of silicon wafer 10 from both sides of the short side. During the cleaning process, due to the action of the air knife, the liquid is blown to the edge region (first region 101 and third region 103) of silicon wafer 10. Setting the roughness of the edge region to be relatively small facilitates the liquid sliding off the silicon wafer surface 100, further reducing the amount of liquid remaining on the silicon wafer surface 100. The degree of bending of silicon wafer 10 is further reduced, thereby reducing the probability of debris and chips between adjacent silicon wafers 10 during the cleaning process and improving product yield. In specific applications, such as... Figure 3 As shown, silicon wafer 10 is inserted into the basket in the direction of the dashed arrow in the figure, as... Figure 4As shown, after the silicon wafer 10 is inserted into the basket, the bottom of the first region 101 and the third region 103 near the two first sides 11 contacts the toothed rods 20 on the left and right sides of the basket, and then the silicon wafer 10 is cleaned. Understandably, when the roughness of the first region 101 and the third region 103 located on both sides of the silicon wafer surface 100 along the second direction Y is small, the probability of scratches on the silicon wafer surface 100 is reduced when the first region 101 and the third region 103 of the silicon wafer surface 100 come into contact with the basket tooth bar 20. Furthermore, under the action of the air knife, the cleaning fluid on the second region 102 is blown to both sides, and the liquid on the first region 101 and the third region 103 with smaller roughness is more likely to slide off from the edge of the silicon wafer 10 (first region 101 and third region 103), making it less likely for the cleaning fluid to converge towards the center (second region 102). This reduces the amount of cleaning fluid from the edge of the silicon wafer 10 (first region 101 and third region 103) to converge towards the center of the silicon wafer 10 (second region 102), reducing the probability of the silicon wafer 10 bending due to liquid accumulation, thereby reducing the probability of the silicon wafer 10 breaking or chipping due to bending during cleaning.

[0033] Optionally, the ratio of the roughness of the second region 102 to the roughness of the first region 101 is greater than 1 and less than or equal to 4; or the ratio of the roughness of the second region 102 to the roughness of the third region 103 is greater than 1 and less than or equal to 4.

[0034] Understandably, when the roughness ratio of the second region 102 to the roughness ratio of the first region 101 or the third region 103 is less than or equal to 1, the roughness of the first region 101 or the third region 103 is too large, causing scratches on the silicon wafer 10 at the location in contact with the basket, increasing the probability of defects on the silicon wafer surface 100; if the roughness ratio of the second region 102 to the roughness ratio of the first region 101 or the third region 103 is greater than 4, compared with the first region 101 or the third region 103, the stress in the second region 102 of the silicon wafer 10 is too concentrated, increasing the probability of the silicon wafer 10 fragmenting.

[0035] For example, the roughness ratio of the second region 102 to the roughness of the first region 101 can be designed to be 1.1, 1.5, 2, 2.5, 3, 3.5, 4, etc.; the roughness ratio of the second region 102 to the roughness of the third region 103 can be designed to be 1.1, 1.5, 2, 2.5, 3, 3.5, 4, etc.

[0036] It should be understood that during the cleaning process of the silicon wafer surface 100, the air knife generates a high-speed, uniform airflow through a high-pressure blower and impacts the silicon wafer surface 100 to clean it. During the cleaning process, when the roughness of the silicon wafer surface 100 is too small, the adhesion of the cleaning fluid is weak, increasing the fluidity of the cleaning fluid and making it easier for the cleaning fluid to converge towards the center; when the roughness is too large, it will lead to incomplete cleaning, prolong the cleaning time, and reduce the cleaning efficiency. In this embodiment, by controlling the roughness Ra of the silicon wafer surface 100 to be between 0.1µm and 2µm, the surface tension and wettability of water on the silicon wafer surface 100 are reduced. As a result, when the airflow generated by the air knife acts on the silicon wafer surface 100, the liquid on the silicon wafer surface 100 is more easily peeled off, reducing the probability of silicon wafer 10 bending caused by liquid accumulation. At the same time, it also improves the cleanliness of the cleaning and increases the cleaning efficiency. For example, the surface roughness Ra of a silicon wafer 100 can be designed to be 0.1µm, 0.2µm, 0.3µm, 0.5µm, 0.7µm, 0.8µm, 1.0µm, 1.1µm, 1.2µm, 1.5µm, 1.7µm, 1.8µm, 2µm, etc.

[0037] For example, in the embodiments of this application, the roughness Ra of the silicon wafer surface 100 on the first region 101 and the third region 103 satisfies: 0.3um ≤ Ra ≤ 1.2um, and / or, the roughness Ra of the silicon wafer surface 100 on the second region 102 satisfies: 0.4um ≤ Ra ≤ 1.3um. For example, the roughness Ra of the silicon wafer surface 100 on the first region 101 and the third region 103 can be designed to be 0.3um, 0.4um, 0.5um, 0.7um, 0.8um, 1.0um, 1.1um, 1.2um, etc.; the roughness Ra of the silicon wafer surface 100 on the second region 102 can be designed to be 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1.0um, 1.1um, 1.2um, 1.3um, etc.

[0038] By further defining the roughness of the silicon wafer surface 100 in the first region 101, the second region 102, and the third region 103, the relationship between friction and light absorption efficiency can be balanced.

[0039] In this process, the roughness Ra of the first region 101 and the third region 103 satisfies 0.3µm ≤ Ra ≤ 1.2µm. In the solar cell made from this silicon wafer 10, since the edge region of the silicon wafer 10 is prone to fragmentation, reducing its roughness is beneficial to stress release. During the cell fabrication process, the edge of the solar cell is more regular, effectively suppressing the risk of edge leakage. The roughness Ra of the second region 102 is 0.4µm ≤ Ra ≤ 1.3µm, which is relatively larger than the roughness of the first region 101 and the third region 103. When the roughness Ra of the second region 102 is ≤ 0.4µm, it is not conducive to more light reflection on the silicon wafer surface 100, reducing the light transmission path and thus not conducive to improving photoelectric conversion efficiency. When the roughness Ra of the second region 102 is ≥ 1.3µm, the roughness of the silicon wafer surface 100 is too large, increasing defects, which is not conducive to carrier migration and affects the efficiency of the cell.

[0040] like Figure 5 As shown, the silicon wafer surface 100 has a fourth region 104, a fifth region 105, and a sixth region 106 arranged sequentially along the first direction X. The fourth region 104 is closer to the second side 12, and the line mark density of the fourth region 104 is greater than that of the fifth region 105. After the silicon wafer 10 is cleaned, during the sorting process, the second side 12 is positioned forward, and the line marks 13 on the silicon wafer surface 100 are perpendicular to the belt conveyor direction. By increasing the line mark density of the fourth region 104 corresponding to the second side 12, it is ensured that the silicon wafer 10 does not jam when it contacts the conveyor belt. Meanwhile, by setting the roughness of the fifth region 105 on the silicon wafer surface 100 to be relatively large, the contact area between it and the conveyor belt is increased, ensuring the positional accuracy and stability of the silicon wafer 10.

[0041] Specifically, of the two second edges 12, one second edge 12 is located in the fourth region 104 and corresponds to the exit region 107, while the other second edge 12 is located in the sixth region 106 and corresponds to the entry region 108. Here, the line mark density refers to the number of lines 13 within a certain distance range on the silicon wafer surface 100 along the first direction X. In actual silicon wafer 10 products, based on adjustments to the actual process and the distribution of line mark density, the region division of the silicon wafer 10 can be determined, and the number of stripes within a range such as 5mm, 8mm, 10mm, and 12mm can be selected as the stripe density.

[0042] It should be noted that in the process of obtaining silicon wafers 10 by wire cutting of silicon rods, the cutting speed of the wire and the feed speed of the silicon rod are not constant, but are adjusted according to the actual situation. Typically, the feed speed of the silicon rod is adjusted in the fourth region 104, the fifth region 105, and the sixth region 106 of the silicon rod, resulting in wire marks of varying density on the silicon wafer surface 100 in these regions. Furthermore, the wire reciprocates during the cutting process, exhibiting acceleration, uniform speed, and deceleration cycles. Specifically, when the wire enters the sixth region 106, the silicon rod has a chamfer. To reduce the fragmentation rate in the chamfered area, the feed speed of the silicon rod is slower, the number of wire reciprocating cutting cycles is higher, and the resulting wire marks 13 are denser. In the fifth cutting region 105, the wire mesh cutting speed is relatively fast, the silicon rod feed speed is also relatively fast, and the resulting cutting marks 13 are sparsely arranged. Upon cutting to the fourth region 104, near the exit position, the silicon rod has a chamfered area and is close to the resin plate. To reduce the fragmentation rate during exit, the cutting speed is slowed down, the number of reciprocating cutting cycles of the wire mesh is also higher, and the resulting cutting marks are denser.

[0043] In practical applications, the line mark density can be controlled by adjusting the cutting process parameters between different areas on the silicon wafer surface 100.

[0044] For example, in the embodiments of this application, the spacing S1 between adjacent line marks 13 in the fourth region 104 satisfies: 0.2mm≤S1≤1.5mm; and / or, the spacing S2 between adjacent line marks 13 in the fifth region 105 satisfies: 0.5mm≤S2≤2.2mm; and / or, the spacing S3 between line marks 13 in the sixth region 106 satisfies: 0.2mm≤S3≤1.8mm.

[0045] In this embodiment, by controlling the spacing of adjacent traces 13 in the fourth region 104 and the sixth region 106, the chamfer structure of the edge of the silicon wafer 10 can be adapted. In practical applications, the feed speed of the silicon rod and the number of cycles of wire mesh reciprocating cutting can be slower, thereby reducing the breakage rate of the fourth region 104 and the sixth region 106 in the chamfer area. By controlling the trace density of the fifth region 105, under the condition of satisfying the trace density of the fifth region 105, the cutting speed of the wire mesh and the feed speed of the silicon rod can be set to be faster. This allows the fifth region 105 of the silicon wafer surface 100 to apply a faster cutting speed while ensuring roughness, thereby optimizing the balance between product quality and production efficiency.

[0046] like Figure 6As shown, the depth of the line mark 13 is D, satisfying: 1µm ≤ D ≤ 7µm. In this embodiment, by controlling the depth range of the line mark 13, on the one hand, it can avoid the excessive roughness of the entire silicon wafer surface 100 due to an excessively large line mark 13, which would affect the uniformity of the film layer during the subsequent cell fabrication process. Ensuring the uniformity of the film layer on the cell surface guarantees the photoelectric conversion efficiency of the cell. On the other hand, if the line mark 13 is too small, the requirements for the cutting process parameters are higher, which would reduce the processing efficiency of the silicon wafer 10 and increase the production cost of the silicon wafer 10. In practical applications, the depth of the line mark 13 can be controlled by controlling the cutting speed and quality of the cutting line.

[0047] For example, the depth of the trace 13 on the silicon wafer surface 100 can be 1um, 1.5um, 2um, 2.5um, 3um, 3.5um, 4um, 4.5um, 5um, 6um, 7um, etc. The embodiments of this application do not specifically limit the depth of the trace 13.

[0048] Optionally, the trace 13 extends in an arc shape on the silicon wafer surface 100, with the endpoint of the trace 13 located on the first side 11 and the vertex of the trace 13 located between the two first sides 11. The distance between the vertex and the endpoint along the first direction X is L, satisfying: 1mm ≤ L ≤ 2mm. Since the trace 13 extends in an arc shape on the silicon wafer surface 100, L can be used to characterize the curvature of the trace 13 when the size of the second side 12 of the silicon wafer 10 is fixed. When 1mm ≤ L ≤ 2mm is satisfied, the height of the endpoint and vertex of the trace 13 along the first direction X is small, that is, the curvature of the trace 13 is small. It can be understood that since the trace 13 has a certain depth, when the curvature is large, liquid will accumulate towards the vertex of the trace 13. By controlling the curvature of the trace 13 within a small range, the accumulation of liquid towards the middle of the silicon wafer 10 along the second direction Y can be reduced, thereby reducing the probability of the silicon wafer 10 bending and reducing the risk of fragmentation caused by bending.

[0049] In practical applications, when printing gate lines on silicon wafer 10, the gate lines can extend along the second direction Y. If the roughness Ra of the silicon wafer surface 100 satisfies 0.1µm ≤ Ra ≤ 2µm, and the distance L between the vertex and the endpoint along the first direction X satisfies 1mm ≤ L ≤ 2mm, then printing gate lines on the silicon wafer surface 100 is convenient. Furthermore, the smaller L is, the higher the flatness of the silicon wafer surface 100, and the less the gate lines are damaged by roughness.

[0050] For example, the distance L between the vertex and the endpoint of line mark 13 along the first direction X can be 1mm, 1.1mm, 1.2mm, 1.5mm, 1.6mm, 1.8mm, 2mm, etc. In this embodiment of the application, the distance L between the vertex and the endpoint along the first direction X is not specifically limited.

[0051] Optionally, the thickness of the silicon wafer 10 is 100μm-145μm. In this embodiment, by controlling the thickness of the silicon wafer 10 within the above range, the carrier transport efficiency can be guaranteed, the cost of the silicon wafer 10 can be controlled, and the fragmentation rate of the silicon wafer 10 can be reduced. It should be noted that when the thickness of the silicon wafer 10 is greater than 145μm, the number of silicon wafers 10 formed by slicing silicon rods is smaller, which leads to increased cost. In addition, when the silicon wafer 10 is thicker, the probability of carrier collision is higher, and the probability of recombination during transport is increased, which reduces the carrier collection efficiency. When the thickness of the silicon wafer 10 is less than 100μm, although it is more conducive to carrier transport, it increases the brittleness of the silicon wafer 10, resulting in a higher fragmentation rate. In addition, when the silicon wafer 10 is too thin, the propagation path of light in the silicon wafer 10 is shortened, and some photons may escape from the silicon wafer 10 without being absorbed, resulting in a reduction in the number of excitable carriers and a decrease in short-circuit current density.

[0052] In summary, the silicon wafer 10 provided in this application embodiment may include at least the following advantages: In this embodiment, the ratio of the length of the first side to the length of the second side of the silicon wafer is 1.5-3. The lines on the surface of the silicon wafer extend along the direction of the second side. The surface of the silicon wafer includes a first region, a second region, and a third region arranged sequentially along the second direction. The roughness of the first region and the roughness of the third region are less than the roughness of the second region. During the cleaning process, the first region of the silicon wafer surface contacts the basket tooth rod. Since the direction of the lines on the silicon wafer surface is parallel to the direction of the extension of the basket tooth rod, and the roughness of the first and third regions, i.e., the regions in contact with the basket tooth rod, is relatively small, the probability of the silicon wafer surface being scratched at the contact point with the basket tooth rod is reduced. At the position on the silicon wafer that does not contact the basket tooth rod, since the ratio of the length of the first side to the length of the second side of the silicon wafer is 1.5-3, the length of the silicon wafer in the suspended state is relatively small. The roughness of the second region at the suspended position is greater than that of other regions, which reduces the accumulation of liquid. This results in less deflection caused by liquid accumulation, less bending in the middle of the silicon wafer, and reduces the probability of fragmentation or chipping between adjacent silicon wafers.

[0053] This application also provides a solar cell, which includes the silicon wafer 10 described in any of the above embodiments.

[0054] In specific applications, during the process of fabricating a solar cell from the silicon wafer 10, the roughness of the first region 101 to the third region 103 of the silicon wafer surface 100 is different. By setting the roughness of the first region 101 and the third region 103 to be smaller than the roughness of the second region 102, the stress at the edge of the silicon wafer 10 is well released, reducing the risk of edge fragmentation. At the same time, it provides a stable and reliable contact surface for the printing of cell grid lines and is also conducive to the collection of charge carriers. On the other hand, the roughness of the second region 102 of the silicon wafer surface 100 is large, which increases the light transmission path and is conducive to increasing light absorption, thereby improving the efficiency of the solar cell fabricated from the silicon wafer 10.

[0055] In practical applications, during the fabrication of a solar cell from the aforementioned silicon wafer 10, a film layer needs to be formed on the surface of the silicon wafer 10, and then grid lines are printed on the film layer. The surface roughness of the silicon wafer 10 reflects the flatness of the silicon wafer surface 100. Since the surface roughness Ra of the silicon wafer surface 100 satisfies 0.03um≤Ra≤1.2um, the flatness of the silicon wafer surface 100 is relatively high. During the cell manufacturing process, the silicon wafer 10 undergoes wet processing, such as damage layer removal and etching, removing a portion of the thickness of the silicon wafer surface 100. Thus, after processing the film layer on the silicon wafer surface 100, during the printing of the electrode grid lines on the film layer, due to the high flatness of the silicon wafer surface 100, the uniformity of the flatness of the silicon wafer surface 100 after wet processing is better. This results in a more uniform width and thickness of the electrode grid lines, lower grid line resistance, and facilitates current conduction on the grid lines. Therefore, the photoelectric conversion efficiency of the solar cell using the silicon wafer 10 can be improved.

[0056] This application also provides a photovoltaic module, which includes the silicon wafer 10 or the solar cell as described above.

[0057] It should be noted that in the embodiments of this application, the structure of the silicon wafer 10 or the battery cell is the same as that of the silicon wafer 10 or the battery cell in any of the above embodiments, and its beneficial effects are also similar, so they will not be described in detail here.

[0058] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0059] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A silicon wafer, characterized in that, The silicon wafer includes a first edge, a second edge, and a silicon wafer surface. The first edge extends along a first direction, and the second edge extends along a second direction, with the first direction intersecting the second direction. The ratio of the length of the first edge to the length of the second edge is 1.5-3. The silicon wafer surface has line marks extending along the second direction. The silicon wafer surface includes a first region, a second region, and a third region arranged sequentially along the second direction. The first region and the third region are respectively close to the two first edges of the silicon wafer. The roughness Ra of the first region or the roughness Ra of the third region is less than the roughness Ra of the second region. The first region is a region located along the second direction at a distance of less than 15 mm from the nearest first side; the third region is a region located along the second direction at a distance of less than 15 mm from the nearest other first side; the second region is located between the first region and the third region.

2. The silicon wafer according to claim 1, characterized in that, The ratio of the roughness of the second region to the roughness of the first region is greater than 1 and less than or equal to 2; or the ratio of the roughness of the second region to the roughness of the third region is greater than 1 and less than or equal to 2.

3. The silicon wafer according to claim 2, characterized in that, The roughness Ra of the first region or the third region satisfies: 0.3um≤Ra≤1.2um, and / or the roughness Ra of the second region satisfies: 0.4um≤Ra≤1.3um.

4. The silicon wafer according to claim 1 or 3, characterized in that, The silicon wafer surface has a fourth region, a fifth region and a sixth region arranged sequentially along the first direction. The fourth region is close to the second side, and the line mark density of the fourth region is greater than that of the fifth region. The fourth region is a region whose distance from the nearest second side along the first direction is less than or equal to 15 mm, the sixth region is a region whose distance from the nearest other second side along the first direction is less than or equal to 15 mm, and the fifth region is located between the fourth region and the sixth region.

5. The silicon wafer according to claim 4, characterized in that, The spacing S1 between adjacent line marks in the fourth region satisfies: 0.2mm ≤ S1 ≤ 1.5mm; And / or, the spacing S2 between adjacent line marks in the fifth region satisfies: 0.5mm ≤ S2 ≤ 2.2mm; And / or, the spacing S3 between adjacent lines in the sixth region satisfies: 0.2mm≤S3≤1.8mm.

6. The silicon wafer according to claim 1, characterized in that, The depth D of the line mark satisfies: 1um ≤ D ≤ 7um.

7. The silicon wafer according to claim 1, characterized in that, The line extends in an arc shape on the surface of the silicon wafer, with the endpoint of the line located on the first side and the vertex of the line located between the two first sides; the distance L between the vertex and the endpoint along the first direction satisfies: 1mm≤L≤2mm.

8. The silicon wafer according to claim 7, characterized in that, The thickness of the silicon wafer is 100 μm - 145 μm.

9. A battery cell, characterized in that, The solar cell comprises: a silicon wafer as described in any one of claims 1 to 8.

10. A photovoltaic module, characterized in that, The photovoltaic module comprises: a silicon wafer as described in any one of claims 1 to 8, or a solar cell as described in claim 9.

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