Semiconductor device structure

Abstract

A semiconductor device structure includes a first copper-containing metal interconnect structure, a copper-based tunnel barrier layer, and a second copper-containing metal interconnect structure. The first copper-containing metal interconnect structure is formed within a first dielectric material layer. The copper-based tunnel barrier layer is located on a surface of the first copper-containing metal interconnect structure. The second copper-containing metal interconnect structure is embedded in a second dielectric material layer that covers the first dielectric material layer, wherein the second copper-containing metal interconnect structure is in direct contact with the copper-based tunnel barrier layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device structure. Background Technology

[0002] In semiconductor manufacturing, the reliability and performance of interconnect structures impact the overall integrity of electronic devices. Copper-containing metal interconnect structures present challenges due to their susceptibility to stress-related reliability issues, particularly delamination. These stress-related reliability problems stem from the mismatch in the coefficients of thermal expansion between copper and adjacent materials. This mismatch can lead to the accumulation of tensile stress during thermal cycling. This accumulation of tensile stress can cause defects such as hillocks and ultimately delamination, especially in areas with large copper surfaces. Therefore, mitigating these stress-induced problems is crucial for improving the yield and reliability of semiconductor devices, particularly as packaging designs continue to evolve, increasing density and complexity. Utility Model Content

[0003] In some embodiments, a semiconductor device structure includes a first copper-containing metal interconnect structure, a copper-based tunnel barrier layer, and a second copper-containing metal interconnect structure. The first copper-containing metal interconnect structure is located within a first dielectric material layer. The copper-based tunnel barrier layer is located on the surface of the first copper-containing metal interconnect structure. The second copper-containing metal interconnect structure is embedded in a second dielectric material layer covering the first dielectric material layer, wherein the second copper-containing metal interconnect structure is in direct contact with the copper-based tunnel barrier layer.

[0004] In some embodiments, a semiconductor device structure includes a first copper-containing metal interconnect structure, a copper-based tunnel barrier layer, an additional copper-based tunnel barrier layer, and a second copper-containing metal interconnect structure. The copper-based tunnel barrier layer is located on the surface of the first copper-containing metal interconnect structure. The additional copper-based tunnel barrier layer is in contact with the top surface and sidewalls of the first copper-containing metal interconnect structure. The second copper-containing metal interconnect structure is in direct contact with the copper-based tunnel barrier layer.

[0005] In some embodiments, a semiconductor device structure includes a first copper-containing metal interconnect structure, a copper-based tunnel barrier layer, and a second copper-containing metal interconnect structure. The first copper-containing metal interconnect structure is located within a first dielectric material layer. The copper-based tunnel barrier layer is situated on the surface of the first copper-containing metal interconnect structure. The second copper-containing metal interconnect structure is in direct contact with the copper-based tunnel barrier layer, wherein the second copper-containing metal interconnect structure is perpendicularly spaced from the first copper-containing metal interconnect structure through the copper-based tunnel barrier layer. Attached Figure Description

[0006] The form of this disclosure is similar to that of the accompanying document. Figure 1The best way to understand this text is by referring to the detailed description below. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a vertical cross-sectional view of an exemplary structure after the formation of a semiconductor device and a metal interconnect structure within a dielectric material layer according to an embodiment of this disclosure.

[0008] Figures 2A to 2L This is a continuous vertical cross-sectional view of a region of an exemplary structure during the formation of a copper-containing metal interconnect structure and a copper-based tunnel barrier layer, according to the first embodiment of this disclosure.

[0009] Figures 3A to 3D This is a continuous vertical cross-sectional view of a region of an exemplary structure during the formation of a copper-containing metal interconnect structure and a copper-based tunnel barrier layer, according to the second embodiment of this disclosure.

[0010] Figures 4A to 4F This is a continuous vertical cross-sectional view of a region of an exemplary structure during the formation of a copper-containing metal interconnect structure and a copper-based tunnel barrier layer, according to the third embodiment of this disclosure.

[0011] Figure 5A and Figure 5B This is a continuous vertical cross-sectional view of a region of an exemplary structure during the formation of a copper-containing metal interconnect structure and a copper-based tunnel barrier layer, according to the fourth embodiment of this disclosure.

[0012] Figure 6A and Figure 6B This is a continuous vertical cross-sectional view of a region of an exemplary structure during the formation of a copper-containing metal interconnect structure and a copper-based tunnel barrier layer, according to the fifth embodiment of this disclosure.

[0013] Figure 7A and Figure 7B This is a continuous vertical cross-sectional view of a region of an exemplary structure during the formation of a copper-containing metal interconnect structure and a copper-based tunnel barrier layer, according to the sixth embodiment of this disclosure.

[0014] Figure 8A and Figure 8B This is a continuous vertical cross-sectional view of a region of an exemplary structure during the formation of a copper-containing metal interconnect structure and a copper-based tunnel barrier layer, according to the seventh embodiment of this disclosure.

[0015] Figure 9A and Figure 9B This is a continuous vertical cross-sectional view of a region of an exemplary structure during the formation of a copper-containing metal interconnect structure and a copper-based tunnel barrier layer, according to the eighth embodiment of this disclosure.

[0016] Figures 10A to 10H This is a vertical cross-sectional view of a region of an exemplary structure according to an additional embodiment of this disclosure;

[0017] Figure 11 This is a vertical cross-sectional view of an exemplary structure after the bonding pad has been formed;

[0018] Figure 12A This is a vertical cross-sectional view of the region of the reconstructed wafer surrounding the first semiconductor die according to an embodiment of the present disclosure;

[0019] Figure 12B This is a top view of the reconstructed wafer during the process;

[0020] Figure 13 This is a vertical cross-sectional view of a region of the reconstructed wafer after the formation of the first molding compound matrix, according to an embodiment of the present disclosure.

[0021] Figure 14 This is a vertical cross-sectional view of a region of the reconstructed wafer after the formation of the first bonding level dielectric layer and the first active bonding pad, according to an embodiment of the present disclosure.

[0022] Figure 15 This is a vertical cross-sectional view of the region of the reconstructed wafer after the second semiconductor die is attached to each of the first semiconductor dies, according to an embodiment of the present disclosure.

[0023] Figure 16A This is a vertical cross-sectional view of a region of the reconstructed wafer after the formation of the second molding compound matrix, according to an embodiment of the present disclosure.

[0024] Figure 16B yes Figure 16A A top view of the area of ​​the reconstructed wafer;

[0025] Figure 17 This is a first flowchart illustrating the steps of forming the device structure according to the embodiments described herein;

[0026] Figure 18 This is a second flowchart illustrating the steps of forming the device structure according to the embodiments disclosed herein.

[0027] [Symbol Explanation]

[0028] 100: First semiconductor die

[0029] 109: First Semiconductor Substrate

[0030] 112: First shallow trench isolation structure

[0031] 113: Dielectric Pad

[0032] 114: Substrate perforation structure

[0033] 117: First back-side dielectric layer

[0034] 120: First Semiconductor Device

[0035] 160: First interconnect layer dielectric material layer, first interconnect level dielectric material layer

[0036] 170: First grain edge sealing ring structure

[0037] 180: First metal interconnect structure

[0038] 188: Package bonding structure

[0039] 190: First bonding level dielectric layer

[0040] 200: First molding grain unit

[0041] 220: Bonding-level dielectric layer

[0042] 228: First joint pad

[0043] 228A: First Active Engagement Pad

[0044] 228D: First Virtual Bonding Pad

[0045] 260: First molding compound matrix

[0046] 300: Second semiconductor die

[0047] 309: Semiconductor substrate

[0048] 312: Shallow trench isolation structure

[0049] 320: Semiconductor device

[0050] 330: Interconnect-level dielectric material layer, interconnect-level dielectric material layer

[0051] 340: Metal interconnect structure

[0052] 344: Edge sealing ring structure

[0053] 349: Copper-based tunnel barrier layer

[0054] 349E: Encapsulated copper-based tunnel barrier layer

[0055] 349L: Localized copper-based tunnel barrier layer

[0056] 350: First dielectric material layer

[0057] 351: Through-hole cavity

[0058] 352: First cover passivation layer

[0059] 354: First via-level dielectric layer

[0060] 356: First-level dielectric layer

[0061] 357: Electroplated masking layer

[0062] 362, 364: Metal interconnect structure

[0063] 367: Opening

[0064] 368: First copper-containing metal interconnect structure

[0065] 368BL: First Metal Barrier Liner

[0066] 368B: First metallic barrier layer

[0067] 368M: First Electroplating Material Section

[0068] 369: Copper-based tunnel barrier layer

[0069] 369E: Encapsulated copper-based tunnel barrier layer

[0070] 369L: Localized copper-based tunnel barrier layer

[0071] 370: Second dielectric material layer

[0072] 372: Second cover passivation layer

[0073] 374: Second interconnect dielectric layer

[0074] 387: Cavity

[0075] 388: Second copper-containing metal interconnect structure

[0076] 388A: Active bonding pad

[0077] 388B: Second Metal Barrier Pad

[0078] 388D: Virtual Joining Pad

[0079] 388M: Second Electroplating Material Section

[0080] 400: Second molding grain unit

[0081] 460: Second molding compound matrix

[0082] 810: Carrier substrate

[0083] 811: Adhesive layer

[0084] 900: Composite grains

[0085] 1710, 1720, 1730, 1740, 1750, 1810, 1820, 1830, 1840, 1850: Steps

[0086] UA: Cell Region

[0087] hd1: First horizontal direction

[0088] hd2: Second horizontal direction Detailed Implementation

[0089] The following disclosure provides numerous different implementations or examples for carrying out various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. The drawings are not to scale. Unless otherwise expressly stated, elements with the same symbols refer to the same elements and are assumed to have the same material composition and the same thickness range. Unless otherwise expressly disclosed, all features of the original embodiments are assumed to exist in any derived embodiments. Therefore, the features described in the relevant embodiments in the drawings and / or description support the features in the embodiments. Unless otherwise expressly stated, embodiments in which multiple instances of any described element are repeated are expressly contemplated. Embodiments in which non-essential elements are omitted are expressly contemplated, even if such embodiments are not expressly disclosed but are known in the art.

[0090] Additionally, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used herein for ease of description to describe the geometric characteristics of the elements selected from the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Unless otherwise explicitly stated, each element with the same symbol is assumed to have the same material composition and thickness within the same thickness range.

[0091] Several embodiments of this disclosure address challenges in semiconductor manufacturing, particularly those concerning the reliability and performance of multiple copper-based interconnect structures. Multiple copper-based interconnects are susceptible to stress-induced problems, such as multiple hillocks and delamination, especially after thermal cycling. These problems arise from a mismatch in the coefficients of thermal expansion between copper and the adjacent dielectric materials, leading to the accumulation of tensile stress. Copper-based tunnel barrier layers can be used to mitigate these stress-related reliability issues. Copper-based tunnel barrier layers can improve the integrity and performance of interconnects in semiconductor devices.

[0092] A copper-based tunneling barrier layer can be formed on the surface of a copper-containing metal interconnect structure, creating a thin dielectric layer composed of materials such as copper oxide, copper nitride, or copper oxynitride. This layer can be carefully designed to be thin enough (typically in the range of 0.5 nm to 2.0 nm) to allow electron tunneling between the first and second copper-containing metal interconnect structures. By allowing the tunneling effect, the barrier layer maintains electrical connectivity, which affects the function of the device, and can also act as a physical buffer that redistributes and alleviates tensile stresses generated during thermal cycling.

[0093] The stress reduction mechanism of tunnel barrier layers involves their ability to adapt to the difference in thermal expansion between copper and the surrounding dielectric material. By providing a transition layer that partially absorbs and redistributes stress, tunnel barrier layers prevent stress concentration at the interface, which could otherwise lead to defects such as hillocks and delamination. Therefore, the presence of tunnel barrier layers can stabilize the structure during temperature variations, thereby reducing the likelihood of stress-induced failure.

[0094] The advantage of embodiments of this disclosure lies in its ability to address stress-related reliability issues in copper interconnects without altering manufacturing processes or increasing costs. The method for forming the tunnel barrier layer utilizes established thermal and plasma processes, ensuring compatibility with existing semiconductor manufacturing processes. Furthermore, the flexibility in selecting the composition and thickness of the barrier layer allows for optimization to meet specific device requirements. This approach not only enhances the reliability of interconnect structures but also supports the use of metals such as copper in increasingly dense and complex semiconductor designs, thereby expanding the applicability and performance of interconnect technologies in advanced electronic devices. Various embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0095] Reference Figure 1 An exemplary structure is illustrated, which may include a plurality of semiconductor devices 320 formed on a semiconductor substrate 309 and a plurality of metal interconnect structures 340 formed within a plurality of interconnect dielectric material layers 330 and covering the semiconductor devices 320. The semiconductor devices 320 may include field-effect transistors, junction transistors, resistors, capacitors, inductors, diodes, and / or other semiconductor devices known in the art. In one embodiment, the semiconductor devices 320 may include complementary metal-oxide-semiconductor (CMOS) devices known in the art. The various semiconductor devices 320 may be electrically isolated from each other via shallow trench isolation structures 312.

[0096] The interconnect-level dielectric material layer 330 may include multiple inorganic dielectric materials and / or may be composed of inorganic dielectric materials, such as silicate glass, silicon nitride, silicon carbonitride, silicon oxynitride, and / or dielectric metal oxide materials. The metal interconnect structure 340 may include metal wire structures, metal via structures, and / or metal pads. A subset of the metal interconnect structure 340 may laterally surround the semiconductor device 320 and the remainder of the metal interconnect structure 340 as a continuous wall structure and may form an edge-sealing ring structure 344. In one embodiment, via-level metal interconnect structures and wire-level metal interconnect structures may alternate vertically along a vertical direction. The total number of metal wire layers within the metal interconnect structure 340 may range from 1 to 20, for example, 2 to 10.

[0097] Figures 2A to 2L This is a continuous vertical cross-sectional view of the region of an exemplary structure during the formation of a copper-containing metal interconnect structure (first copper-containing metal interconnect structure 368, second copper-containing metal interconnect structure 388) and a copper-based tunnel barrier layer 369, according to a first embodiment of the present disclosure.

[0098] Reference Figure 2A Optionally, a first cover passivation layer 352 and a first via-level dielectric layer 354 may be formed over the interconnect-level dielectric material layer 330. The first cover passivation layer 352 includes at least one diffusion-blocking dielectric material, such as silicon nitride, silicon oxynitride, or silicon carbonitride. The first cover passivation layer 352 can be formed by chemical vapor deposition (CVD) and can have a thickness in the range of 3 nm to 30 nm, although smaller and larger thicknesses can also be used. The first via-level dielectric layer 354 includes an interlayer dielectric (ILD) material, such as silicate glass. The thickness of the first via-level dielectric layer 354 can be in the range of 100 nm to 2000 nm, such as 200 nm to 1000 nm, although smaller and larger thicknesses can also be used.

[0099] Reference Figure 2BA photoresist layer (not shown) may be applied over the first via-level dielectric layer 354 and may be photolithographically patterned to form multiple openings that may be located over a subset of the metal interconnect structures 340 at the top layer of the interconnect-level dielectric layer 330. Each opening in the photoresist layer may be formed over a corresponding metal interconnect structure 340 at the top layer of the interconnect-level dielectric layer 330. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the first via-level dielectric layer 354 and the first overlay passivation layer 352. Multiple via cavities 351 may be formed through the first via-level dielectric layer 354 and the first overlay passivation layer 352, such that the top surface solid of the underlying metal interconnect structures 340 is exposed beneath each via cavity 351.

[0100] Reference Figure 2C A first metal barrier liner 368BL can be deposited over the first via-level dielectric layer 354 and in the peripheral region of the via cavity 351. The first metal barrier liner 368BL serves as a conductive substrate, which facilitates subsequent copper plating by providing a uniform, conductive surface (on which copper can be electroplated). The first metal barrier liner 368BL can be deposited by physical vapor deposition (PVD), which can provide high consistency and thickness uniformity across the varying morphology of the first via-level dielectric layer 354. In one embodiment, the first metal barrier liner 368BL may include a stack comprising a metal barrier material layer such as tantalum or tantalum nitride (Ta / TaN) and a covering copper layer. The first metal barrier liner 368BL includes a horizontal extension covering the horizontal top surface of the first via-level dielectric layer 354 and a vertical extension projecting downwards from the horizontal extension into the peripheral region of a corresponding via cavity 351. The thickness of the first metal barrier liner 368BL can range from 30nm to 200nm, although smaller and larger thicknesses can also be used.

[0101] Reference Figure 2D A patterned electroplated mask layer 357 can be formed over the first metal barrier pad layer 368BL. In one embodiment, the patterned electroplated mask layer 357 can be formed by applying a photoresist layer over the first metal barrier pad layer 368BL and patterning the photoresist layer by photolithography to form a plurality of discontinuous openings 367 therein. Each discontinuous opening 367 in the patterned electroplated mask layer 357 may have a larger opening than the corresponding underlying through-hole cavity 351 (e.g., Figure 2B (as shown in the diagram) a larger area. The lateral dimensions of each discontinuous opening 367 in the patterned electroplated mask layer 357 can range from 1 micrometer to 100 micrometers, although smaller and larger lateral dimensions can also be used.

[0102] refer to Figure 2E An electroplating process can be performed to electroplat a metallic material, which can be any electroplatable material known in the art. In one embodiment, the electroplated metallic material can be substantially composed of copper. The electroplated metallic material forms a plurality of first electroplated material portions 368M. The first electroplated material portions 368M are formed in areas not shielded by a patterned electroplating mask layer 357. In one embodiment, the first electroplated material portions 368M can be substantially composed of copper. The height of the top surface of the first electroplated material portions 368M, measured from a horizontal plane including the topmost surface of the first metal barrier pad layer 368BL, can be in the range of 150 nm to 6000 nm, for example, 300 nm to 3000 nm, although smaller and larger heights can also be used.

[0103] Reference Figure 2F The patterned electroplated mask layer 357 can be removed by ashing or by dissolving it in a solvent.

[0104] Reference Figure 2G Multiple unmasked portions of the first metal barrier pad layer 368BL can be removed by performing an etching process that selectively etches the material of the first metal barrier pad layer 368BL relative to the material of the first via-level dielectric layer 354. In the case where the first metal barrier pad layer 368BL comprises a stack of a metal barrier pad layer composed of TiN or TaN and a copper seed layer, the unmasked portions of the copper seed layer and the metal barrier pad layer can be removed by performing a two-step etching process. First, an isotropic wet etching process using a persulfate-based solution such as ammonium persulfate can be used to selectively remove the copper seed layer without etching the material of the metal barrier pad layer. Subsequently, a selective dry etching process, such as reactive ion etching (RIE) using fluorine-based chemicals (e.g., CF4 or SF6), can be performed to remove the unmasked portions of the metal barrier pad layer. A suitable cleaning process can then be performed to remove any residual material. The first metal barrier pad layer 368BL is divided into multiple first metal barrier layers 368B. Each successive combination of the first metal barrier layer 368B and the first electroplated material portion 368M includes a first copper-containing metal interconnect structure 368.

[0105] Reference Figure 2HAn interlayer dielectric (ILD) material can be deposited over the first copper-containing metal interconnect structure 368 and the first via-level dielectric layer 354. A planarization process, such as chemical mechanical polishing, can be performed to remove a portion of the ILD material from a horizontal plane including the top surface of the first copper-containing metal interconnect structure 368. The remaining portion of the ILD material constitutes the first line-level dielectric layer 356. An optional combination of the first cover passivation layer 352, the first via-level dielectric layer 354, and the first line-level dielectric layer 356 is referred to herein as the first dielectric material layer 350. A first copper-containing metal interconnect structure 368 embedded in the first dielectric material layer 350 can be formed.

[0106] Reference Figure 2I An optional second cover passivation layer 372 and a second interconnect-level dielectric layer 374 may be formed over the first dielectric material layer 350. The optional second cover passivation layer 372 and the second interconnect-level dielectric layer 374 are collectively referred to herein as the second dielectric material layer 370. The second cover passivation layer 372 comprises at least one diffusion barrier dielectric material such as silicon nitride, silicon oxynitride, or silicon carbonitride. The second cover passivation layer 372 may be formed by chemical vapor deposition and may have a thickness in the range of 3 nm to 30 nm, although smaller and larger thicknesses may also be used. The second interconnect-level dielectric layer 374 comprises an interlayer dielectric (ILD) material, such as a silicate glass material. The thickness of the second interconnect-level dielectric layer 374 may be in the range of 200 nm to 6000 nm, such as in the range of 400 nm to 3000 nm, although smaller and larger thicknesses may also be used. In an alternative implementation, a single dielectric material layer may be formed instead of a combination of a first via-level dielectric layer 354, an optional second cover passivation layer 372, and a second interconnect-level dielectric layer 374.

[0107] Reference Figure 2J As shown, a plurality of cavities 387 can be formed through the second dielectric material layer 370. For example, at least one patterned photoresist layer (not shown) can be formed above the second dielectric material layer 370, and each pattern in the at least one patterned photoresist layer can be transferred through the second dielectric material layer 370 by performing at least one anisotropic etching process. Generally, cavities 387 can be formed through at least one additional dielectric material layer, such that surface segments of the first copper-containing metal interconnect structure 368 or copper-based tunnel barrier layer 369 are exposed below each cavity 387. In one embodiment, the cavity 387 may include integrated pad and via cavities. In this embodiment, each cavity 387 may include a via cavity portion located in the lower portion of the second dielectric material layer 370 and a pad cavity portion located in the upper portion of the second dielectric material layer 370.

[0108] Cavities 387 can be formed through the second dielectric material layer 370, such that surface segments of the first copper-containing metal interconnect structure 368 are exposed beneath each cavity 387. In one embodiment, a portion of the top surface of the first copper-containing metal interconnect structure 368 can be vertically recessed during the formation of the cavity 387. In one embodiment, the solid exposed surface of the first copper-containing metal interconnect structure 368 may include a recessed surface segment of the first copper-containing metal interconnect structure 368 and at least one sidewall surface segment of the first copper-containing metal interconnect structure 368. In one embodiment, the periphery of the recessed surface segment coincides with the bottom periphery of at least one sidewall surface segment. In one embodiment, the vertical recess distance of the recessed surface segment of the first copper-containing metal interconnect structure 368 relative to the topmost surface segment of the first copper-containing metal interconnect structure 368 can be in the range of 1 nm to 60 nm, for example, 3 nm to 20 nm, although smaller and larger vertical recess distances can also be used.

[0109] Reference Figure 2K Each solid exposed surface portion of the first copper-containing metal interconnect structure 368 can be transformed into a copper-based tunneling barrier layer 369. Each such copper-based tunneling barrier layer 369 is formed as a local film on a surface segment of the top surface of the corresponding first copper-containing metal interconnect structure 368, and is referred to herein as a local copper-based tunneling barrier layer 369L. Generally, each copper-based tunneling barrier layer 369 can be formed by exposing a surface portion of the first copper-containing metal interconnect structure 368 to a gaseous environment, which includes an oxidizing gas or a nitriding gas in a temperature range of 10 degrees Celsius to 450 degrees Celsius. In one embodiment, the gaseous environment may include at least one of ammonia, oxygen, ozone gas, nitrous oxide (N2O) gas, nitric oxide (NO) gas, and nitrogen dioxide (NO2) gas.

[0110] In one embodiment, the copper-based tunnel barrier layer 369 can be formed by performing at least one of a thermal oxidation process and a thermal nitriding process. In this embodiment, the temperature rise of the thermal oxidation process can be in the range of 200 degrees Celsius to 450 degrees Celsius, and preferably in the range of 250 degrees Celsius to 400 degrees Celsius. Alternatively, the copper-based tunnel barrier layer 369 can be formed by performing at least one of a plasma oxidation process and a plasma nitriding process. In one embodiment, the copper-based tunnel barrier layer 369 may include a dielectric material selected from copper oxide, copper nitride, or copper oxynitride.

[0111] According to one embodiment of this disclosure, when an electrical bias voltage greater than 0.5V is applied to the copper-based tunneling barrier layer 369, each copper-based tunneling barrier layer 369 has a thickness that provides for charge tunneling. In one embodiment, each copper-based tunneling barrier layer 369 may have a thickness in the range of 0.5nm to 2.0nm.

[0112] Generally, each copper-based tunneling barrier layer 369 can be formed by performing at least one of a surface oxidation process and a surface nitriding process. The copper-based tunneling barrier layer 369 is formed on a surface segment of the top surface of the corresponding first copper-containing metal interconnect structure 368, and this surface segment is smaller than the entire top surface of the corresponding first copper-containing metal interconnect structure 368.

[0113] In one embodiment, the copper-based tunneling barrier layer 369 can be formed by a combination of oxidation and nitriding processes, resulting in nitrogen and oxygen concentration gradients within the copper-based tunneling barrier layer 369. In this embodiment, the oxidation process can be performed before or after the nitriding process. In one embodiment, the copper-based tunneling barrier layer 369 may comprise a heterogeneous copper oxynitride material, resulting in nitrogen and oxygen concentration gradients within the copper-based tunneling barrier layer 369. In the horizontal extension of the copper-based tunneling barrier layer 369, the atomic concentration of oxygen atoms can increase or decrease along the vertical direction. Similarly, in the horizontal extension of the copper-based tunneling barrier layer 369, the atomic concentration of nitrogen atoms can decrease or increase along the vertical direction. In this embodiment, the atomic concentrations of oxygen atoms and nitrogen atoms can be changed in a complementary manner (i.e., in opposite directions).

[0114] Reference Figure 2L A second metal barrier liner may be deposited over the second dielectric material layer 370 and in the peripheral region of the cavity 387. The second metal barrier liner serves as a conductive base layer, facilitating subsequent copper plating by providing a uniform, conductive surface for copper plating. The second metal barrier liner may be deposited by physical vapor deposition (PVD), which can provide high consistency and thickness uniformity across the varying morphology of the second dielectric material layer 370. In one embodiment, the second metal barrier liner may comprise a stack comprising a metal barrier material layer such as tantalum or tantalum nitride (Ta / TaN) and a covering copper layer. The second metal barrier liner includes a horizontal extension covering the horizontal top surface of the second dielectric material layer 370 and a vertical extension projecting downwards from the horizontal extension into the peripheral region of a corresponding cavity 387. The thickness of the metal barrier liner may range from 30 nm to 200 nm, although smaller and larger thicknesses are also possible.

[0115] An electroplating process can be performed to electroplat a metallic material, which can be any electroplatable material known in the art. In one embodiment, the electroplated metallic material can be substantially composed of copper. A planarization process, such as chemical mechanical polishing, can be performed to remove portions of the electroplated metallic material and the second metal barrier pad layer from above a horizontal plane including the top surface of the second dielectric material layer 370. Each remaining portion of the second metal barrier pad layer includes a second metal barrier pad 388B. Each remaining portion of the electroplated metallic material includes a second electroplated material portion 388M. Each consecutive combination of the second metal barrier pad 388B and the second electroplated material portion 388M constitutes a second copper-containing metal interconnect structure 388.

[0116] In one embodiment, a horizontal extension of the copper-based tunneling barrier layer 369 is inserted between a first copper-containing metal interconnect structure 368 and a second copper-containing metal interconnect structure 388. The second copper-containing metal interconnect structure 388 can be formed directly on the horizontal extension of the copper-based tunneling barrier layer 369 and can be perpendicularly spaced from the first copper-containing metal interconnect structure 368 through the horizontal extension of the copper-based tunneling barrier layer 369. The copper-based tunneling barrier layer 369 can have a uniform thickness.

[0117] Figures 3A to 3D This is a continuous vertical cross-sectional view of the region of an exemplary structure during the formation of a copper-containing metal interconnect structure (first copper-containing metal interconnect structure 368, second copper-containing metal interconnect structure 388) and a copper-based tunnel barrier layer 369, according to a second embodiment of this disclosure.

[0118] Reference Figure 3A This describes an exemplary structure according to the second embodiment of the present disclosure after the formation of the second dielectric material layer 370. Exemplary Structure Description Figure 3A It can be related to... Figure 2I The exemplary structure described in the first embodiment according to this disclosure is the same.

[0119] refer to Figure 3B ,about Figure 2I The described process steps can be performed by modifying the anisotropic etching chemistry. Specifically, the anisotropic etching chemistry can be highly selective for the material of the first electroplated material portion 368M, which can be a copper portion. In this embodiment, the cavity 387 can be formed through the second dielectric material layer 370, such that the solidly exposed surface segment of the first copper-containing metal interconnect structure 368 is not recessed. Therefore, the solidly exposed surface segment of the first copper-containing metal interconnect structure 368 can be coplanar with the non-solidly exposed top surface segment of the first copper-containing metal interconnect structure 368.

[0120] refer to Figure 3CIt can execute about Figure 2K The described processing steps transform the exposed surface portion of each physical component of the first copper-containing metal interconnect structure 368 into a copper-based tunneling barrier layer 369. Each such copper-based tunneling barrier layer 369 can be formed on a surface segment of the top surface of the corresponding first copper-containing metal interconnect structure 368 as a local film, and is referred to herein as a local copper-based tunneling barrier layer 369L. (The last sentence appears to be incomplete and possibly refers to a different process.) Figure 2K Any of the described processing steps forms a copper-based tunnel barrier layer 369, therefore the copper-based tunnel barrier layer 369 can have the following characteristics: Figure 2K Any of the characteristics described. Each copper-based tunnel barrier layer 369 may be formed on a surface segment of the top surface of the corresponding first copper-containing metal interconnect structure 368, the surface segment being smaller than the entire top surface of the corresponding first copper-containing metal interconnect structure 368.

[0121] refer to Figure 3D It can execute about Figure 2L The described processing steps form a second copper-containing metal interconnect structure 388 in each cavity 387. Each copper-based tunneling barrier layer 369 may consist of a horizontally extending portion. In one embodiment, the copper-based tunneling barrier layer 369 may be inserted between the first copper-containing metal interconnect structure 368 and the second copper-containing metal interconnect structure 388. The second copper-containing metal interconnect structure 388 may be formed directly on the copper-based tunneling barrier layer 369 and may be perpendicularly spaced from the first copper-containing metal interconnect structure 368 by the copper-based tunneling barrier layer 369. The copper-based tunneling barrier layer 369 may have a uniform thickness.

[0122] Figures 4A to 4F This is a continuous vertical cross-sectional view of the region of an exemplary structure during the formation of a copper-containing metal interconnect structure (first copper-containing metal interconnect structure 368, second copper-containing metal interconnect structure 388) and a copper-based tunnel barrier layer 369, according to the third embodiment of this disclosure.

[0123] refer to Figure 4A This illustrates an exemplary structure according to a third embodiment of the present disclosure after the formation of the first copper-containing metal interconnect structure 368. Figure 4A The exemplary structure described can be used in conjunction with, according to, the information provided. Figure 2G The exemplary structure of the first embodiment of the present disclosure is the same.

[0124] refer to Figure 4BEach exposed surface of the first copper-containing metal interconnect structure 368 can be transformed into a copper-based tunneling barrier layer 369. Each such copper-based tunneling barrier layer 369 can be a continuous layer of material encapsulating the corresponding first copper-containing metal interconnect structure 368, and is referred to herein as an encapsulated copper-based tunneling barrier layer 369E. Each copper-based tunneling barrier layer 369 is formed on the top surface and at least one sidewall of the corresponding first copper-containing metal interconnect structure 368. In one embodiment, each encapsulated copper-based tunneling barrier layer 369E contacts the top surface and each sidewall of the corresponding first copper-containing metal interconnect structure 368. Generally, each copper-based tunneling barrier layer 369 can be formed from the exposed surface portion of the first copper-containing metal interconnect structure 368 in a gaseous environment comprising an oxidizing gas or a nitriding gas in a temperature range of 10 degrees Celsius to 450 degrees Celsius. In one embodiment, the gaseous environment may include at least one of ammonia, oxygen, ozone, nitrous oxide (N2O), nitric oxide (NO), and nitrogen dioxide (NO2).

[0125] In one embodiment, the copper-based tunnel barrier layer 369 can be formed by performing at least one of a thermal oxidation process and a thermal nitriding process. In this embodiment, the temperature rise of the thermal oxidation process can be in the range of 200 degrees Celsius to 450 degrees Celsius, and preferably in the range of 250 degrees Celsius to 400 degrees Celsius. Alternatively, the copper-based tunnel barrier layer 369 can be formed by performing at least one of a plasma oxidation process and a plasma nitriding process. In one embodiment, the copper-based tunnel barrier layer 369 may include a dielectric material selected from copper oxide, copper nitride, or copper oxynitride.

[0126] According to one aspect of this disclosure, each copper-based tunneling barrier layer 369 has a thickness that provides charge tunneling when an electrical bias voltage greater than 0.5V is applied to the copper-based tunneling barrier layer 369. In one embodiment, each copper-based tunneling barrier layer 369 may have a thickness in the range of 0.5 nm to 2.0 nm.

[0127] Generally, each copper-based tunneling barrier layer 369 can be formed by performing at least one of a surface oxidation process and a surface nitriding process. The copper-based tunneling barrier layer 369 is formed on a surface segment of the top surface of the corresponding first copper-containing metal interconnect structure 368, the surface segment being equal to the entire top surface of the corresponding first copper-containing metal interconnect structure 368.

[0128] In one embodiment, the copper-based tunneling barrier layer 369 can be formed by a combination of oxidation and nitriding processes, resulting in nitrogen and oxygen concentration gradients within the copper-based tunneling barrier layer 369. In this embodiment, the oxidation process can be performed before or after the nitriding process. In one embodiment, the copper-based tunneling barrier layer 369 may include a non-uniform copper oxynitride material, resulting in nitrogen and oxygen concentration gradients within the copper-based tunneling barrier layer 369. The atomic concentration of oxygen atoms can increase or decrease along the vertical direction of the horizontal extension of the copper-based tunneling barrier layer 369. Similarly, the atomic concentration of nitrogen atoms can decrease or increase along the vertical direction of the horizontal extension of the copper-based tunneling barrier layer 369. In this embodiment, the atomic concentrations of oxygen atoms and nitrogen atoms can be changed in a complementary manner (i.e., in opposite directions).

[0129] refer to Figure 4C Interlayer dielectric (ILD) material can be deposited over the first copper-containing metal interconnect structure 368 and the first via-level dielectric layer 354. Planarization processes such as chemical mechanical polishing can be performed to remove a portion of the ILD material from a horizontal plane including the top surface of the copper-based tunnel barrier layer 369. In one embodiment, the thickness of the horizontal extension of the copper-based tunnel barrier layer 369 covering the first copper-containing metal interconnect structure 368 can be reduced during the planarization process. The remaining portion of the ILD material constitutes the first line-level dielectric layer 356. An optional combination of the first overlay passivation layer 352, the first via-level dielectric layer 354, and the first line-level dielectric layer 356 is referred to herein as the first dielectric material layer 350. The first copper-containing metal interconnect structure 368 can be formed embedded in the first dielectric material layer 350.

[0130] refer to Figure 4D Optional second cover passivation layer 372 and second interconnect-level dielectric layer 374 may be formed over the first dielectric material layer 350. Optional second cover passivation layer 372 and second interconnect-level dielectric layer 374 are collectively referred to herein as second dielectric material layer 370. Second cover passivation layer 372 includes at least one diffusion barrier dielectric material, such as silicon nitride, silicon oxynitride, or silicon carbonitride. Second cover passivation layer 372 may be formed by chemical vapor deposition and may have a thickness in the range of 3 nm to 30 nm, although smaller and larger thicknesses may also be used. Second interconnect-level dielectric layer 374 includes an interlayer dielectric (ILD) material, such as silicate glass. The thickness of second interconnect-level dielectric layer 374 may be in the range of 200 nm to 6000 nm, for example, 400 nm to 3000 nm, although smaller and larger thicknesses may also be used. In an alternative implementation, a single dielectric material layer may be formed instead of a combination of a first via-level dielectric layer 354, an optional second cover passivation layer 372, and a second interconnect-level dielectric layer 374.

[0131] refer to Figure 4E A cavity 387 can be formed through the second dielectric material layer 370. For example, at least one patterned photoresist layer (not shown) can be formed above the second dielectric material layer 370, and each pattern in the at least one patterned photoresist layer can be transferred through the second dielectric material layer 370 by performing at least one anisotropic etching process. Generally, the cavity 387 can be formed through at least one additional dielectric material layer, such that a surface segment of the first copper-containing metal interconnect structure 368 or copper-based tunnel barrier layer 369 is exposed beneath each cavity 387. In one embodiment, the cavity 387 may include integrated pad and via cavities. In this embodiment, each cavity 387 may include a via cavity portion located in the lower portion of the second dielectric material layer 370 and a pad cavity portion located in the upper portion of the second dielectric material layer 370.

[0132] Cavities 387 can be formed through the second dielectric material layer 370, such that surface segments of the first copper-containing metal interconnect structure 368 are exposed beneath each cavity 387. In one embodiment, a portion of the top surface of the first copper-containing metal interconnect structure 368 can be vertically recessed during the formation of the cavity 387. In one embodiment, the solid recessed surface of the first copper-containing metal interconnect structure 368 may include a recessed surface segment of the first copper-containing metal interconnect structure 368 and at least one sidewall surface segment of the first copper-containing metal interconnect structure 368. In one embodiment, the periphery of the recessed surface segment coincides with the bottom periphery of at least one sidewall surface segment. In one embodiment, the vertical recess distance of the recessed surface segment of the first copper-containing metal interconnect structure 368 relative to the vertical recess distance of the topmost surface segment of the first copper-containing metal interconnect structure 368 can be in the range of 1 nm to 60 nm, for example, 3 nm to 20 nm, although smaller and larger vertical recess distances can also be used.

[0133] refer to Figure 4FA second metal barrier liner may be deposited over the second dielectric material layer 370 and in the peripheral region of the cavity 387. The second metal barrier liner serves as a conductive substrate, which facilitates subsequent copper plating by providing a uniform conductive surface on the copper (which may be plated). The second metal barrier liner may be deposited by physical vapor deposition (PVD), which can provide high consistency and thickness uniformity across the varying morphology of the second dielectric material layer 370. In one embodiment, the second metal barrier liner may comprise a layer stack comprising a metal barrier material layer such as tantalum or tantalum nitride (Ta / TaN) and a covering copper layer. The second metal barrier liner includes a horizontal extension covering the horizontal top surface of the second dielectric material layer 370 and a vertical extension projecting downwards from the horizontal extension into the peripheral region of a corresponding cavity. The thickness of the second metal barrier liner may range from 30 nm to 200 nm, although smaller and larger thicknesses are also possible.

[0134] An electroplating process can be performed to electroplat a metallic material, which can be any electroplatable material known in the art. In one embodiment, the electroplated metallic material can be substantially composed of copper. A planarization process, such as chemical mechanical polishing, can be performed to remove portions of the electroplated metallic material and the second metal barrier pad layer from above a horizontal plane including the top surface of the second dielectric material layer 370. Each remaining portion of the second metal barrier pad layer includes a second metal barrier pad 388B. Each remaining portion of the electroplated metallic material includes a second electroplated material portion 388M. Each consecutive combination of the second metal barrier pad 388B and the second electroplated material portion 388M constitutes a second copper-containing metal interconnect structure 388. The second copper-containing metal interconnect structure 388 can be formed directly on a recessed horizontal surface segment of the first copper-containing metal interconnect structure 368.

[0135] Figure 5A and Figure 5B This is a continuous vertical cross-sectional view of the region of an exemplary structure during the formation of a copper-containing metal interconnect structure (first copper-containing metal interconnect structure 368, second copper-containing metal interconnect structure 388) and a copper-based tunnel barrier layer 369, according to the fourth embodiment of this disclosure.

[0136] refer to Figure 5A This illustrates the region of an exemplary structure following the formation of the second dielectric material layer 370 and the cavity 387. Figure 5A The exemplary structure described herein can be derived from modifying the chemical composition of the anisotropic etching process that forms cavity 387. Figure 4EThe exemplary structure shown is illustrated. Specifically, the anisotropic etching chemistry can be a material highly selective for the copper-based tunnel barrier layer 369, which may include copper oxide, copper nitride, or copper oxynitride. In this embodiment, the cavity 387 can be formed through the second dielectric material layer 370, such that the solid exposed surface segments of the copper-based tunnel barrier layer 369 do not recess.

[0137] refer to Figure 5B It can execute about Figure 2L The process steps involve forming a second copper-containing metal interconnect structure 388 in each cavity 387. In one embodiment, a copper-based tunneling barrier layer 369 is inserted between the first copper-containing metal interconnect structure 368 and the second copper-containing metal interconnect structure 388. The second copper-containing metal interconnect structure 388 can be formed directly on the copper-based tunneling barrier layer 369 and can be perpendicularly spaced from the first copper-containing metal interconnect structure 368 by the copper-based tunneling barrier layer 369.

[0138] Figure 6A and Figure 6B This is a continuous vertical cross-sectional view of the region of an exemplary structure during the formation of a copper-containing metal interconnect structure (first copper-containing metal interconnect structure 368, second copper-containing metal interconnect structure 388) and a copper-based tunnel barrier layer 369, according to the fifth embodiment of this disclosure.

[0139] refer to Figure 6A The diagram shows a region of an exemplary structure after the formation of the second dielectric material layer 370 and the cavity 387. Figure 6A The exemplary structure described herein can be derived from modifying the chemical composition of the anisotropic etching process that forms cavity 387. Figure 4E The exemplary structure is shown. Specifically, the anisotropic etching chemistry can be a material selective for the copper-based tunnel barrier layer 369, which may include copper oxide, copper nitride, or copper oxynitride. The cavity 387 may extend through a portion of the upper surface of the copper-based tunnel barrier layer 369, but not perpendicularly through the entire copper-based tunnel barrier layer 369. In this embodiment, the cavity 387 may be formed through the second dielectric material layer 370, such that a solid exposed surface segment of the copper-based tunnel barrier layer 369 is recessed by a recess distance less than the thickness of the copper-based tunnel barrier layer 369.

[0140] refer to Figure 6B It can execute about Figure 2LThe described processing steps form a second copper-containing metal interconnect structure 388 in each cavity 387. In one embodiment, a copper-based tunneling barrier layer 369 is inserted between the first copper-containing metal interconnect structure 368 and the second copper-containing metal interconnect structure 388. The second copper-containing metal interconnect structure 388 may be formed directly on a thin portion of the copper-based tunneling barrier layer 369 and may be perpendicularly spaced from the first copper-containing metal interconnect structure 368 through the thin portion of the copper-based tunneling barrier layer 369. In one embodiment, the first portion of the copper-based tunneling barrier layer 369 inserted between the first and second copper-containing metal interconnect structures 368 has a smaller thickness than the second portion of the copper-based tunneling barrier layer 369 that contacts the first copper-containing metal interconnect structure 368 but does not contact the second copper-containing metal interconnect structure 388.

[0141] Figure 7A and Figure 7B This is a continuous vertical cross-sectional view of the region of an exemplary structure during the formation of a copper-containing metal interconnect structure (first copper-containing metal interconnect structure 368, second copper-containing metal interconnect structure 388) and a copper-based tunnel barrier layer 369, according to the sixth embodiment of this disclosure.

[0142] refer to Figure 7A The region of the exemplary structure is shown according to the sixth embodiment after the formation of the additional copper-based tunnel barrier layer 369. Figure 7A The exemplary structure shown can be derived by transforming the solid exposed surface of each first copper-containing metal interconnect structure 368 into an additional copper-based tunneling barrier layer 369. Figure 4E The exemplary structure is shown. Specifically, the proximal portion of each first copper-containing metal interconnect structure 368 located beneath the respective cavity 387 can be transformed into an additional copper-based tunneling barrier layer 369. Each such copper-based tunneling barrier layer 369 is formed on a surface segment of the top surface of the respective first copper-containing metal interconnect structure 368, which serves as a local film. Generally, each local copper-based tunneling barrier layer 369L can be formed by exposing the surface portion of the first copper-containing metal interconnect structure 368 to a gaseous environment comprising an oxidizing gas or a nitriding gas in a temperature range of 10 degrees Celsius to 450 degrees Celsius. In one embodiment, the gaseous environment may include at least one of ammonia, oxygen, ozone gas, nitrous oxide (N2O) gas, nitric oxide (NO) gas, and nitrogen dioxide (NO2) gas.

[0143] In one embodiment, the localized copper-based tunnel barrier layer 369L can be formed by performing at least one of a thermal oxidation process and a thermal nitriding process. In this embodiment, the temperature rise of the thermal oxidation process can be in the range of 200 degrees Celsius to 450 degrees Celsius, and preferably in the range of 250 degrees Celsius to 400 degrees Celsius. Alternatively, the localized copper-based tunnel barrier layer 369L can be formed by performing at least one of a plasma oxidation process and a plasma nitriding process. In one embodiment, the localized copper-based tunnel barrier layer 369L may comprise a dielectric material selected from copper oxide, copper nitride, or copper oxynitride.

[0144] According to one aspect of this disclosure, each local copper-based tunneling barrier layer 369L has a thickness that provides charge tunneling when an electrical bias voltage greater than 0.5V is applied to the local copper-based tunneling barrier layer 369L. In one embodiment, each local copper-based tunneling barrier layer 369L may have a thickness in the range of 0.5 nm to 2.0 nm.

[0145] Generally, each local copper-based tunneling barrier layer 369L can be formed by performing at least one of a surface oxidation process and a surface nitriding process. The local copper-based tunneling barrier layer 369L is formed on a surface segment of the top surface of the corresponding first copper-containing metal interconnect structure 368, and this surface segment is smaller than the entire top surface of the corresponding first copper-containing metal interconnect structure 368.

[0146] In one embodiment, a localized copper-based tunneling barrier layer 369L can be formed by a combination of oxidation and nitriding processes, resulting in nitrogen and oxygen concentration gradients within the localized copper-based tunneling barrier layer 369L. In this embodiment, the oxidation process can be performed before or after the nitriding process. In one embodiment, the localized copper-based tunneling barrier layer 369L may comprise a heterogeneous copper oxynitride material, resulting in nitrogen and oxygen concentration gradients within the localized copper-based tunneling barrier layer 369L. In the horizontal extension of the localized copper-based tunneling barrier layer 369L, the atomic concentration of oxygen atoms can increase or decrease along the vertical direction. Similarly, the atomic concentration of nitrogen atoms can decrease or increase along the vertical direction in the horizontal extension of the localized copper-based tunneling barrier layer 369L. In this embodiment, the atomic concentrations of oxygen atoms and nitrogen atoms can be changed in a complementary manner (i.e., in opposite directions).

[0147] refer to Figure 7B It can execute about Figure 2LThe process steps involve forming a second copper-containing metal interconnect structure 388 in each cavity 387. In one embodiment, a partial copper-based tunneling barrier layer 369L is inserted between the first and second copper-containing metal interconnect structures 368. The second copper-containing metal interconnect structure 388 can be formed directly on the partial copper-based tunneling barrier layer 369L and can be perpendicularly spaced from the first copper-containing metal interconnect structure 368 through the partial copper-based tunneling barrier layer 369L. In one embodiment, each partial copper-based tunneling barrier layer 369L can contact the top surface and sidewalls of the first copper-containing metal interconnect structure 368.

[0148] Figure 8A and Figure 8B This is a continuous vertical cross-sectional view of the region of an exemplary structure during the formation of a copper-containing metal interconnect structure (first copper-containing metal interconnect structure 368, second copper-containing metal interconnect structure 388) and a copper-based tunnel barrier layer 369, according to the seventh embodiment of this disclosure.

[0149] refer to Figure 8A The region of the exemplary structure according to the seventh embodiment is shown after the formation of the additional copper-based tunnel barrier layer 369. Figure 8A The exemplary structure described can be derived by transforming the surface portion of each first copper-containing metal interconnect structure 368, which lies beneath the corresponding cavity 387 and encapsulates the copper-based tunnel barrier layer 369E, into an additional copper-based tunnel barrier layer 369. Figure 5A The exemplary structure is illustrated below. A surface portion of each first copper-containing metal interconnect structure 368 is converted to a copper-based dielectric material (e.g., copper oxide, copper nitride, or copper oxynitride), and merges with a covering portion encapsulating the copper-based tunnel barrier layer 369E to become a partial copper-based tunnel barrier layer 369L. In one embodiment, the partial copper-based tunnel barrier layer 369L has a thickness greater than the thickness of the encapsulating copper-based tunnel barrier layer 369E.

[0150] In one embodiment, the partial copper-based tunneling barrier layer 369L may have a different material composition than the encapsulated copper-based tunneling barrier layer 369E. In one embodiment, the encapsulated copper-based tunneling barrier layer 369E can be formed by performing an oxidation process and may include copper oxide, while the partial copper-based tunneling barrier layer 369L can be formed by performing a nitriding process and may include copper nitride or copper oxynitride. In another embodiment, the encapsulated copper-based tunneling barrier layer 369E can be formed by performing a nitriding process and may include copper nitride, while the partial copper-based tunneling barrier layer 369L can be formed by performing an oxidation process and may include copper oxide or copper oxynitride.

[0151] Figure 9A and Figure 9BThis is a continuous vertical cross-sectional view of the region of an exemplary structure during the formation of a copper-containing metal interconnect structure (first copper-containing metal interconnect structure 368, second copper-containing metal interconnect structure 388) and a copper-based tunnel barrier layer 369, according to the eighth embodiment of this disclosure.

[0152] refer to Figure 9A The region of the exemplary structure according to the eighth embodiment is shown after the formation of the additional copper-based tunnel barrier layer 369. Figure 9A The exemplary structure described herein arises from transforming the surface portion of each first copper-containing metal interconnect structure 368, which lies beneath the corresponding cavity 387 and encapsulates a horizontally extending thin portion of a copper-based tunnel barrier layer 369E, into an additional copper-based tunnel barrier layer 369. Figure 6A The exemplary structure is shown in the figure. A surface portion of each first copper-containing metal interconnect structure 368 is converted into a copper-based dielectric material (e.g., copper oxide, copper nitride, or copper oxynitride) and merged with a covering portion encapsulating the copper-based tunnel barrier layer 369E to become a partial copper-based tunnel barrier layer 369L. In one embodiment, the thickness of the partial copper-based tunnel barrier layer 369L may be equal to, less than, or greater than the thickness of the encapsulating copper-based tunnel barrier layer 369E.

[0153] In one embodiment, the partial copper-based tunneling barrier layer 369L may have a different material composition than the encapsulated copper-based tunneling barrier layer 369E. In one embodiment, the encapsulated copper-based tunneling barrier layer 369E can be formed by performing an oxidation process and may include copper oxide, while the partial copper-based tunneling barrier layer 369L can be formed by performing a nitriding process and may include copper nitride or copper oxynitride. In another embodiment, the encapsulated copper-based tunneling barrier layer 369E can be formed by performing a nitriding process and may include copper nitride, while the partial copper-based tunneling barrier layer 369L can be formed by performing an oxidation process and may include copper oxide or copper oxynitride.

[0154] Figures 10A to 10H This is a vertical cross-sectional view of a region of an exemplary structure according to an additional embodiment of this disclosure. Generally speaking, Figures 10A to 10H Additional embodiments of this disclosure may arise from the formation of at least one copper-based tunnel barrier layer 349 on a metal interconnect structure 340 that is below and closest to the first copper-containing metal interconnect structure 368. Figures 2A to 9B In any of the embodiments described, at least one copper-based tunneling barrier layer 349 may include a partial copper-based tunneling barrier layer 349L and / or an encapsulated copper-based tunneling barrier layer 349E. Although Figures 10A to 10H Each of the examples illustrates a corresponding set of at least one copper-based tunnel barrier layer 349 in a specific configuration, and it should be understood that... Figures 10A to 10H Each configuration of the group of at least one copper-based tunnel barrier layer 349 shown can be Figures 10A to 10H It can be used in any of the exemplary structures shown. In addition, any configuration of at least one copper-based tunnel barrier layer 369 relative to the first copper-containing metal interconnect structure 368 can be used for at least one copper-based tunnel barrier layer 349 relative to the metal interconnect structure 340.

[0155] refer to Figure 11 This illustrates an exemplary structure after the formation of the second copper-containing metal interconnect structure 388. In one embodiment, the second copper-containing metal interconnect structure 388 may include active bonding pads 388A electrically connected to a subset of corresponding metal interconnect structures 340 and metal interconnect structure 362, the metal interconnect structures 340 being embedded in an interconnect-level dielectric layer 330, and the metal interconnect structure 362 being embedded in a first dielectric layer 350. Further, the second copper-containing metal interconnect structure 388 may include dummy bonding pads 388D, which are electrically isolated from the metal interconnect structure 340 and electrically connected to the metal interconnect structure 364. The active bonding pads 388A and dummy bonding pads 388D are collectively referred to as bonding pads (second copper-containing metal interconnect structure 388). In one embodiment, the semiconductor substrate 309 may be provided as a semiconductor wafer, and a plurality of second semiconductor dies 300 may be formed on top of the semiconductor wafer. In this embodiment, a dicing process may be performed to singulate the plurality of second semiconductor dies 300.

[0156] refer to Figure 12A and Figure 12BThis diagram illustrates a reconstructed wafer comprising a two-dimensional array of a carrier substrate 810 and a first semiconductor die 100. The carrier substrate 810 can be any type of carrier substrate suitable for supporting an array of semiconductor dies on the carrier substrate 810. For example, the carrier substrate 810 can be a glass substrate, a semiconductor substrate, or a conductive substrate. The carrier substrate 810 can have a circular shape in a plan view. In other embodiments (not shown), the carrier substrate can have a rectangular shape or any other shape suitable for supporting an array of semiconductor dies on the carrier substrate. The first semiconductor die 100 can be any type of semiconductor die known in the art. For example, the first semiconductor die 100 can include logic dies, including at least one central processing unit (CPU), at least one graphics processing unit (GPU), at least one neural processing unit (NPU), at least one memory array, and / or any other type of semiconductor device known in the art. The array of the first semiconductor dies 100 can be attached to the carrier substrate 810 using an adhesive layer 811. The array of the first semiconductor dies 100 can be arranged as a periodic two-dimensional array. The region that constitutes the smallest repeating unit in a periodic two-dimensional array is referred to as the cell region UA ​​in this paper.

[0157] In one embodiment, each first semiconductor die 100 may be attached to a carrier substrate 810 via an adhesive layer 811. The adhesive layer 811 may be a thermally degradable adhesive layer, such as a polyimide layer, or a UV-degradable adhesive layer, such as ultraviolet-sensitive tape. The first semiconductor die 100 may include a first semiconductor substrate 109, a first semiconductor device 120 located on the first semiconductor substrate 109, a first metal interconnect structure 180 formed within a first interconnect dielectric layer 160, a first bonding dielectric layer 190, and a package bonding structure 188 formed within the first bonding dielectric layer 190. The package bonding structure 188 serves as the bonding structure for subsequently formed composite dies and may be configured for solder-mediated bonding (e.g., wafer-to-wafer bonding, i.e., microbump bonding or controlled collapse wafer-to-wafer bonding, i.e., C4 bonding) or may be configured for metal-to-metal bonding. The first grain edge sealing ring structure 170 can extend vertically through the first interconnect level dielectric material layer 160 and the first bonding level dielectric layer 190, and can laterally surround the entire first metal interconnect structure 180.

[0158] The first semiconductor device 120 may include any semiconductor device known in the art, such as a field-effect transistor and a passive element. A first shallow trench isolation structure 112 may be provided within the first semiconductor substrate 109 such that adjacent pairs of first semiconductor devices 120 are electrically isolated from each other. The first semiconductor die 100 may include a substrate through-hole structure 114 extending vertically through the first semiconductor substrate 109 and optionally through a subset of the first interconnect level dielectric material layer 160. The substrate through-hole structure 114 may be electrically isolated from the first semiconductor substrate 109 by a dielectric pad 113. A first back-side dielectric layer 117 may be provided on the back side of the first semiconductor substrate 109. In this embodiment, the substrate through-hole structure 114 may extend vertically through the first back-side dielectric layer 117. In one embodiment, the substrate through-hole structure 114 may be arranged in a periodic pattern having the same periodicity as the pattern of the first active bonding pad subsequently formed over the first back-side dielectric layer 117. Each first semiconductor die 100 may be solidly exposed.

[0159] refer to Figure 13 A first molding compound may be applied to the gap between adjacent pairs of first semiconductor grains 100. The first molding compound may include an epoxy compound, which may be hardened (i.e., cured) to provide a dielectric material portion with sufficient stiffness and mechanical strength. The first molding compound may include epoxy resin, a hardener, silica (as a filler), and other additives. The first molding compound may be provided in liquid or solid form depending on viscosity and flowability. Liquid first molding compounds offer better workability, good flowability, fewer voids, better filling, and fewer flow marks. Solid molding compounds offer less curing shrinkage, better isolation, and less mold drift. A high filler content (e.g., 85% by weight) in the molding compound can shorten the time in the mold, reduce mold shrinkage, and reduce mold warpage. A uniform filler size distribution in the molding compound can reduce flow marks and enhance flowability. In embodiments where the adhesive layer 811 includes a heat-release material, the curing temperature of the molding compound may be lower than the release (peel) temperature of the adhesive layer 811. For example, the curing temperature of the first molding compound can be in the range of 125°C to 150°C.

[0160] A first molding compound can be cured at a curing temperature to form a first molding compound matrix 260 that laterally surrounds a two-dimensional array of first semiconductor grains 100. The first molding compound matrix 260 includes a plurality of first molding compound grain frames interconnected with other first molding compound grain frames. Each first molding compound grain frame is part of the first molding compound matrix 260, which is located within a region of repeating cells in a two-dimensional periodic array covering the carrier substrate 810. Therefore, each first molding compound grain frame laterally surrounds and embeds itself into a corresponding first semiconductor grain 100.

[0161] A portion of the first molding compound matrix 260 covers a horizontal plane, which includes the top surface of the first semiconductor die 100 that can be removed by a planarization process. For example, chemical mechanical planarization (CMP) can be used to remove the portion of the first molding compound matrix 260 covering the horizontal plane. The combination of the remaining portion of the first molding compound matrix 260 and the array of the first semiconductor dies 100 includes reconstructing the wafer. Each portion of the first molding compound matrix 260 located within the cell region UA ​​constitutes a first molding compound die framework. Generally, the first molding compound matrix 260 can be formed around the first semiconductor die 100 such that the top surface of the first molding compound matrix 260 is coplanar with the top dielectric surface of the first semiconductor die 100.

[0162] refer to Figure 14 A combination of at least one bonding level dielectric layer 220 and a first bonding pad 228 may be formed over the first semiconductor die 100 and the first molding compound matrix 260. The first bonding pad 228 may include a first active bonding pad 228A electrically connected to a corresponding first metal interconnect structure 180, and may also include a first dummy bonding pad 228D not electrically connected to any other conductive structure. Each first active bonding pad 228A may be formed directly on a corresponding conductive structure (e.g., substrate through-hole structure 114) within the first semiconductor die 100. Each portion of the exemplary structure within the cell region UA ​​is referred to herein as a first molding die unit 200, which includes a first die group of the first semiconductor die 100 and a portion of the first molding compound matrix 260, as well as a combination of at least one bonding level dielectric layer 220, the first active bonding pad 228A, and the first dummy bonding pad 228D located within the cell region UA.

[0163] Generally, each first virtual bonding pad 228D may have the same material composition as the first active bonding pad 228A, or it may have a different material composition. In one embodiment, all first virtual bonding pads 228D may have the same material composition as the first active bonding pad 228A. In another embodiment, all first virtual bonding pads 228D may have a different material composition than the first active bonding pad 228A. At least one bonding level dielectric layer 220 may include a single bonding level dielectric layer 220 or may include multiple bonding level dielectric layers 220.

[0164] refer to Figure 15 A second semiconductor die 300 having a second bonding pad (which may include a second metal interconnect structure 388) can be bonded to a corresponding one of the first semiconductor dies 100 via a metal-to-metal bonding process. The second semiconductor die 300 can be associated with... Figure 11 The second semiconductor die 300 described is the same as and uses the information about Figures 1 to 4F The process steps described herein are formed. The bonding pads of the second semiconductor die 300 are hereinafter referred to as second bonding pads (which may include second metal interconnect structures 388). Generally, in embodiments where similar structural elements exist in the first semiconductor die 100, each structural element in the second semiconductor die 300 may be referred to hereinafter as a second structural element.

[0165] Multiple second semiconductor dies 300 can be bonded to multiple first semiconductor dies 100. Each second semiconductor die 300 can be bonded to a corresponding first semiconductor die 100 by performing a bonding process that bonds the second bonding pads of the second semiconductor die 300 (which may include second metal interconnect structures 388) to first bonding pads 228 within a corresponding cell region UA ​​of the first semiconductor die 100 via metal-to-metal bonding. In one embodiment, a first active bonding pad 228A can be bonded to a second active bonding pad 388A, and a first dummy bonding pad 228D can be bonded to a second dummy bonding pad 388D.

[0166] Each second semiconductor die 300 may include a second semiconductor substrate 309, a second semiconductor device 320 located on the second semiconductor substrate 309, a second metal interconnect structure 340 formed within a second interconnect dielectric layer 330, a second dielectric layer 370, and a second bonding pad (which may include the second metal interconnect structure 388) formed within the second dielectric layer 370. The second bonding pad (which may include the second metal interconnect structure 388) may be configured for metal-to-metal bonding, such as copper-to-copper bonding. As used herein, metal-to-metal bonding refers to the direct bonding of metal surfaces without the use of intermediate adhesives or solders. Metal-to-metal bonding can be provided between two metal surfaces in direct contact by thermocompression bonding and / or diffusion bonding by performing an annealing process at elevated temperatures.

[0167] The edge sealing ring structure 344 of the second die (which may also be referred to as edge sealing ring structure 344) may extend vertically through the second interconnect layer dielectric material layer 330 and the second dielectric material layer 370, and may laterally surround the entire second metal interconnect structure 340. The second semiconductor device 320 may include any semiconductor device known in the art, such as field-effect transistors and passive elements. A second shallow trench isolation structure 312 may be provided within the second semiconductor substrate 309 such that adjacent pairs of second semiconductor devices 320 are electrically isolated from each other. All sidewalls of the second semiconductor die 300 may be solidly exposed.

[0168] The second active bonding pad 388A can be bonded to the first active bonding pad 228A via a metal-to-metal bond, such as a copper-to-copper bond. The second dummy bonding pad 388D can be bonded to the first dummy bonding pad 228D via a metal-to-metal bond, such as a copper-to-copper bond. Furthermore, the horizontal bottom surface of the second dielectric material layer 370 can be bonded to the top surface of at least one bonding level dielectric layer 220 via a dielectric-to-dielectric bond, such as a silicon oxide-to-silicon oxide bond.

[0169] In one embodiment, the second semiconductor die 300 includes an edge sealing ring structure 344 extending continuously along all sidewalls of the second semiconductor die 300. In one embodiment, at least one first virtual bonding pad 228D within a first subset of the first virtual bonding pads 228D overlaps with the edge sealing ring structure 344 in a plan view. Alternatively or additionally, at least one first virtual bonding pad 228D within the first subset of the first virtual bonding pads 228D is at least partially surrounded by the edge sealing ring structure 344 in a plan view within a region. Alternatively or additionally, at least one first virtual bonding pad 228D within the first subset of the first virtual bonding pads 228D is at least partially located within a frame-shaped region between the outer periphery of the edge sealing ring structure 344 in a plan view and the sidewalls of the second semiconductor die 300.

[0170] refer to Figure 16A and Figure 16B A second molding compound matrix 460 may be formed around the second semiconductor grain 300. Specifically, the second molding compound may be applied to the gaps between adjacent pairs of second semiconductor grains 300. The second molding compound may include any material that can be used as the first molding compound. Generally, the second molding compound and the first molding compound may have the same material composition or may have different material compositions. The second molding compound may be cured at a curing temperature to form a second molding compound matrix 460 that laterally surrounds a two-dimensional array of second semiconductor grains 300. The second molding compound matrix 460 includes a plurality of second molding compound grain frames interconnected with each other. Each second molding compound grain frame is part of the second molding compound matrix 460 and is located within a region of repeating units in a two-dimensional periodic structural array covering the carrier substrate 810. Thus, each second molding compound grain frame laterally surrounds and embeds itself into a corresponding second semiconductor grain 300.

[0171] The second molding compound matrix 460 partially covers a horizontal plane, which includes the top surface of the second semiconductor die 300 that can be removed by a planarization process. For example, the second molding compound matrix 460 partially covers a horizontal plane that can be removed using chemical mechanical planarization (CMP). The remaining portion of the second molding compound matrix 460, combined with the array of the second semiconductor die 300, comprises second molding die units 400. Each second molding die unit 400 includes a second semiconductor die 300 located within a cell region UA ​​and a portion of the second molding compound matrix 460. Each portion of the second molding compound matrix 460 is located within a cell region UA ​​that forms the framework of the second molding compound die. Generally, the second molding compound matrix 460 can be formed around the second semiconductor die 300 such that the top surface of the second molding compound matrix 460 is coplanar with the top surface of the second semiconductor die 300. Each vertical stack of the first molding die unit 200 and the second molding die unit 400 constitutes a composite die 900. A two-dimensional array of composite grains 900 can be formed above the carrier substrate 810.

[0172] Subsequently, the carrier substrate 810 can be separated from the reconstructed wafer comprising the two-dimensional array of composite grains 900 by decomposing the adhesive layer 811. A thermal annealing process or an ultraviolet irradiation process can be used to decompose the adhesive layer 811. A suitable cleaning process can be performed to clean the solid exposed surfaces of the first bonding level dielectric layer 190 and the package bonding structure 188.

[0173] The reconstructed wafer can be diced along a dicing channel to divide the composite dies 900. Each composite die 900 includes components of a first semiconductor die 100, a first molding compound matrix 260 (which is a first molding compound die framework), at least one bonding level dielectric layer 220, a combination of a first active bonding pad 228A and a first virtual bonding pad 228D, a second semiconductor die 300 including a second bonding pad (which may include a second metal interconnect structure 388) bonded to the first active bonding pad 228A via metal-to-metal bonding, and a second molding compound matrix 460 (which is a second molding compound die framework). In one embodiment, each composite die 900 may have a pair of first sidewalls parallel to a first horizontal direction hd1 and a pair of second sidewalls parallel to a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0174] refer to Figure 17 The first flowchart illustrates the steps of forming an apparatus structure according to an embodiment of the present disclosure.

[0175] Refer to step 1710 and Figure 1 , Figures 2A to 2G , Figure 3A , Figure 10A , Figure 10B and Figures 10F to 10H A first copper-containing metal interconnect structure 368 is formed within the first dielectric material layer 350.

[0176] Refer to step 1720 and Figure 2H , Figure 2I , Figure 3A , Figure 10A , Figure 10B and Figures 10F to 10H The second dielectric material layer 370 can be formed above the first copper-containing metal interconnect structure 368 and the first dielectric material layer 350.

[0177] Refer to step 1730 and Figure 2J , Figure 3B , Figure 10A , Figure 10B and Figures 10F to 10H The cavity 387 can be formed through the second dielectric material layer 370, so that the surface segments of the first copper-containing metal interconnect structure 368 are exposed under the cavity 387.

[0178] Refer to step 1740 and Figure 2K , Figure 3C , Figure 10A , Figure 10B and Figures 10F to 10H The surface portion of the first copper-containing metal interconnect structure 368 can be transformed into a copper-based tunnel barrier layer 369.

[0179] Refer to step 1750 and Figure 2L , Figure 3D , Figure 10A , Figure 10B and Figures 10F to 10H The second copper-containing metal interconnect structure 388 can be formed in the cavity 387 on the copper-based tunnel barrier layer 369.

[0180] refer to Figure 18 The second flowchart illustrates the steps of forming an apparatus structure according to an embodiment of the present disclosure.

[0181] Refer to step 1810 and Figure 1 , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figures 10C to 10H The first copper-containing metal interconnect structure 368 may be formed above the first dielectric material layer, such as an optional first cover passivation layer 352 and a first via-level dielectric layer 354.

[0182] Refer to step 1820 and Figure 4B , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figures 10C to 10H The surface portion of the first copper-containing metal interconnect structure 368 can be transformed into a copper-based tunnel barrier layer 369.

[0183] Refer to step 1830 and Figure 4C , Figure 4D , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figures 10C to 10H At least one additional dielectric material layer (first line-level dielectric layer 356, second dielectric material layer 370) may be formed above the first dielectric material layer (first cover passivation layer 352, first via-level dielectric layer 354) and the copper-based tunnel barrier layer 369.

[0184] Refer to step 1840 and Figure 4E , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figures 10C to 10HThe cavity 387 can pass through at least one additional dielectric material layer (first line-level dielectric layer 356, second dielectric material layer 370), so that surface segments of the first copper-containing metal interconnect structure 368 or copper-based tunnel barrier layer 369 are exposed under the cavity 387.

[0185] Refer to step 1850 and Figure 4F , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figures 10C to 10H The second copper-containing metal interconnect structure 388 can be formed in the cavity 387 on the copper-based tunnel barrier layer 369.

[0186] Referring to all the accompanying drawings and various embodiments of the present disclosure, a semiconductor device structure is provided, comprising a first copper-containing metal interconnect structure 368 within a first dielectric material layer 350, a copper-based tunnel barrier layer 369 located on the surface of the first copper-containing metal interconnect structure 368, and a second copper-containing metal interconnect structure 388 embedded in a second dielectric material layer 370 covering the first dielectric material layer 350, wherein the second copper-containing metal interconnect structure 388 is in direct contact with the copper-based tunnel barrier layer 369.

[0187] In one embodiment, the copper-based tunnel barrier layer 369 has a thickness ranging from 0.5 nm to 2.0 nm. In one embodiment, the copper-based tunnel barrier layer 369 contacts the sidewall of the first copper-containing metal interconnect structure 368. In one embodiment, a first portion of the copper-based tunnel barrier layer 369 inserted between the first copper-containing metal interconnect structure 368 and the second copper-containing metal interconnect structure 388 has a smaller thickness than a second portion of the copper-based tunnel barrier layer 369 that contacts the first copper-containing metal interconnect structure 368 but does not contact the second copper-containing metal interconnect structure 388. In one embodiment, the semiconductor device structure includes an additional copper-based tunnel barrier layer 369 that contacts the top surface and sidewall of the first copper-containing metal interconnect structure 368. In one embodiment, the copper-based tunnel barrier layer 369 comprises a heterogeneous copper oxynitride material, such that a nitrogen concentration gradient and an oxygen concentration gradient exist within the copper-based tunnel barrier layer 369.

[0188] Generally, copper atoms within copper-containing metal interconnect structures can diffuse along grain boundaries, especially under elevated temperature and compressive stress conditions. This diffusion is driven by stress gradients, causing copper atoms to migrate to regions of lower stress, typically accumulating around the grain boundaries. Over time, this accumulation can lead to the formation of protrusions called hillocks on the surface of the copper interconnect structure. Hillocks are particularly problematic because they can cause physical damage within the interconnect layer, resulting in semiconductor device failure.

[0189] In the presence of hydrogen or nitrogen radicals, which may be introduced during various process steps such as plasma treatment, these radicals can further influence the diffusion process. Hydrogen radicals can penetrate grain boundaries, interact with copper atoms, and potentially promote their migration by weakening atomic bonds within the copper structure. Similarly, nitrogen radicals or trapped nitrogen atoms can enhance or hinder diffusion, depending on their interaction with copper atoms and the resulting changes in the local stress environment. These radicals may also become trapped within grain boundaries, altering the microstructure and potentially affecting hillock formation and growth. Therefore, the presence of these radicals or trapped atoms can play a role in the reliability and stability of copper interconnect structures, particularly under conditions that promote hillock formation.

[0190] The embodiments disclosed herein suppress the diffusion of copper atoms along grain boundaries and the subsequent formation of hillocks under compressive stress and elevated temperatures. This approach mitigates the diffusion of copper atoms to the surface by incorporating a copper-based tunnel barrier layer 369 into the device structure, thereby reducing the risk of hillock formation. This tunnel barrier layer, which may be composed of copper oxide, copper nitride, or copper oxynitride, is strategically formed on the surface of the first copper-containing metal interconnect structure 368, thereby creating a solid barrier that impedes the migration of copper atoms along grain boundaries.

[0191] The copper-based tunneling barrier layer 369 can be achieved by exposing a portion of the surface of the first copper-containing metal interconnect structure 368 to an environment including an oxidizing gas or a nitriding gas at a controlled temperature. This process forms a thin, uniform layer that is both conductive and resistant to atomic migration. The barrier layer serves a dual purpose: it allows electron tunneling between the first and second copper-containing metal interconnect structures (first copper-containing metal interconnect structure 368, second copper-containing metal interconnect structure 388) while simultaneously acting as a buffer to absorb and redistribute stress. This prevents stress concentration at the copper-dielectric interface, a major factor in hillock formation. Furthermore, by controlling the thickness of the copper-based tunneling barrier layer 369 (typically in the range of 0.5 nm to 2.0 nm), this method ensures that the layer effectively blocks copper diffusion without compromising the electrical connectivity required for device function.

[0192] According to one aspect of this disclosure, tunnel barrier layers can be formed through various processes, including thermal oxidation, thermal nitriding, plasma oxidation, and plasma nitriding. The choice of processes and materials can be customized to optimize barrier performance under specific operating conditions. For example, plasma treatment may introduce hydrogen or nitrogen radicals that are trapped within grain boundaries, thereby further stabilizing the copper structure and preventing unwanted diffusion. This increased stability is particularly advantageous in high-temperature environments where conventional copper interconnects might otherwise fail due to hillock formation and delamination.

[0193] By integrating a copper-based tunnel barrier layer 369 into the interconnect structure, embodiments of this disclosure provide a reliable solution to reliability issues caused by stress in copper interconnects. The barrier layer not only reduces the likelihood of hillock formation by inhibiting copper atom migration but also enhances the overall durability and lifespan of the device structure. The structures and methods of this disclosure support the continued use of copper in advanced semiconductor devices, particularly as designs become more complex and densely packaged, by ensuring interconnects remain reliable even under challenging thermal and mechanical conditions.

[0194] This disclosure provides a method for forming a semiconductor device structure, the method comprising the following operations: forming a first copper-containing metal interconnect structure within a first dielectric material layer; forming a second dielectric material layer above the first copper-containing metal interconnect structure and the first dielectric material layer; forming a cavity through the second dielectric material layer such that a surface segment of the first copper-containing metal interconnect structure is exposed beneath the cavity; transforming the surface portion of the first copper-containing metal interconnect structure into a copper-based tunnel barrier layer; and forming a second copper-containing metal interconnect structure within the cavity on the copper-based tunnel barrier layer.

[0195] In some embodiments, the copper-based tunnel barrier layer comprises a dielectric material selected from copper oxide, copper nitride, or copper oxynitride.

[0196] In some embodiments, the copper-based tunnel barrier layer is formed by exposing the surface portion of the first copper-containing metal interconnect structure to an environment, which includes an oxidizing gas or a nitriding gas in a temperature range of 10 degrees Celsius to 450 degrees Celsius.

[0197] In some embodiments, the environment includes at least one of ammonia, oxygen, ozone, nitrous oxide, nitric oxide, and nitrogen dioxide.

[0198] In some implementations, the copper-based tunnel barrier layer is formed by performing at least one of a thermal oxidation process and a thermal nitriding process.

[0199] In some embodiments, the copper-based tunnel barrier layer is formed by performing at least one of a plasma oxidation process and a plasma nitriding process.

[0200] In some embodiments, the copper-based tunnel barrier layer is formed by a combination of oxidation and nitriding processes, resulting in nitrogen and oxygen concentration gradients existing within the copper-based tunnel barrier layer.

[0201] In some embodiments, the method further includes, during the formation of the cavity, vertically recessing a portion of the top surface of the first copper-containing metal interconnect structure, wherein a plurality of solid exposed surfaces of the first copper-containing metal interconnect structure include recessed surface segments of the first copper-containing metal interconnect structure and at least one sidewall surface segment of the first copper-containing metal interconnect structure, and wherein the periphery of the recessed surface segment coincides with the bottom periphery of the at least one sidewall surface segment.

[0202] This disclosure provides a method for forming a semiconductor device structure, the method comprising the following operations: forming a first copper-containing metal interconnect structure over a first dielectric material layer; transforming a surface portion of the first copper-containing metal interconnect structure into a copper-based tunnel barrier layer; forming at least one additional dielectric material layer over the first dielectric material layer and the copper-based tunnel barrier layer; forming a cavity through the at least one additional dielectric material layer, such that a surface segment of the first copper-containing metal interconnect structure or the copper-based tunnel barrier layer is exposed beneath the cavity; and forming a second copper-containing metal interconnect structure within the cavity on the copper-based tunnel barrier layer.

[0203] In some embodiments, the copper-based tunnel barrier layer is formed by performing at least one of a surface oxidation process and a surface nitriding process.

[0204] In some implementations, the method also includes removing a portion of the copper-based tunnel barrier layer from beneath the cavity.

[0205] In some embodiments, a copper-based tunnel barrier layer is formed on the top surface and at least one sidewall of the first copper-containing metal interconnect structure.

[0206] In some embodiments, during cavity formation, a horizontal extension of the copper-based tunneling barrier layer is inserted between the first copper-containing metal interconnect structure and the cavity. A second copper-containing metal interconnect structure is formed on the horizontal extension of the copper-based tunneling barrier layer.

[0207] In some embodiments, the method further includes transforming the proximal portion of the first copper-containing metal interconnect structure located beneath the cavity into an additional copper-based tunneling barrier layer, wherein the second copper-containing metal interconnect structure is formed on the additional copper-based tunneling barrier layer.

[0208] In some embodiments, a semiconductor device structure includes a first copper-containing metal interconnect structure, a copper-based tunnel barrier layer, an additional copper-based tunnel barrier layer, and a second copper-containing metal interconnect structure. The copper-based tunnel barrier layer is located on the surface of the first copper-containing metal interconnect structure. The additional copper-based tunnel barrier layer is in contact with the top surface and sidewalls of the first copper-containing metal interconnect structure. The second copper-containing metal interconnect structure is in direct contact with the copper-based tunnel barrier layer.

[0209] In some implementations, the additional copper-based tunneling barrier layer has a thickness ranging from 0.5 nm to 2.0 nm.

[0210] In some embodiments, a semiconductor device structure includes a first copper-containing metal interconnect structure, a copper-based tunnel barrier layer, and a second copper-containing metal interconnect structure. The first copper-containing metal interconnect structure is located within a first dielectric material layer. The copper-based tunnel barrier layer is situated on the surface of the first copper-containing metal interconnect structure. The second copper-containing metal interconnect structure is in direct contact with the copper-based tunnel barrier layer, wherein the second copper-containing metal interconnect structure is perpendicularly spaced from the first copper-containing metal interconnect structure through the copper-based tunnel barrier layer.

[0211] In some implementations, the copper-based tunneling barrier layer has a thickness ranging from 0.5 nm to 2.0 nm.

[0212] In some embodiments, the copper-based tunnel barrier layer inserted between the first copper-containing metal interconnect structure and the second copper-containing metal interconnect structure has a first portion, and the copper-based tunnel barrier layer that contacts the first copper-containing metal interconnect structure but does not contact the second copper-containing metal interconnect structure has a second portion, and the first portion has a smaller thickness than the second portion.

[0213] In some embodiments, the semiconductor device structure further includes an additional copper-based tunnel barrier layer in contact with the top surface and sidewalls of the first copper-containing metal interconnect structure.

[0214] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Each embodiment described using the term "comprising" also inherently discloses that in some embodiments the term "comprising" may be replaced by "substantially consisting of" or "consisting of," unless otherwise explicitly disclosed herein. Whenever two or more elements are listed as alternatives in the same or different paragraphs, a list comprising two or more elements may also be implicitly disclosed. Whenever the auxiliary verb "may" is used in this disclosure to describe the formation of an element or the execution of a process step, embodiments in which such an element or process step is not performed are also explicitly considered, provided that the resulting apparatus or device can provide equivalent results. Strictly speaking, whenever omitting the formation of such an element or such process step can provide the same or equivalent results, the auxiliary verb "may" applied to the formation of an element or the execution of a process step should also be interpreted as "possible" or "possible or impossible," with equivalent results including slightly better and slightly worse results. Those skilled in the art will understand that this disclosure can be easily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, characterized in that, include: A first copper-containing metal interconnect structure is contained within a first dielectric material layer; A copper-based tunneling barrier layer is located on one surface of the first copper-containing metal interconnect structure; and A second copper-containing metal interconnect structure is embedded in a second dielectric material layer covering the first dielectric material layer, wherein the second copper-containing metal interconnect structure is in direct contact with the copper-based tunnel barrier layer.

2. The semiconductor device structure as described in claim 1, characterized in that, The copper-based tunnel barrier layer has a thickness ranging from 0.5 nm to 2.0 nm.

3. The semiconductor device structure as described in claim 1 or 2, characterized in that, The copper-based tunnel barrier layer contacts multiple sidewalls of the first copper-containing metal interconnect structure.

4. The semiconductor device structure as described in claim 1 or 2, characterized in that, The copper-based tunnel barrier layer inserted between the first copper-containing metal interconnect structure and the second copper-containing metal interconnect structure has a first portion, and the copper-based tunnel barrier layer that contacts the first copper-containing metal interconnect structure but does not contact the second copper-containing metal interconnect structure has a second portion. Compared with the second portion, the first portion has a smaller thickness.

5. A semiconductor device structure, characterized in that, include: A first copper-containing metal interconnect structure; A copper-based tunnel barrier layer is located on a surface of the first copper-containing metal interconnect structure; An additional copper-based tunnel barrier layer contacts a top surface and a sidewall of the first copper-containing metal interconnect structure; and A second copper-containing metal interconnect structure is in direct contact with the copper-based tunnel barrier layer.

6. The semiconductor device structure as described in claim 5, characterized in that, The additional copper-based tunnel barrier layer has a thickness ranging from 0.5 nm to 2.0 nm.

7. A semiconductor device structure, characterized in that, include: A first copper-containing metal interconnect structure is contained within a dielectric material layer; A copper-based tunneling barrier layer is located on one surface of the first copper-containing metal interconnect structure; and A second copper-containing metal interconnect structure is in direct contact with the copper-based tunnel barrier layer, wherein the second copper-containing metal interconnect structure is perpendicularly spaced from the first copper-containing metal interconnect structure through the copper-based tunnel barrier layer.

8. The semiconductor device structure as described in claim 7, characterized in that, The copper-based tunnel barrier layer has a thickness ranging from 0.5 nm to 2.0 nm.

9. The semiconductor device structure as described in claim 7 or 8, characterized in that, The copper-based tunnel barrier layer inserted between the first copper-containing metal interconnect structure and the second copper-containing metal interconnect structure has a first portion, and the copper-based tunnel barrier layer that contacts the first copper-containing metal interconnect structure but does not contact the second copper-containing metal interconnect structure has a second portion. Compared with the second portion, the first portion has a smaller thickness.

10. The semiconductor device structure as described in claim 7 or 8, characterized in that, It also includes an additional copper-based tunnel barrier layer that contacts a top surface and a sidewall of the first copper-containing metal interconnect structure.

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