A scribe lane structure for a silicon carbide wafer

Abstract

The utility model relates to the technical field of semiconductor processing especially is a kind of scribe lane structure of silicon carbide wafer, including: the wafer with identification part and the multiple chip units shaped on the wafer by multiple scribe lane separation;The chip unit includes device layer and packaging layer, and the scribe lane of device layer close to the identification part is provided with widening structure, in the utility model, the active region layer, metal layer, passivation layer below laser marking place are additionally widened 30 μm opening area by opening scribe lane, the width of scribe lane below laser marking place reaches 60 μm, completely satisfies the size requirement of laser scribing, completely solves the problem that the uppermost scribe lane cannot be normally cut open, effectively improves scribing success rate and product yield;Second, the original design is retained for the zero layer and P trap layer that scribe lane does not open, and the scribe lane width of other positions in wafer interior also remains unchanged.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor processing technology, and in particular to a dicing structure for silicon carbide wafers. Background Technology

[0002] In the manufacturing process of silicon carbide diodes, wafer dicing is a key step in dividing the wafer into individual chips. Due to the inherent high hardness and brittleness of silicon carbide material, laser dicing technology has become the mainstream choice. It has extremely strict process requirements on the dimensional accuracy of the dicing traces, and the compliance of the dicing trace dimensions directly determines the dicing quality and chip yield.

[0003] Currently, a common technical bottleneck exists in the layout design of silicon carbide diode wafers. To maximize wafer utilization while ensuring chip performance, the industry typically sets the scribe line width inside the wafer to 60μm, which meets the process window requirements of mainstream laser scribers. However, the situation becomes particularly complex below the laser marking area on the wafer; because the laser marking process itself requires a certain amount of physical space, the scribe line width directly below it is significantly compressed, typically reduced to 30μm, as detailed in the specification. Figure 1 As shown in the figure, I is the wafer, II is the marking area, and III is the dicing track near the marking area.

[0004] This 30μm width is far below the minimum effective width required for laser scribing. Therefore, when the laser scribing equipment processes this narrow area, the laser energy cannot form a complete and effective cutting path, causing the scribing tracks to fail to separate properly. This defect not only directly leads to wafer dicing failure in this area, but also significantly reduces product yield.

[0005] Therefore, overcoming this inherent defect in existing designs and developing a novel silicon carbide wafer dicing design has become a pressing technical challenge in this field. Utility Model Content

[0006] The purpose of this invention is to address the shortcomings of existing technologies, such as the inability to form a complete and effective cutting path with the width of the scribe line below the laser marking area, and to propose a scribe line structure for silicon carbide wafers.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: Design a dicing structure for a silicon carbide wafer, including: A wafer with a marking section and multiple chip units formed on the wafer by multiple dicing channels; The chip unit includes a device layer and a packaging layer, and the scribe line of the device layer near the marking portion is provided with a widening structure.

[0008] Furthermore, several of the chip units are distributed in a matrix, and adjacent chip units are separated by dicing channels.

[0009] Furthermore, the dicing channel forms an open layer and an unopened layer on the wafer, wherein the thickness of the open layer is adapted to the thickness of the encapsulation layer, and the thickness of the unopened layer is adapted to the thickness of the device layer.

[0010] Furthermore, the device layer includes a zero layer and a P-well layer; The P-well layer is formed above the zero layer.

[0011] Furthermore, the encapsulation layer includes a passivation layer, a metal layer, and an active region layer arranged sequentially from top to bottom; The passivation layer, metal layer, and open layer of the active region layer completely overlap in the vertical direction.

[0012] Furthermore, the widening structure is a widening portion disposed at the open layer, and the depth of the widening portion is the same as the depth of the open layer; The sum of the width of the open layer near the marking portion and the width of the widened portion is the same as the width of the open layer between two adjacent chip units.

[0013] Furthermore, the width of the slit track near the marking section is 30 μm, and the width of the widening structure is 30 μm.

[0014] The dicing channel structure for silicon carbide wafers proposed in this invention has the following advantages: By extending the active region layer, metal layer, and passivation layer of the dicing channel by an additional 30μm below the laser marking area, the width of the dicing channel below the laser marking area reaches 60μm, fully meeting the size requirements of laser dicing. This completely solves the problem of the uppermost dicing channel not being able to open properly, effectively improving the dicing success rate and product yield. Secondly, the original design is retained for the zero layer and P-well layer where the scribe line is not opened, and the scribe line width in other locations inside the wafer is also kept unchanged. This avoids the impact of design adjustments on the electrical performance, structural stability, and wafer utilization of silicon carbide diodes, ensuring that the product performance meets the standard requirements. Furthermore, this design only requires a simple widening operation on the existing dicing channel opening layer, without the need for significant modifications to the existing production process. It is easily compatible with existing production lines, reducing equipment modification costs and process adjustment difficulties for enterprises, and facilitating large-scale promotion and application. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the existing slicing track structure; Figure 2This is a schematic diagram of the structure of this utility model; Figure 3 This is a cross-sectional view of the present invention.

[0016] In the diagram: 1. Wafer; 10. Marking section; 2. Die traverse; 21. Open layer; 22. Unopened layer; 3. Chip unit; 31. Device layer; 311. Zero layer; 312. P-well layer; 32. Packaging layer; 321. Passivation layer; 322. Metal layer; 323. Active region layer; 4. Widening structure. Detailed Implementation

[0017] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.

[0018] Reference Figure 2-3 As an embodiment of the utility model, a dicing channel structure for a silicon carbide wafer is disclosed. Its purpose is to overcome the defect in the existing silicon carbide diode wafer dicing channel design that the dicing channel width below the laser marking area is insufficient, leading to dicing failure. It provides a silicon carbide dicing channel design that is designed differently for different layer structures, ensures that the width of the dicing channel below the laser marking area meets the standard, and does not affect the width of other dicing channels inside the wafer. Specifically, the dicing structure includes a wafer 1 with a marking portion 10 and a plurality of chip units 3 formed on the wafer 1 by a plurality of dicing channels 2. That is, in this embodiment, a plurality of the chip units 3 are distributed in a matrix, and adjacent chip units 3 are separated by dicing channels 2. The marking part 10 described in this utility model is used to laser mark the surface of the wafer 1 to form a corresponding mark. At the same time, multiple dicing channels 2 are formed on the surface of the wafer 1 along the longitudinal and transverse directions to form multiple chip units 3 on the top of the wafer 1. It should be noted that the dicing channels 2 described in this invention are blank areas reserved between chips during the manufacturing process of the wafer 1 through photolithography and etching processes. The chip unit 3 includes a device layer 31 and a packaging layer 32, and the dicing track 2 of the device layer 31 near the marking part 10 is provided with a widening structure 4.

[0019] In some embodiments, the dicing channel 2 of the present invention forms an open layer 21 and an unopened layer 22 on the wafer 1, wherein the thickness of the open layer 21 is adapted to the thickness of the encapsulation layer 32, and the thickness of the unopened layer 22 is adapted to the thickness of the device layer 31.

[0020] Specifically, in this embodiment, the open layer 21 is the cut portion during laser cutting, and the unopened layer 22 is the uncut portion on wafer 1 during laser cutting.

[0021] Furthermore, in this embodiment, the device layer 31 includes a zero layer 311 and a P-well layer 312; the P-well layer 312 is formed on top of the zero layer 311.

[0022] Furthermore, in this embodiment, the encapsulation layer 32 includes a passivation layer 321, a metal layer 322, and an active region layer 323 arranged sequentially from top to bottom; The passivation layer 321, the metal layer 322, and the open layer 21 of the active region layer 323 completely overlap in the vertical direction.

[0023] In an optional embodiment, the widening structure 4 is a widening portion disposed at the open layer 21, the depth of the widening portion being the same as the depth of the open layer 21; The sum of the width of the open layer 21 near the marking portion 10 and the width of the widened portion is the same as the width of the open layer 21 between two adjacent chip units 3.

[0024] Taking a 6-inch diameter silicon carbide diode wafer as an example, the processing methods for each layer are as follows: Treatment of unopened layer 22 in lane 2: In this embodiment, the zero layer 311 uses the original semiconductor substrate material, and the dicing 2 region maintains the same material structure as other regions of wafer 1, without any etching or removal operations, to ensure the insulation and support performance of this layer. The P-well layer 312 is formed by ion implantation to form the P-well region. No P-type impurity is implanted in the scribe line 2 region to maintain the original boundary between the P-well layer and the scribe line region and ensure the stability of the electrical properties of the P-well layer. Specifically, in this embodiment, the design of the unopened layer 22 of the scribe line 2 is retained in its original form. For the unopened zero layer 311 and P-well layer 312 of the scribe line 2 on the silicon carbide diode wafer, the original unopened design is completely retained. The original scribe line 2 design is maintained in the zero layer 311 without any additional processing or modification, ensuring that this layer can play its basic alignment role normally in subsequent processes. In the P-well layer 312, the original doping region range and structural design are also followed, without changing the positional relationship and electrical characteristics between the P-well layer 312 and other layers, avoiding adverse effects on the electrical performance of the diode due to the adjustment of the scribe line 2 design.

[0025] The open layer 21 of the slicing channel 2 is widened by the structure 4: For the active region layer, metal layer and passivation layer opened by the scribe line on the silicon carbide diode wafer, an additional 30μm opening area is added above the scribe line, based on the original scribe line opening area.

[0026] The active region layer 323 is etched using a dry etching process. Above the original 30μm wide open area of ​​the scribe line 2, etching is performed again to form an additional open area with a width of 30μm, so that the total width of the active region layer scribe line below the laser marking is 60μm. The width of the open area of ​​the active region layer scribe line in other locations inside the wafer is still 60μm, and the etching depth is consistent with the original process. After the metal layer 322 is prepared by sputtering, a 30μm wide metal layer is etched away above the original 30μm wide scribe line 2 opening area using photolithography and wet etching processes to form an additional opening area, ensuring that the scribe line width of the metal layer 322 below the laser marking area is 60μm; the opening area width of the scribe line of other metal layers inside the wafer remains 60μm. The passivation layer 321 is formed by chemical vapor deposition (the material is silicon nitride). Then, by plasma etching, an additional 30μm wide open area is etched above the original 30μm wide open area of ​​the scribe line 2, so that the width of the scribe line of the passivation layer below the laser marking area reaches 60μm. The width of the open area of ​​the scribe line of other passivation layers inside the wafer is 60μm.

[0027] In other words, in this utility model, the width of the slit track 2 near the marking part 10 is 30μm, the width of the widening structure 4 is 30μm, that is, the width of the widened open layer 21 is 60μm.

[0028] In summary, by extending the active region layer 323, metal layer 322, and passivation layer 321 of the scribe line 2 by an additional 30μm below the laser marking area, the width of the scribe line below the laser marking area reaches 60μm, fully meeting the size requirements of laser scribe. This completely solves the problem of the uppermost scribe line not being able to open properly, effectively improving the scribe success rate and product yield. Secondly, the original design is retained for the zero layer 311 and P-well layer 312, which are not opened in scribe line 2. The width of scribe line 2 in other positions inside wafer 1 is also kept unchanged. This avoids the impact of design adjustments on the electrical performance, structural stability and wafer utilization of silicon carbide diodes, and ensures that the product performance meets the standard requirements. Furthermore, this design only requires a simple widening operation on the existing dicing channel 2 opening layer 21, without the need for significant modifications to the existing production process. It is easily compatible with existing production lines, reducing the equipment modification costs and process adjustment difficulties for enterprises, and facilitating large-scale promotion and application.

[0029] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A dicing structure for a silicon carbide wafer, characterized in that, include: A wafer (1) having a marking section (10) and a plurality of chip units (3) formed on the wafer (1) by a plurality of dicing channels (2); The chip unit (3) includes a device layer (31) and a packaging layer (32), and the dicing channel (2) of the device layer (31) near the marking part (10) is provided with a widening structure (4).

2. The dicing structure of a silicon carbide wafer according to claim 1, characterized in that: The chip units (3) are arranged in a matrix, and adjacent chip units (3) are separated by dicing channels (2).

3. The dicing structure of a silicon carbide wafer according to claim 1, characterized in that: The dicing channel (2) forms an open layer (21) and an unopened layer (22) on the wafer (1), wherein the thickness of the open layer (21) is adapted to the thickness of the encapsulation layer (32), and the thickness of the unopened layer (22) is adapted to the thickness of the device layer (31).

4. The dicing structure of a silicon carbide wafer according to claim 3, characterized in that: The device layer (31) includes a zero layer (311) and a P-well layer (312). The P-well layer (312) is formed on top of the zero layer (311).

5. The dicing structure of a silicon carbide wafer according to claim 3, characterized in that: The encapsulation layer (32) includes a passivation layer (321), a metal layer (322), and an active region layer (323) arranged sequentially from top to bottom. The passivation layer (321), the metal layer (322), and the open layer (21) of the active region layer (323) completely overlap in the vertical direction.

6. The dicing structure of a silicon carbide wafer according to claim 3, characterized in that: The widening structure (4) is a widening portion disposed at the open layer (21), and the depth of the widening portion is the same as the depth of the open layer (21); The sum of the width of the open layer (21) near the marking part (10) and the width of the widened part is the same as the width of the open layer (21) between two adjacent chip units (3).

7. A dicing structure for a silicon carbide wafer according to any one of claims 1-6, characterized in that: The width of the slicing lane (2) near the marking section (10) is 30 μm, and the width of the widening structure (4) is 30 μm.

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