A package

Abstract

A package. The package includes: a plastic package; a first set of pins extending from a first side of the plastic package and a second set of pins extending from a second side of the plastic package; wherein the first set of pins includes a first plurality of individual pins and a first consolidated pin, and the second set of pins includes a second plurality of individual pins and a second consolidated pin; and wherein a width of the first consolidated pin and a width of the second consolidated pin are greater than a width of any individual pin of the first plurality of individual pins and the second plurality of individual pins.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing, and more specifically to a package with an improved pin layout. Background Technology

[0002] In the semiconductor manufacturing industry, packaging is a crucial step in ensuring chip functionality and reliable connection to external circuits. Currently, mainstream applications utilize Infineon's standard Q-DPAK package. In semiconductor packaging, the pins on the molded enclosure are used to electrically connect the chip inside the package to external circuitry (such as a printed circuit board). Pin layout design is one of the core elements of packaging. For example, for power semiconductor devices, the package typically includes power pins for transmitting high current and control pins for transmitting signals.

[0003] As electronic devices become increasingly complex, chips need to control more and more signals, which places higher demands on the number of control pins. At the same time, the trend towards device miniaturization requires continuously shrinking package sizes. Therefore, the number of pins and their functional allocation directly affect the electrical performance and physical size of the package. Utility Model Content

[0004] This invention provides a package with an improved pin layout, which can optimize the pin layout to balance current carrying capacity and signal control functions, while reducing package size.

[0005] For example, at least one embodiment of the present invention provides a package comprising: a molding compound; a first set of pins extending from a first side of the molding compound and a second set of pins extending from a second side of the molding compound; wherein the first set of pins includes a first plurality of individual pins and a first merged pin, and the second set of pins includes a second plurality of individual pins and a second merged pin; and wherein the width of the first merged pin and the width of the second merged pin are greater than the width of any one of the first plurality of individual pins and the second plurality of individual pins.

[0006] For example, in a package according to at least one embodiment of the present invention, a first merged pin is formed by merging a first number of individual pins, and a second merged pin is formed by merging a second number of individual pins.

[0007] For example, in a package according to at least one embodiment of the present invention, the width of the first merged pin is equal to the sum of the widths of the first number of individual pins and the width of the gaps between the first number of individual pins; and the width of the second merged pin is equal to the sum of the widths of the second number of individual pins and the width of the gaps between the second number of individual pins.

[0008] For example, in the package according to at least one embodiment of the present invention, the first merging pin and the second merging pin have an integrally formed bent structure.

[0009] For example, in the packaging according to at least one embodiment of the present invention, the first quantity is equal to the second quantity.

[0010] For example, in the package according to at least one embodiment of the present invention, the values ​​of the first quantity and the second quantity are 6.

[0011] For example, the package according to at least one embodiment of the present invention further includes: a semiconductor chip encapsulated in a plastic encapsulation; and wherein the semiconductor chip includes a power chip.

[0012] For example, in a package according to at least one embodiment of the present invention, the first merged pin and the second merged pin are power pins; and the first plurality of individual pins and the second plurality of individual pins are control pins.

[0013] For example, in a package according to at least one embodiment of the present invention, one of the first merging pin and the second merging pin is connected to the source of the power chip, and the other of the first merging pin and the second merging pin is connected to the drain of the power chip.

[0014] For example, in a package according to at least one embodiment of the present invention, a first plurality of individual pins and a second plurality of individual pins are connected to at least one of the gate of a power chip, a drive source, or a temperature sensor. Attached Figure Description

[0015] Figure 1 A schematic diagram of a package according to an exemplary embodiment of the present invention is shown;

[0016] Figure 2 A schematic diagram depicting the width of the merged pins according to an exemplary embodiment of the present invention is shown;

[0017] Figure 3 A 3D diagram of a package with an improved pin layout based on a Q-DPAK package according to an exemplary embodiment of the present invention is shown.

[0018] Figure 4 The diagram illustrates the interconnection of semiconductor chips within a package according to an exemplary embodiment of the present invention. Detailed Implementation

[0019] The following description, with reference to the accompanying drawings, is provided to facilitate a comprehensive understanding of various embodiments of the present invention as defined by the claims and their equivalents. This description includes various specific details to aid understanding but should be considered exemplary only. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the various embodiments described herein without departing from the scope and spirit of the present invention. Furthermore, for clarity and brevity, descriptions of well-known functions and structures may be omitted.

[0020] The terms and wording used in the following description and claims are not limited to their dictionary meanings, but are merely used by the inventors to enable a clear and consistent understanding of the present invention. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of the present invention is for illustrative purposes only and is not intended to limit the purpose of the invention as defined in the appended claims and their equivalents.

[0021] It should be understood that the singular forms of “one,” “an,” and “the” include plural references unless the context clearly indicates otherwise. Thus, for example, the reference to “component surface” includes one or more such surfaces.

[0022] The terms "comprising" or "may include" refer to the presence of corresponding disclosed functions, operations, or components that can be used in various embodiments of the present invention, rather than limiting the presence of one or more additional functions, operations, or features. Furthermore, the terms "comprising" or "having" can be interpreted as indicating certain characteristics, numbers, steps, operations, constituent elements, components, or combinations thereof, but should not be construed as excluding the possibility of the presence of one or more other characteristics, numbers, steps, operations, constituent elements, components, or combinations thereof.

[0023] In various embodiments of this invention, the term "or" includes any of the listed terms and all combinations thereof. For example, "A or B" may include A, may include B, or may include both A and B.

[0024] Unless otherwise defined, all terms used in this invention (including technical or scientific terms) have the same meaning as understood by those skilled in the art as described herein. Common terms as defined in dictionaries are to be interpreted as having a meaning consistent with their context in the relevant technical field and should not be interpreted ideally or overly formally, unless expressly so defined in this invention.

[0025] In the semiconductor packaging field, the pins of power devices (such as power amplifiers and power management chips) are typically divided into power pins for high-current transmission and control pins for signal control. As electronic devices become smaller and more multifunctional, package sizes continue to shrink, highlighting the growing contradiction between pin count and layout. In existing package designs, power pins and control pins are usually set up independently. In packages with separately placed power pins, the power pin area is more dispersed, and the gaps between pins with the same function are larger. While this is more versatile and flexible, it requires reconnecting these pins on the printed circuit board (PCB) via copper traces. This leads to the following problems: uneven current flow, insufficient overall package overcurrent capacity, and reduced heat dissipation from the package pins to the PCB.

[0026] This invention provides a package with an improved pin layout. The package according to an example embodiment of this invention has a unique packaging scheme and shape, which optimizes the pin layout while achieving the corresponding functions, providing better overcurrent capability and better heat dissipation, improving signal control functions (e.g., increasing the number of control pins), reducing package size to save costs, and better securing the product during use. The above-described beneficial effects according to this invention are merely examples, and the beneficial effects of this invention are not limited thereto. See below for reference. Figures 1-4 Describes the packaging according to an example embodiment of the present invention.

[0027] Figure 1 A schematic diagram of a package 100 according to an exemplary embodiment of the present invention is shown.

[0028] refer to Figure 1 A package 100 is provided, which may include a molding compound 110 and a first set of pins ( Figure 1 Pins P11, P12, P13, P14, P15 shown in the diagram) and the second group of pins ( Figure 1 Pins P21, P22, P23, P24, and P25 are shown in the figure. The molding compound 110 can be made of an insulating material (such as epoxy resin or silicone) through processes such as molding or transfer molding. Its main function is to encapsulate and protect the internal semiconductor chip (not shown), lead frame, and the connection lines between the chip and the pins (such as bonding wires) from external moisture, chemicals, and mechanical stress, and to provide electrical insulation.

[0029] According to an exemplary embodiment of the present invention, the molding compound 110 may include a first set of pins extending from a first side of the molding compound 110 and a second set of pins extending from a second side of the molding compound, wherein the first set of pins includes a first plurality of individual pins and a first merged pin, and the second set of pins includes a second plurality of individual pins and a second merged pin. For example, in Figure 1 In the illustrated embodiment, the first set of pins may extend from a first side (e.g., the left side) of the molding compound 110, and the first set of pins may include a first plurality of individual pins ( Figure 1 Pins P11, P12, P13, P14 shown in the diagram and the first merging pin ( Figure 1 Pin P15 is shown in the diagram. A second set of pins may extend from a second side (e.g., the right side) of the molding compound 110, and this second set of pins may include a second plurality of individual pins (…). Figure 1 Pins P21, P22, P23, P24 shown in the diagram) and the second merged pin ( Figure 1 (P25 shown in the diagram). According to an exemplary embodiment of the present invention, the first side and the second side may be opposite sides of the molding compound 110, for example in a dual in-line package (DIP) or a similar layout.

[0030] According to exemplary embodiments of the present invention, the first set of pins P11, P12, P13, P14, P15 and the second set of pins P21, P22, P23, P24, P25 extending from both sides of the molding compound 110 can be manufactured in various ways. For example, all pins in the first set of pins P11, P12, P13, P14, P15 and the second set of pins P21, P22, P23, P24, P25 can be partially embedded in and penetrate the molding compound 110. Specifically, each pin may include an inner end completely enclosed by the molding compound 110 (or "chip connection end"), an outer end exposed outside the molding compound (or "soldering end"), and a root transition region located between the two and intersecting with the sidewall of the molding compound. During manufacturing, a molding compound can be molded around the pin using a molding process to form a strong mechanical bond. It should be noted that the above-described method of manufacturing the first set of pins and the second set of pins extending from both sides of the molding compound 110 is merely an example, and the present invention is not limited thereto.

[0031] According to an exemplary embodiment of the present invention, the merged pins can be configured such that their width is greater than the width of a single pin. In embodiments of the present invention, the pin width is defined as along... Figure 1 The length shown is measured along the X-axis, while the length of the pin is defined along... Figure 1 The length measured along the Y-axis is shown. For example, as... Figure 1As shown, the width of the first merged pin P15 can be greater than the width of any one of the first plurality of individual pins P11, P12, P13, P14 and the second plurality of individual pins P21, P22, P23, P24. Similarly, the width of the second merged pin P25 can be greater than the width of any one of the first plurality of individual pins P11, P12, P13, P14 and the second plurality of individual pins P21, P22, P23, P24. For example, the width of an individual pin can be about 0.2 mm to 0.3 mm, while the width of the merged pin can be about 0.5 mm to 0.8 mm, but this is merely an example, and the present invention is not limited thereto. For example, according to an embodiment of the present invention, the first merged pin can be formed by merging a first number of individual pins, and the second merged pin can be formed by merging a second number of individual pins. For example, the width of the first merged pin can be equal to the sum of the width of the first number of individual pins and the width of the gap between the first number of individual pins, and the width of the second merged pin can be equal to the sum of the width of the second number of individual pins and the width of the gap between the second number of individual pins.

[0032] According to an exemplary embodiment of this utility model, the first merging pin P15 and the second merging pin P25 can have an integrated bent structure, for example, formed by integral bending, but this utility model is not limited thereto. Merging pins with an integrated bent structure can improve the mechanical strength, electrical conductivity, and heat dissipation performance of the package 100, while simplifying the manufacturing process and reducing costs.

[0033] exist Figure 1 In the illustrated embodiment, the first and second sets of pins are shown as each comprising a total of five pins (i.e., a first plurality of individual pins P11, P12, P13, P14 and a first combined pin P15 or a second plurality of individual pins P21, P22, P23, P24 and a second combined pin P25), but the invention is not limited thereto. Each set of pins in the package according to the present invention may include any number of pins. For example, the first and second sets of pins may each comprise a total of six pins, etc. Furthermore, in Figure 1 In the illustrated embodiment, the first plurality of individual pins and the second plurality of individual pins are shown as each comprising four individual pins, but the present invention is not limited thereto, and the first plurality of individual pins and the second plurality of individual pins may each comprise more or fewer individual pins.

[0034] According to an exemplary embodiment of this utility model, the larger width of the merged pins in package 100 increases the usable pin area, allowing for greater current capability within the same package size. Simultaneously, the internal merging of the pins increases the current voltage drop. Because the merged pins have higher current carrying capacity, more control pins can be reserved or the package size can be reduced for the same current capability requirements. Furthermore, the merged pins offer better heat dissipation and better product fixation during use.

[0035] For example, according to an exemplary embodiment of the present invention, the first and second merged pins of package 100 can be configured as power pins of a power chip, and the first plurality of individual pins and the second plurality of individual pins of package 100 can be configured as control pins of a power chip.

[0036] Figure 2 A schematic diagram depicting the width of the merged pins according to an exemplary embodiment of the present invention is shown.

[0037] According to an exemplary embodiment of the present invention, a merged pin can be formed by merging a certain number of individual pins. Figure 2 by Figure 1 Taking package 100 as an example, the width of the merged pin, formed by combining a certain number of individual pins, is depicted. For the sake of brevity, details related to... Figure 1 The embodiments shown are repeated descriptions of the same content.

[0038] According to an exemplary embodiment of the present invention, the first merged pin P15 of package 100 can be formed by merging a first number of individual pins, and the second merged pin P25 can be formed by merging a second number of individual pins. For example, in Figure 2 In the package 100 shown, individual pins are indicated by dashed boxes. Figure 2 As shown, the first combined pin P15 of package 100 can be formed by combining four individual pins, and the second pin P25 of package 100 can be formed by combining four individual pins. Figure 2 In the illustrated embodiment, the first merged pin P15 and the second merged pin P25 are formed by merging four individual pins; however, this is merely an embodiment. According to exemplary embodiments of the present invention, the first merged pin P15 and the second merged pin P25 can be formed by merging any number of individual pins. Furthermore, in Figure 2In the illustrated embodiment, the number of individual pins forming the first merged pin P15 is equal to the number of individual pins forming the second merged pin P25, i.e., the first number equals the second number. When the first number equals the second number, the first merged pin and the second merged pin can be formed using the same manufacturing process, thereby simplifying the manufacturing process and reducing costs. However, the present invention is not limited to this; the first number of individual pins forming the first merged pin P15 may not be equal to the second number of individual pins forming the second merged pin P25.

[0039] According to an exemplary embodiment of this utility model, the width of the first merged pin P15 can be equal to the sum of the widths of a first number of individual pins and the width of the gaps between the first number of individual pins, and the width of the second merged pin P25 can be equal to the sum of the widths of a second number of individual pins and the width of the gaps between the second number of individual pins. For example, the width of the first merged pin P15 can be equal to the sum of the widths of four individual pins and the width of the gaps between the four individual pins, and the width of the second merged pin P25 can be equal to the sum of the widths of four individual pins and the width of the gaps between the four individual pins, but this is merely an example.

[0040] The following is for reference. Figure 2 This describes the width of the merged pins according to an exemplary embodiment of the present invention.

[0041] refer to Figure 2 The dashed box represents a schematic of a single pin; that is, the first merged pin P15 is formed by combining four individual pins. The width of the first merged pin P15 can be L6, the width of each individual pin can be L4, and the width of the gap between the individual pins can be L5. For example... Figure 2 As shown, the width of the first merged pin P15 can be equal to the sum of the widths of the four individual pins and the width of the gap between the four individual pins, that is, L6 = 4L4 + 3L5.

[0042] Similarly, the second merged pin P25 is formed by merging four individual pins. The width of the second merged pin P25 can be L3, the width of each individual pin can be L1, and the width of the gap between the individual pins can be L2. For example... Figure 2 As shown, the width of the second merged pin P25 can be equal to the sum of the widths of the four individual pins and the width of the gap between the four individual pins, that is, L3 = 4L1 + 3L2.

[0043] According to an exemplary embodiment of the present invention, the width of the merged pin is equal to the sum of the widths of the individual pins and the width of the gaps between the individual pins. For example, in Figure 2In the illustrated embodiment, the width of the second merged pin P25 is equal to the sum of the widths of the four individual pins and the width of the gap between the four individual pins, i.e., greater than the width of the four individual pins. Therefore, the merged pin according to the exemplary embodiment of this invention increases the available pin area, thereby allowing for greater current capability within the same package size. For the same current capability requirements, more control pins can be reserved or the package size can be reduced, while also providing better heat dissipation and better product fixation during use.

[0044] In the semiconductor manufacturing field, the current mainstream application uses the Infineon-developed standard Q-DPAK package. In the Q-DPAK package, each side of the package has 11 individual pins. The package according to the exemplary embodiment of this utility model can be applied to the Q-DPAK package, as described below... Figure 3 Provide a detailed description.

[0045] Figure 3 A 3D diagram of a package 300 with an improved pin layout based on a Q-DPAK package according to an exemplary embodiment of the present invention is shown.

[0046] Figure 3 The illustrated package 300 may include a molding compound 310, a first set of pins extending from a first side (e.g., the left side) of the molding compound 310, and a second set of pins extending from a second side (e.g., the right side) of the molding compound 310. The first set of pins may include a first plurality of individual pins 320 and a first merged pin 330, and the second set of pins may include a second plurality of individual pins 340 and a second merged pin 350. Figure 3 As shown, the first plurality of individual pins 320 may include 5 individual pins, and the second plurality of individual pins 340 may include 5 individual pins, but the present invention is not limited thereto, and the first plurality of individual pins 320 and the second plurality of individual pins 340 may include more or fewer individual pins.

[0047] exist Figure 3 In the embodiment shown, the first merged pin 330 can be formed by merging 6 individual pins, and the second merged pin 350 can be formed by merging 6 individual pins. However, the present invention is not limited thereto, and the first merged pin 330 and the second merged pin 350 can be formed by merging more or fewer individual pins.

[0048] According to an exemplary embodiment of this utility model, the width of the first merged pin 330 is equal to the sum of the widths of the six individual pins and the width of the gaps between the six individual pins, and the width of the second merged pin 350 is equal to the sum of the widths of the six individual pins and the width of the gaps between the six individual pins. Because the first merged pin 330 and the second merged pin 350 increase the usable pin area, the current carrying capacity of the pins is increased.

[0049] According to an exemplary embodiment of the present invention, the first merged pin 330 and the second merged pin 350 can be configured as power pins of the power chip, and the first plurality of individual pins 320 and the second plurality of individual pins 340 can be configured as control pins of the power chip. Compared to the Q-DPAK package, which configures 7 individual pins on one side and all 11 individual pins on the other side as power pins and the remaining 4 pins as control pins in the same application scenario, the package 300 based on the Q-DPAK package with improved pin layout according to the exemplary embodiment of the present invention can reserve more control pins in the same package size, while having better heat dissipation capabilities and better securing the product during use.

[0050] Figure 4 The diagram illustrates the interconnection of semiconductor chips within a package according to an exemplary embodiment of the present invention.

[0051] According to exemplary embodiments of the present invention, semiconductor chips can be packaged in a package according to embodiments of the present invention to protect the semiconductor chips from damage by external moisture, chemicals, and mechanical stress, and to provide electrical insulation. Figure 4 The embodiments shown are illustrated using a power chip as an example, but this is merely an example. It should be understood that the package according to the example embodiments of this utility model can package various types of semiconductor chips.

[0052] Figure 4 A power chip 400 is shown. This power semiconductor chip may include a gate, a source, a drain, a driving source, and a temperature sensor. The source and drain may be referred to as power electrodes, and the gate, driving source, and temperature sensor may be referred to as control electrodes. Figure 4 The power semiconductor chip shown is merely an example, and the power chip packaged in the package according to the example embodiment of this utility model can have various structures. For example, power chip 400 may include more or fewer components.

[0053] The power chip 400 can be packaged in a package (e.g., package 100 or package 300) according to an example embodiment of the present invention.

[0054] According to an example embodiment of the present invention, the combined pins of the package (e.g., package 100 or package 300) can be power pins and connected to the power electrode of the power chip 400, while the individual pins of the package can be control pins and connected to the control electrode of the power chip 300.

[0055] like Figure 4 As shown, the source of the power chip 400 can be connected to one of the merged pins of the package according to an embodiment of the present invention, and the drain of the power chip 400 can be connected to another merged pin of the package according to an embodiment of the present invention. The gate, drive source, and temperature sensor of the power chip 400 can be connected to separate pins. However, the present invention is not limited thereto; for example, at least one of the gate, drive source, or temperature sensor of the power chip 400 can be connected to a separate pin.

[0056] For example, as Figure 3 Taking package 300 as an example, the first merged pin 330 of package 300 can be connected to the source of power chip 400, and the second merged pin 350 of package 300 can be connected to the drain of power chip 400. The first plurality of individual pins 320 and the second plurality of individual pins 340 of package 300 can be connected to at least one of the gate, drive source, or temperature sensor of power chip 400. For example, according to an exemplary embodiment of the present invention, at least one of the gate, drive source, or temperature sensor of power chip 400 can be connected to one or more individual pins of the first plurality of individual pins 320 and the second plurality of individual pins 340.

[0057] The combined pins of the exemplary embodiments of this utility model increase the available pin area and can have a greater current capability. Therefore, by using combined pins to carry the large current of the power terminals (e.g., drain and source) of the power chip, more control pins can be reserved or the package size can be reduced. At the same time, it can have better heat dissipation capabilities and can better fix the product during use.

[0058] According to such Figures 1-4 The described example embodiment of the present invention provides a package with an improved pin layout. The package according to the example embodiment of the present invention increases the pin area by merging multiple individual pins to form a merged pin, resulting in better pin overcurrent capability and better heat dissipation, improved signal control functionality (e.g., increasing the number of control pins), reduced package size for cost savings, and better product fixation during use.

[0059] Those skilled in the art will understand that the illustrative embodiments described above are not intended to be limiting. It should be understood that any two or more of the embodiments disclosed herein can be combined in any combination. Furthermore, other embodiments may be utilized and other changes may be made without departing from the spirit and scope of the subject matter presented herein. It will be readily understood that aspects of the invention, as generally described herein and shown in the accompanying drawings, can be arranged, substituted, combined, separated, and designed in various different configurations, all of which are contemplated herein.

[0060] The exemplary embodiments described herein are not intended to be limiting. The aspects of the invention, as generally described herein and shown in the accompanying drawings, can be arranged, substituted, combined, separated, and designed in a variety of different configurations, all of which are conceivable herein. Furthermore, unless the context otherwise requires, the features shown in each drawing can be used in combination with each other. Therefore, the accompanying drawings should be considered... Figure 1 These features are generally considered to be part of one or more overall embodiments, but it should be understood that not all of the illustrated features are necessary for each embodiment.

[0061] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any person skilled in the art can make various changes or substitutions within the technical scope disclosed in this utility model, and such changes or substitutions should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A package, characterized in that, The package includes: Plastic encapsulation; A first set of pins extending from a first side of the molding compound and a second set of pins extending from a second side of the molding compound; Wherein, the first group of pins includes a first plurality of individual pins and a first combined pin, and the second group of pins includes a second plurality of individual pins and a second combined pin; and Wherein, the width of the first merged pin and the width of the second merged pin are greater than the width of any one of the first plurality of individual pins and the second plurality of individual pins.

2. The packaging according to claim 1, characterized in that, The first merged pin is formed by merging a first number of individual pins, and The second merged pin is formed by merging a second number of individual pins.

3. The packaging according to claim 2, characterized in that, The width of the first merged pin is equal to the sum of the widths of the first number of individual pins and the width of the gaps between the first number of individual pins; and The width of the second merged pin is equal to the sum of the widths of the second number of individual pins and the width of the gaps between the second number of individual pins.

4. The packaging according to claim 1, characterized in that, The first merging pin and the second merging pin have an integrally formed bent structure.

5. The packaging according to claim 2, characterized in that, The first quantity is equal to the second quantity.

6. The packaging according to claim 5, characterized in that, The values ​​of the first quantity and the second quantity are 6.

7. The packaging according to claim 1, characterized in that, Also includes: A semiconductor chip encapsulated in the plastic package; and The semiconductor chip includes a power chip.

8. The packaging according to claim 1 or 7, characterized in that, The first merging pin and the second merging pin are power pins; and The first plurality of individual pins and the second plurality of individual pins are control pins.

9. The packaging according to claim 8, characterized in that, One of the first merging pin and the second merging pin is connected to the source of the power chip, and the other of the first merging pin and the second merging pin is connected to the drain of the power chip.

10. The packaging according to claim 8, characterized in that, The first plurality of individual pins and the second plurality of individual pins are connected to at least one of the power chip’s gate, drive source, or temperature sensor.

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