Package structure with interposer

Abstract

The utility model relates to a kind of packaging structures with interlayer.The packaging structure with interlayer includes: interlayer, including the upper surface and lower surface of opposite distribution along first direction;Insulating filling layer, covering on the side wall of interlayer, insulating filling layer includes flush with the front of upper surface and flush with the back of lower surface;Upper wiring layer, continuous distribution is on the upper surface of interlayer and the front of insulating filling layer, and upper wiring layer is electrically connected with interlayer;Chip, located on the side of upper wiring layer away from interlayer, and chip is electrically connected with upper wiring layer.The utility model makes the area of upper wiring layer increase, increases the possibility of more fan-out connecting pin under the condition of not changing wiring density, simultaneously reduces the possibility that interlayer occurs deformation or fragmentation, so that the manufacturing yield of packaging structure is further improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing technology, and in particular to a packaging structure with an intermediary layer. Background Technology

[0002] In today's high-end semiconductor packaging field, advanced packaging technologies based on glass substrates, silicon interposers, and glass interposers have become core solutions for key applications such as high-performance computing (HPC) and artificial intelligence (AI) chips. These technologies, through high-density interconnect technology and heterogeneous integration capabilities, effectively support the collaborative operation of multiple chipsets and high-bandwidth memory (HBM), meeting the ever-increasing demands of modern computing for bandwidth, energy efficiency, and integration scale.

[0003] In the widely adopted interposer-based packaging architecture, the manufacturing process typically includes: forming a high-density interconnect layer on one side of the silicon or glass material. This high-density interconnect layer includes fine-linewidth wiring and vertical interconnects via through-silicon vias (TSVs) or through-glass vias (TGVs), and is used to carry and connect multiple chiplets or HBM stack memory. On the other side of the interposer, a relatively low-density redistribution layer (RDL) is arranged. Its main function is to fan out signals from the upper chip and connect them to the lower packaging substrate. The redistribution layer covers the surface of the silicon or glass interposer, not only realizing signal fan-in and fan-out, but also providing interface conversion and I / O expansion functions. After the RDL is manufactured and the chip is mounted on the upper surface of the interposer, the entire silicon or glass interposer is diced to form individual packaging units, which are then assembled onto a conventional organic substrate to complete the system-in-package (SIP).

[0004] However, such technologies still face significant challenges: on the one hand, silicon interposers are expensive due to the complexity of wafer manufacturing and high process costs. At the same time, the circular geometry of silicon wafers limits the utilization rate of the wafer when packaging ultra-large chips, resulting in material waste. On the other hand, although glass interposers have better signal integrity and lower cost, their high brittleness and fragility pose significant challenges to handling, processing, and transportation during the manufacturing process, and also significantly affect the overall yield and reliability.

[0005] Therefore, how to enhance the mechanical strength of the interposer, reduce the risk of breakage, improve the manufacturing yield of the packaging structure, and at the same time improve and enhance the performance of the packaging structure are the technical problems that urgently need to be solved. Summary of the Invention

[0006] This invention provides a packaging structure with an intermediary layer, which enhances the mechanical strength of the intermediary layer, reduces the risk of breakage, improves the manufacturing yield of the packaging structure, and simultaneously improves and enhances the performance of the packaging structure.

[0007] According to some embodiments, this utility model provides a packaging structure with an intermediary layer, including: The intermediate layer includes an upper surface and a lower surface that are relatively distributed along a first direction; An insulating filler layer covers the sidewalls of the intermediate layer, the insulating filler layer including a front side flush with the upper surface and a back side flush with the lower surface; An upper wiring layer is continuously distributed on the upper surface of the intermediate layer and the front side of the insulating fill layer, and the upper wiring layer is electrically connected to the intermediate layer; The chip is located on the side of the upper wiring layer opposite to the interposer layer, and the chip is electrically connected to the upper wiring layer.

[0008] In some embodiments, it also includes: A lower wiring layer is continuously distributed on the lower surface of the intermediate layer and the back surface of the insulating filler layer, and the lower wiring layer is electrically connected to the intermediate layer.

[0009] In some embodiments, the interposer layer includes a via interconnect structure, with one end of the via interconnect structure electrically connected to the upper wiring layer and the other end electrically connected to the lower wiring layer.

[0010] In some embodiments, the interposer is a silicon interposer or a glass interposer.

[0011] In some embodiments, it also includes: The packaging substrate is located on the side of the interposer layer opposite to the upper wiring layer and is electrically connected to the interposer layer; The projected area of ​​the interposer layer on the surface of the encapsulation substrate is greater than the projected area of ​​the insulating filler layer on the surface of the encapsulation substrate.

[0012] In some embodiments, a plurality of the interposers are spaced apart along a second direction, and an insulating filler layer covers the sidewalls of each of the interposers and fills the gaps between adjacent interposers, wherein the second direction is parallel to the front side of the insulating filler layer.

[0013] In some embodiments, the upper wiring layer is distributed on the upper surface of the plurality of interposer layers and on the front side of the insulating filler layer.

[0014] In some embodiments, the insulating filler layer is distributed around the outer periphery of the intermediate layer; or... The insulating filler layer covers the opposite sidewalls of the intermediate layer along the second direction, which is parallel to the upper surface of the intermediate layer; or, The insulating filler layer covers only one sidewall of the intermediate layer along the second direction.

[0015] In some embodiments, the sidewalls of the upper wiring layer are flush with the sidewalls of the insulating fill layer.

[0016] In some embodiments, a plurality of chips are disposed on the side of the upper wiring layer away from the interposer layer, and the plurality of chips are electrically connected to the upper wiring layer, wherein the second direction is parallel to the front side of the insulating filler layer.

[0017] In some embodiments, it also includes: A molding layer is located on the surface of the upper wiring layer opposite to the interposer layer, and the molding layer encapsulates the chip. The material of the molding layer is the same as that of the insulating filler layer.

[0018] In some embodiments, it also includes: The components are located on the side of the upper wiring layer away from the interposer layer. The components are electrically connected to the upper wiring layer, and the components and the chip are arranged at intervals along a direction parallel to the upper surface of the interposer layer.

[0019] In some embodiments, the component is a passive device or a power device.

[0020] In some embodiments, the component is located above the insulating filler layer.

[0021] In some embodiments, the upper wiring layer includes a high-density region above the interposer layer and a low-density region above the insulating filler layer, wherein the wiring density in the high-density region is greater than the wiring density in the low-density region. The chip is electrically connected to the high-density region, and the component is electrically connected to the low-density region.

[0022] The present invention provides a packaging structure with an interposer layer. By covering the sidewalls of the interposer layer with an insulating filler layer, and ensuring that the front side of the insulating filler layer is flush with the upper surface of the interposer layer and the back side of the insulating filler layer is flush with the lower surface of the interposer layer, and that an upper wiring layer is continuously distributed on the upper surface of the interposer layer and the front side of the insulating filler layer, the area of ​​the upper wiring layer is increased. This increases the possibility of fanning out more connection pins without changing the wiring density. Simultaneously, by covering the upper surface of the interposer layer with the upper wiring layer and the sidewalls of the interposer layer with the insulating filler layer, the protection of the interposer layer is more comprehensive, reducing the possibility of deformation or breakage, and further improving the manufacturing yield of the packaging structure. Furthermore, by covering the sidewalls of the interposer layer with the insulating filler layer, the insulating filler layer can act as a buffer medium to disperse stress in the interposer layer, allowing the thinner interposer layer to withstand greater warpage without causing overall breakage.

[0023] This invention achieves a consistent thickness between the insulating filler layer and the insulating filler layer by aligning the front surface of the insulating filler layer with the upper surface of the interposer layer and the back surface of the insulating filler layer with the lower surface of the interposer layer. This makes it easier to achieve thinner package sizes, further reducing the package structure size. On the other hand, it simplifies the manufacturing process of the upper wiring layer, highlighting the advantages of the package structure with the interposer layer in terms of planarity and overall integration. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0025] Figure 1 This is a cross-sectional schematic diagram of the packaging structure with an intermediate layer in a specific embodiment of this utility model; Figure 2 This is a top view schematic diagram showing the relative positional relationship between the intermediate layer and the insulating filler layer in a specific embodiment of this utility model; Figure 3 This is another top view schematic diagram showing the relative positional relationship between the intermediate layer and the insulating filler layer in a specific embodiment of this utility model; Figure 4 This is another top view schematic diagram showing the relative positional relationship between the intermediate layer and the insulating filler layer in a specific embodiment of this utility model; Figure 5This is another cross-sectional schematic diagram of the packaging structure with an intermediary layer in a specific embodiment of this utility model; Figure 6 This is another cross-sectional schematic diagram of the encapsulation structure with an intermediate layer in a specific embodiment of this utility model.

[0026] Explanation of reference numerals in the attached figures 10 Intermediary Layers 11 Insulation Filler Layer 12 Upper wiring layer 13 Upper layer wiring 14-hole interconnect structure 15 Lower Wiring Layer 16 Lower layer wiring 17 chips 18 weld layers 19 sealing layers 20 adhesive layers 50 components Detailed Implementation The specific embodiments of the encapsulation structure with an intermediary layer provided by this utility model will be described in detail below with reference to the accompanying drawings.

[0027] This specific embodiment provides a packaging structure with an intermediary layer. Figure 1 This is a cross-sectional schematic diagram of a packaging structure with an intermediary layer in a specific embodiment of this utility model. For example... Figure 1 As shown, the encapsulation structure with an intermediary layer includes: Intermediate layer 10 includes an upper surface and a lower surface that are relatively distributed along the first direction D1; An insulating filler layer 11 covers the sidewall of the intermediate layer 10, the insulating filler layer 11 including a front side flush with the upper surface and a back side flush with the lower surface; The upper wiring layer 12 is continuously distributed on the upper surface of the intermediate layer 10 and the front surface of the insulating fill layer 11, and the upper wiring layer 12 is electrically connected to the intermediate layer 10. Chip 17 is located on the side of the upper wiring layer 12 away from the interposer layer 10, and chip 17 is electrically connected to the upper wiring layer 12.

[0028] Specifically, the package structure with an interposer layer includes a package substrate (not shown in the figure), an interposer layer 10 mounted on the package substrate, an upper wiring layer 12 located on the upper surface of the interposer layer 10, and a package body mounted on the upper wiring layer 12. The interposer layer 10 includes an upper surface and a lower surface that are distributed opposite to each other along the first direction D1, with the upper surface of the interposer layer 10 facing the upper wiring layer 12 and the lower surface of the interposer layer 10 facing the package substrate. The interposer layer 10 electrically connects the upper wiring layer 12 and the package substrate, and the upper wiring layer 12 electrically connects the package body, thereby enabling the transmission of electrical signals between the package body, the upper wiring layer 12, the interposer layer 10, and the package substrate. The interposer layer 10 also includes a sidewall located between the upper surface and the lower surface, and an insulating filler layer 11 covers the sidewall of the interposer layer 10. In one example, the insulating filler layer 11 directly covers the sidewall of the intermediate layer 10, meaning the insulating filler layer 11 is in direct contact with the sidewall of the intermediate layer 10. The insulating filler layer 11 is an insulating material layer, thereby avoiding any impact on the transmission of electrical signals within the intermediate layer 10 or between the intermediate layer 10 and the upper wiring layer 12, and reducing the impact of parasitic capacitance effects.

[0029] The upper wiring layer 12 is continuously distributed on the upper surface of the interposer layer 10 and the front surface of the insulating filler layer 11, that is, the coverage area of ​​the upper wiring layer 12 extends from the upper surface of the interposer layer 10 to the front surface of the insulating filler layer 11. The upper wiring layer 12 has multiple high-density upper layer traces 13. The package includes a chip 17 mounted on the surface of the upper wiring layer 12 facing away from the interposer layer 10, and the chip 17 is electrically connected to the upper wiring layer 12. In one example, the chip 17 includes a functional surface and a bottom surface opposite to the functional surface. The functional surface of the chip 17 has multiple conductive bumps, and the surface of the upper wiring layer 12 facing away from the interposer layer 10 has multiple metal pads. The conductive bumps on the chip 17 and the metal pads on the upper wiring layer 12 are soldered together through a solder layer 18, that is, the chip 17 is flip-chip mounted on the upper wiring layer 12. In one example, the package further includes an adhesive layer 20 that fills the space between the chip 17 and the upper wiring layer 12 and covers the sides of the chip 17 to enhance the connection strength between the chip 17 and the upper wiring layer 12. The adhesive layer 20 may be an underfill adhesive.

[0030] This specific embodiment covers the insulating filler layer 11 on the sidewalls of the interposer layer 10, and the upper wiring layer 12 continuously covers the upper surface of the interposer layer 10 and the front surface of the insulating filler layer 11. This expands the area covered by the upper wiring layer 12, increasing the area of ​​the upper wiring layer 12 and thus increasing the area available for rewiring. This increases the possibility of fanning out more connection pins without changing the wiring density. Simultaneously, by covering the sidewalls of the interposer layer 10 with the insulating filler layer 11, the insulating filler layer 11 acts as a buffer medium to disperse stress in the interposer layer 10, thereby enhancing the mechanical strength of the interposer layer 10. Consequently, even if the interposer layer 10 is made of a thin and brittle material, it can withstand greater warping without breaking completely. Furthermore, by having the upper wiring layer 12 continuously cover the upper surface of the interposer layer 10 and the front surface of the insulating filler layer 11, the upper wiring layer 12 and the insulating filler layer 11 not only better encapsulate the interposer layer 10 through their synergistic effect, but also enhance the connection strength between the insulating filler layer 11 and the interposer layer 10. This provides more adequate protection for the interposer layer 10, reduces the possibility of deformation or breakage of the interposer layer 10, and further improves the manufacturing yield of the packaging structure.

[0031] Unlike traditional embedded silicon bridge interconnects or packaging structures using embedded silicon blocks or local interconnects, this specific embodiment makes the front side of the insulating filler layer 11 flush with the upper surface of the interposer layer 10, and the back side of the insulating filler layer 11 flush with the lower surface of the interposer layer 10. This makes the thickness of the interposer layer 10 the same as the thickness of the insulating filler layer 11. On the one hand, it is easier to achieve a thinner package size, thereby further reducing the package structure size. On the other hand, it simplifies the manufacturing process of the upper wiring layer, highlighting the advantages of the package structure with the interposer layer in terms of planarization and overall integration.

[0032] In some embodiments, the encapsulation structure having an intermediary layer further includes: The lower wiring layer 15 is continuously distributed on the lower surface of the intermediate layer 10 and the back surface of the insulating filler layer 11, and the lower wiring layer 15 is electrically connected to the intermediate layer 10.

[0033] Specifically, the encapsulation structure with an interposer layer further includes a lower wiring layer 15 continuously covering the lower surface of the interposer layer 10 and the back surface of the insulating filler layer 11. By having the upper wiring layer 12 and the lower wiring layer 15 jointly encapsulate the interposer layer 10 and the insulating filler layer 11, on the one hand, the clamping effect of the upper wiring layer 12 and the lower wiring layer 15 can better protect the intermediate interposer layer 10, further reducing the possibility of deformation or breakage of the interposer layer 10, thereby further improving the manufacturing yield of the encapsulation structure; on the other hand, by providing redistribution layers (i.e., the upper wiring layer 12 and the lower wiring layer 15) on opposite sides of the interposer layer 10 (i.e., the upper surface and the lower surface), the redistribution layers can be flexibly fan-out or not in the interposer layer 10 according to the product design needs of the encapsulation structure. If fan-out is implemented, it helps increase the number of I / O ports; if not, it further reduces the risk of delamination between the redistribution layer and the interposer layer 10.

[0034] In some embodiments, the interposer layer 10 includes a via interconnect structure 14, one end of which is electrically connected to the upper wiring layer 12 and the other end is electrically connected to the lower wiring layer 15.

[0035] In some embodiments, the interposer 10 is a silicon interposer or a glass interposer.

[0036] Specifically, the interposer layer 10 includes a body portion and a via interconnect structure 14 extending through the body portion along the first direction D1. In one example, the material of the body portion in the interposer layer 10 may be silicon or glass. The lower wiring layer 15 has a plurality of lower layer traces 16 arranged in a high density. One end of the via interconnect structure 14 is electrically connected to the upper layer trace 13 in the upper wiring layer 12, and the other end is electrically connected to the lower layer trace 16 in the lower wiring layer 15, thereby realizing the electrical connection between the lower wiring layer 15, the interposer layer 10, and the upper wiring layer 12. In one example, the material of the via interconnect structure 14 is a conductive metal material, such as copper.

[0037] In some embodiments, the encapsulation structure having an intermediary layer further includes: The packaging substrate is located on the side of the interposer layer 10 opposite to the upper wiring layer 12 and is electrically connected to the interposer layer 10; The projected area of ​​the intermediate layer 10 on the surface of the encapsulation substrate is greater than the projected area of ​​the insulating filler layer 11 on the surface of the encapsulation substrate.

[0038] Specifically, the packaging substrate includes a first main surface facing the interposer layer 10 and a second main surface opposite to the first main surface. The lower wiring layer 15 is located between the interposer layer 10 and the packaging substrate. The packaging substrate can be electrically connected to the lower wiring layer 15 via C4 (Controlled Collapse Chip Connection) technology or copper pillars. The projected area of ​​the interposer layer 10 on the first main surface of the packaging substrate is larger than the projected area of ​​the insulating filler layer 11 on the first main surface of the packaging substrate, such that the interposer layer 10 occupies a dominant area in the region between the upper wiring layer 12 and the lower wiring layer 15. For example, the projected area of ​​the interposer layer 10 on the first main surface of the packaging substrate accounts for more than 60% of the area of ​​the first main surface of the package. Unlike traditional embedded 2.5D packaging architectures (where the interposer layer occupies a small proportion), in this specific embodiment, the interposer layer 10 occupies most of the area between the upper wiring layer 12 and the lower wiring layer 15, thereby enabling sufficient wiring in the interposer layer 10 (i.e., increasing the area in the interposer layer 10 used for wiring) to ensure the electrical connection performance between the upper wiring layer 12 and the lower wiring layer 15.

[0039] Figure 5 This is another cross-sectional schematic diagram of the encapsulation structure with an intermediary layer in a specific embodiment of the present invention. In other embodiments, a plurality of the intermediary layers 10 are arranged at intervals along a second direction D2, and the insulating filler layer 11 covers the sidewall of each of the intermediary layers 10 and fills the gap between adjacent intermediary layers 10, wherein the second direction D2 is parallel to the front side of the insulating filler layer 11.

[0040] In some embodiments, the upper wiring layer 12 is distributed on the upper surface of the plurality of interposer layers 10 and on the front side of the insulating filler layer 11.

[0041] Specifically, such as Figure 5As shown, the encapsulation structure with interposers includes a lower wiring layer 15, an upper wiring layer 12 located above the lower wiring layer 15 along the first direction D1, and a plurality of interposers 10 and an insulating filler layer 11 sandwiched between the upper wiring layer 12 and the lower wiring layer 15. The plurality of interposers 10 are arranged at intervals along the second direction D2, and the insulating filler layer 11 covers the sidewall of each interposer 10 and fills the gap between adjacent interposers 10. Because an upper wiring layer 12 continuously covers the interposer layer 10 and the insulating filler layer 11 above the interposer layer 10, and a lower wiring layer 15 continuously covers the interposer layer 10 and the insulating filler layer 11 below the interposer layer 10, and the insulating filler layer 11 covers the sidewalls of the interposer layer 10, multiple interposer layers 10 can be arranged between the upper wiring layer 12 and the lower wiring layer 15, thus achieving the encapsulation of multiple interposer layers 10. By having the upper wiring layer 12, the lower wiring layer 15, and the insulating filler layer 11 jointly encapsulate multiple interposer layers 10, the integration of the packaging structure is further improved, giving the packaging structure with interposer layers superior scalability and application breadth. In this specific embodiment, "multiple" refers to two or more.

[0042] Figure 2 This is a top view schematic diagram showing the relative positional relationship between the intermediate layer and the insulating filler layer in a specific embodiment of this utility model. Figure 3 This is another top view schematic diagram showing the relative positional relationship between the intermediate layer and the insulating filler layer in a specific embodiment of this utility model. Figure 4 This is another top view schematic diagram showing the relative positional relationship between the intermediate layer and the insulating filler layer in a specific embodiment of this utility model. In some embodiments, the insulating filler layer 11 is distributed around the outer periphery of the intermediate layer 10; or, The insulating filler layer 11 covers the opposite sidewalls of the intermediate layer 10 along the second direction D2, the second direction D2 being parallel to the upper surface of the intermediate layer 10; or, The insulating filler layer 11 covers only one sidewall of the intermediate layer 10 along the second direction D2.

[0043] In one example, such as Figure 2 As shown, the insulating filler layer 11 is in the shape of a closed ring and is distributed around the outer periphery of the intermediate layer 10. This not only supports the intermediate layer 10 from all directions and further improves the mechanical strength of the intermediate layer 10, but also helps to improve the uniformity of stress distribution inside the intermediate layer 10, so as to further prevent the intermediate layer 10 from warping or other deformations.

[0044] In another example, such as Figure 3As shown, the insulating filler layer 11 is symmetrically distributed on the opposite side walls of the intermediary layer 10 along the second direction D2, which can improve the uniformity of stress distribution inside the intermediary layer 10 and help reduce the lateral area of ​​the encapsulation structure.

[0045] In yet another example, such as Figure 4 As shown, the insulating filler layer 11 covers only one sidewall of the interposer layer 10 along the second direction D2, thereby improving the mechanical strength of the interposer layer 10 and avoiding occupying too much area on the packaging substrate to meet specific design requirements.

[0046] In some embodiments, the sidewall of the upper wiring layer 12 is flush with the sidewall of the insulating fill layer 11.

[0047] For example, such as Figure 1 As shown, the sidewalls of the upper wiring layer 12 (e.g., the opposite sidewalls of the upper wiring layer 12 along the second direction D2) are flush with the sidewalls of the insulating filler layer 11 (e.g., the opposite sidewalls of the insulating filler layer 11 along the second direction D2). That is, the upper wiring layer 12 covers the entire upper surface of the interposer layer 10 and the entire front surface of the insulating filler layer 11, thereby increasing the connection strength between the upper wiring layer 12, the interposer layer 10, and the insulating filler layer 11, while also further increasing the rewiring area in the upper wiring layer 12. In one example, the sidewalls of the lower wiring layer 15 are also flush with the sidewalls of the insulating filler layer 11.

[0048] In some embodiments, the upper wiring layer 12 is provided with a plurality of chips 17 arranged at intervals along a second direction D2 on the side opposite to the intermediary layer 10, and the plurality of chips 17 are electrically connected to the upper wiring layer 12, wherein the second direction D2 is parallel to the upper surface of the intermediary layer 10.

[0049] Specifically, such as Figure 1As shown, a plurality of chips 17 are arranged at least at intervals along the second direction D2 on the surface of the upper wiring layer 12 facing away from the interposer layer 10, and all of the chips 17 are electrically connected to the upper wiring layer 12. In one example, the plurality of chips 17 are flip-chip mounted on the surface of the upper wiring layer 12 facing away from the interposer layer 10. Since the upper wiring layer 12 continuously covers the upper surface of the interposer layer 10 and the front side of the insulating filler layer 11, the area of ​​the upper wiring layer 12 is increased, thus providing sufficient space for the mounting of the plurality of chips 17, thereby further improving the integration of the package structure with the interposer layer. In one example, the plurality of chips 17 are chips with identical structure and function to further simplify the manufacturing process of the package structure with the interposer layer. In another example, at least two of the chips 17 have different structures or functions to further expand the functionality of the package structure with the interposer layer.

[0050] In some embodiments, the encapsulation structure having an intermediary layer further includes: A molding layer 19 is located on the surface of the upper wiring layer 12 opposite to the interposer layer 10, and the molding layer 19 molds the chip 17. The material of the molding layer 19 is the same as that of the insulating filler layer 11.

[0051] Specifically, the molding compound 19 is located on the surface of the upper wiring layer 12 facing away from the interposer layer 10, and continuously molds the entire chip 17 to protect the chip 17. In one example, the material of the molding compound 19 is epoxy resin molding compound or polyimide. By setting the material of the molding compound 19 to be the same as the material of the insulating filler layer 11, it helps to balance the stress on opposite sides of the upper wiring layer 12, thereby further improving the overall stability of the package structure with the interposer layer.

[0052] Figure 6 This is another cross-sectional schematic diagram of the encapsulation structure with an intermediary layer in a specific embodiment of the present invention. In some other embodiments, the encapsulation structure with an intermediary layer further includes: Component 50 is located on the side of the upper wiring layer 12 away from the interposer layer 10. Component 50 is electrically connected to the upper wiring layer 12, and component 50 and chip 17 are arranged at intervals along a direction parallel to the upper surface of the interposer layer 10.

[0053] In some embodiments, the component 50 is a passive device or a power device.

[0054] In some embodiments, the component 50 is located above the insulating filler layer 11.

[0055] In some embodiments, the upper wiring layer 12 includes a high-density region above the intermediary layer 10 and a low-density region above the insulating filler layer 11, wherein the wiring density in the high-density region is greater than the wiring density in the low-density region. The chip 17 is electrically connected to the high-density region, and the component 50 is electrically connected to the low-density region.

[0056] Specifically, since the upper wiring layer 12 continuously covers the upper surface of the interposer layer 10 and the front side of the insulating filler layer 11, the area of ​​the upper wiring layer 12 is increased. This allows not only the chip 17 to be mounted on the upper wiring layer 12, but also passive devices or power devices and other components 50, further expanding the functionality of the package structure with the interposer layer. By providing a high-density region above the interposer layer 10 and a low-density region above the insulating filler layer 11 in the upper wiring layer 12, and electrically connecting the chip 17 to the high-density region and the components 50 to the low-density region, the high-density interconnection requirements of the chip 17 and the low-density interconnection requirements of the components 50 are met. Furthermore, this achieves a reasonable allocation of wiring resources in the upper wiring layer 12 while avoiding mutual interference between the chip 17 and the components 50.

[0057] The packaging structure with an interposer provided in this specific embodiment covers the sidewalls of the interposer with an insulating filler layer, wherein the front side of the insulating filler layer is flush with the upper surface of the interposer, and the back side of the insulating filler layer is flush with the lower surface of the interposer. An upper wiring layer is continuously distributed on the upper surface of the interposer and the front side of the insulating filler layer, thereby increasing the area of ​​the upper wiring layer. This increases the possibility of fanning out more connection pins without changing the wiring density. Simultaneously, by covering the upper surface of the interposer with the upper wiring layer and the sidewalls of the interposer with the insulating filler layer, the protection of the interposer is more comprehensive, reducing the possibility of deformation or breakage, and further improving the manufacturing yield of the packaging structure. Furthermore, by covering the sidewalls of the interposer with the insulating filler layer, the insulating filler layer can act as a buffer medium to disperse stress in the interposer, allowing the thinner interposer to withstand greater warpage without causing overall breakage.

[0058] This specific embodiment makes the front side of the insulating filler layer flush with the upper surface of the interposer layer, and the back side of the insulating filler layer flush with the lower surface of the interposer layer, thereby making the thickness of the interposer layer the same as the thickness of the insulating filler layer. On the one hand, it is easier to achieve a thinner package size, so as to further reduce the package structure size; on the other hand, it simplifies the manufacturing process of the upper wiring layer, highlighting the advantages of the package structure with the interposer layer in terms of planarization and overall integration.

[0059] It should be noted that the terms "comprising" and "having," and their variations, used in this utility model document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this utility model can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this utility model. In the various embodiments described above, each embodiment focuses on the differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0060] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. A packaging structure with an intermediary layer, characterized in that, include: The intermediate layer includes an upper surface and a lower surface that are relatively distributed along a first direction; An insulating filler layer covers the sidewalls of the intermediate layer, the insulating filler layer including a front side flush with the upper surface and a back side flush with the lower surface; An upper wiring layer is continuously distributed on the upper surface of the intermediate layer and the front side of the insulating fill layer, and the upper wiring layer is electrically connected to the intermediate layer; The chip is located on the side of the upper wiring layer opposite to the interposer layer, and the chip is electrically connected to the upper wiring layer.

2. The packaging structure with an intermediary layer according to claim 1, characterized in that, Also includes: A lower wiring layer is continuously distributed on the lower surface of the intermediate layer and the back surface of the insulating filler layer, and the lower wiring layer is electrically connected to the intermediate layer.

3. The packaging structure with an intermediary layer according to claim 2, characterized in that, The interposer layer includes a via interconnect structure, with one end of the via interconnect structure electrically connected to the upper wiring layer and the other end electrically connected to the lower wiring layer.

4. The packaging structure with an intermediary layer according to claim 1, characterized in that, The intermediate layer is a silicon intermediate layer or a glass intermediate layer.

5. The packaging structure with an intermediary layer according to claim 1, characterized in that, Also includes: The packaging substrate is located on the side of the interposer layer opposite to the upper wiring layer and is electrically connected to the interposer layer; The projected area of ​​the interposer layer on the surface of the encapsulation substrate is greater than the projected area of ​​the insulating filler layer on the surface of the encapsulation substrate.

6. The packaging structure with an intermediary layer according to claim 1, characterized in that, The plurality of said interlayers are spaced apart along a second direction, and the insulating filler layer covers the sidewall of each said interlayer and fills the gap between adjacent said interlayers, the second direction being parallel to the front side of said insulating filler layer.

7. The packaging structure with an intermediary layer according to claim 6, characterized in that, The upper wiring layer is distributed on the upper surface of the plurality of intermediate layers and on the front side of the insulating fill layer.

8. The packaging structure with an intermediary layer according to claim 1, characterized in that, The insulating filler layer is distributed around the outer periphery of the intermediate layer; or... The insulating filler layer covers the opposite sidewalls of the intermediate layer along a second direction, which is parallel to the upper surface of the intermediate layer; or, The insulating filler layer covers only one sidewall of the intermediate layer along a second direction, which is parallel to the upper surface of the intermediate layer.

9. The packaging structure with an intermediary layer according to claim 1, characterized in that, The sidewall of the upper wiring layer is flush with the sidewall of the insulating filler layer.

10. The packaging structure with an intermediary layer according to claim 1, characterized in that, The upper wiring layer has a plurality of chips arranged at intervals along a second direction on the side opposite to the interposer layer, and the plurality of chips are electrically connected to the upper wiring layer. The second direction is parallel to the front side of the insulating filler layer.

11. The packaging structure with an intermediary layer according to claim 1, characterized in that, Also includes: A molding layer is located on the surface of the upper wiring layer opposite to the interposer layer, and the molding layer encapsulates the chip. The material of the molding layer is the same as that of the insulating filler layer.

12. The packaging structure with an intermediary layer according to claim 1, characterized in that, Also includes: The components are located on the side of the upper wiring layer away from the interposer layer. The components are electrically connected to the upper wiring layer, and the components and the chip are arranged at intervals along a direction parallel to the upper surface of the interposer layer.

13. The packaging structure with an intermediary layer according to claim 12, characterized in that, The components are passive or power devices.

14. The packaging structure with an intermediary layer according to claim 12, characterized in that, The component is located above the insulating filler layer.

15. The packaging structure with an intermediary layer according to claim 14, characterized in that, The upper wiring layer includes a high-density region above the intermediary layer and a low-density region above the insulating filler layer, wherein the wiring density in the high-density region is greater than the wiring density in the low-density region. The chip is electrically connected to the high-density region, and the component is electrically connected to the low-density region.

Images