Semiconductor structure and electronic device

Abstract

The present disclosure relates to a semiconductor structure and an electronic device. The semiconductor structure comprises a substrate and a chip unit. The chip unit comprises a system chip and an interface chip. The system chip is connected to the substrate through an interposer, and the interface chip is connected to the substrate and located laterally to the system chip in a first direction. The semiconductor structure moves the interface chip out of the system chip, reduces the size of the system chip, and enables the system chip and the interface chip to be manufactured using different wafers, thereby reducing manufacturing cost.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and electronic device. Background Technology

[0002] In related technologies, the layout of a system-on-a-chip (SoC) with a semiconductor structure requires additional space to accommodate I / O modules (such as C2C PHY), resulting in a larger size of the SoC and the overall package structure. Furthermore, the SoC requires high-tech wafer nodes, while the I / O modules have lower requirements for wafer technology, leading to higher costs when integrating the I / O modules with the SoC. Utility Model Content

[0003] The purpose of this disclosure is to provide a semiconductor structure and electronic device that can reduce the size of a system-on-a-chip (SoC) and allow the SoC and interface chip to be fabricated using different wafers to reduce manufacturing costs.

[0004] To achieve the above objectives, according to a first aspect of this disclosure, a semiconductor structure is provided, including a substrate and a chip unit; The chip unit includes a system chip and an interface chip; The system chip is connected to the substrate via an intermediary connection layer, and the interface chip is connected to the substrate and is located laterally to the system chip in a first direction.

[0005] Optionally, the chip unit further includes a memory chip located laterally to the system chip in a second direction and connected to the interfacing layer; The second direction is perpendicular to the first direction.

[0006] Optionally, there are multiple system chips, arranged side by side in the first direction; Each of the system chips has a plurality of memory chips arranged on opposite sides in the second direction.

[0007] Optionally, the system chips are interconnected via a UCIE structure; and / or The memory chip and the system chip are connected via a silicon bridge structure disposed in the interfacing layer.

[0008] Optionally, the memory chip includes a computing module with a UCIE interface and a plurality of memory modules stacked sequentially on the computing module.

[0009] Optionally, the system chip, the memory chip, and the interfacing layer are packaged to form a package structure.

[0010] Optionally, in the first direction, at least one of the interface chips is provided on each of the opposite sides of the packaging structure.

[0011] Optionally, the semiconductor structure further includes a reinforcing ring connected to the substrate and surrounding the circumference of the chip unit.

[0012] Optionally, the system chip and the interface chip are manufactured using different processes.

[0013] According to a second aspect of this disclosure, an electronic device is also provided, the electronic device comprising the semiconductor structure described above.

[0014] Through the above-described technical solution, namely the semiconductor structure disclosed herein, the interface chip is moved out of the original system chip and connected to the substrate. The system chip is connected to the substrate through an interposer layer, and the interposer layer is connected to the interface chip through wiring in the substrate. On the one hand, the size of the system chip can be reduced; on the other hand, the system chip and the interface chip can be fabricated using different wafers. For example, the interface chip can use a lower-tech wafer node to reduce manufacturing costs.

[0015] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the system chip structure in related technologies; Figure 2 This is a top view of a semiconductor structure provided in some embodiments of this disclosure; Figure 3 This is a cross-sectional view of a semiconductor structure provided in some embodiments of this disclosure; Figure 4 This is a schematic diagram of a system chip provided in some embodiments of this disclosure; Figure 5 This is a schematic diagram of the structure of a memory chip provided in some embodiments of this disclosure; Figure 6 This is a bottom view of a memory chip provided in some embodiments of this disclosure.

[0017] Explanation of reference numerals in the attached figures 100-substrate; 200 - Chip unit; 210 - System chip; 210a - Package structure; 211 - Intermediate connection layer; 220 - Interface chip; 230 - Memory chip; 231 - Computing module; 2311 - UCIE interface; 232 - Memory module; 300 - Reinforcing ring. Detailed Implementation

[0018] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0019] In this disclosure, unless otherwise stated, directional terms such as "upper," "lower," "left," and "right" generally refer to upper, lower, left, and right relative to the figures; "inner" and "outer" refer to the inner and outer contours of the corresponding components; and "far" and "near" refer to the corresponding structure or component being away from or near another structure or component. In the figures of this disclosure, X indicates a first direction; Y indicates a second direction. Furthermore, the terms "first," "second," etc., used in this disclosure are for distinguishing one element from another and do not have sequential or importance implications. In addition, in the following description, when referring to the figures, unless otherwise explained, the same reference numerals in different figures denote the same or similar elements. The above definitions are for explanation and illustration only and should not be construed as limiting this disclosure.

[0020] like Figure 1 The diagram shows the layout of a System on a Chip (SOC) in a semiconductor structure in related technologies. The SOC requires additional space to accommodate I / O modules 201 (e.g., C2C PHY), resulting in a larger size for the SOC and the overall package structure. While the SOC requires high-tech wafer nodes, the I / O modules 201 have lower requirements for wafer technology. Furthermore, because the I / O modules 201 are located on the SOC, the cost of integrating the I / O modules 201 with the SOC is higher.

[0021] The purpose of this disclosure is to provide a semiconductor structure and an electronic device that can reduce the size of a system chip 210, and that the system chip 210 and the interface chip 220 can be fabricated using different wafers to reduce manufacturing costs and electronic devices.

[0022] To achieve the above objectives, according to the first aspect of this disclosure, as shown in Figures 2 to 30, Figure 6As shown, a semiconductor structure is provided, which includes a substrate 100 and a chip unit 200; the chip unit 200 includes a system chip 210 and an interface chip 220; the system chip 210 is connected to the substrate 100 through an interfacing layer 211, and the interface chip 220 is connected to the substrate 100 and is located laterally to the system chip 210 in a first direction.

[0023] Through the above-described technical solution, namely the semiconductor structure disclosed herein, the interface chip 220 is removed from the original system chip 210 and connected to the substrate 100. The system chip 210 is connected to the substrate 100 through an interposer layer 211, and the interposer layer 211 is connected to the interface chip 220 through wiring in the substrate 100. On the one hand, the size of the system chip 210 can be reduced; on the other hand, the system chip 210 and the interface chip 220 can be fabricated using different wafers. For example, the interface chip 220 can use a lower-tech wafer node to reduce manufacturing costs.

[0024] In some embodiments, in addition to the system chip 210 described above, the chip unit 200 also includes a memory chip 230, which is located laterally to the system chip 210 in a second direction and is connected to the interfacing layer 211. The second direction is perpendicular to the first direction.

[0025] To further illustrate the positional relationship of the chip unit 200, two directions are defined: a first direction and a second direction, with the second direction perpendicular to the first direction. The memory chip 230 is positioned laterally to the system chip 210 in the second direction. From a spatial layout perspective, with the system chip 210 as the reference center, and viewed along the second direction perpendicular to the first direction, the memory chip 230 is located on at least one side of the system chip 210. This lateral layout takes into account various factors, such as signal transmission requirements between chips, wiring convenience, and overall structural compactness. Therefore, corresponding interface modules can be placed near the edge of the system chip 210 in the second direction for connection to the memory chip 230.

[0026] It should be noted that, in terms of electrical connection, the memory chip 230 is connected to the interfacing layer 211. The interfacing layer 211 plays a crucial role in the entire chip structure, providing a bridge for electrical connections and a platform for physical support between the various chips. The memory chip 230 achieves a stable connection with the interfacing layer 211 through specific connection methods (such as metal wiring, solder joints, etc.), thereby ensuring that the memory chip 230 can effectively transmit data and exchange signals with the system chip 210 and other related components. This connection method ensures that the memory chip 230 and the system chip 210 work together to complete the functional tasks undertaken by the entire chip unit 200, providing a solid foundation for the stable operation of the device.

[0027] It should be noted that the interposer layer 211 of this disclosure can be any suitable structure, for example, it can be a silicon interposer, or of course, it can be other structural forms, which can realize the connection between the system chip 210 and the memory chip 230 and the substrate 100.

[0028] Optionally, the system-on-a-chip 210 and the interface chip 220 can be fabricated using different processes. For example, the system-on-a-chip 210 has higher requirements for wafer processing and can be manufactured using a more advanced process, while the interface chip 220 has relatively lower requirements for wafer processing and can be manufactured using a less advanced process, thereby saving processing costs. Of course, the system-on-a-chip 210 and the interface chip 220 can also be fabricated using the same process. Because they are fabricated separately, the fabrication of the interface chip 220 is more flexible.

[0029] It should be noted that high-tech wafer nodes are an important concept in the semiconductor manufacturing field used to measure the level of process technology. High-tech wafer nodes typically refer to those in semiconductor manufacturing processes where the feature size of transistors has reached an extremely small level, evolving from the early micrometer level to today's nanometer level. 28nm, 14nm, 7nm, and 3nm are all different wafer nodes. These numbers represent key dimensions such as transistor gate length; the smaller the number, the more advanced the manufacturing process, allowing more transistors to be integrated on the same wafer area, thereby improving chip performance and functionality. Therefore, in some embodiments, the wafer node of the system chip 210 is smaller than that of the interface chip 220. Compared to related technologies, the interface chip 220 does not need to use the same wafer node as the system chip 210, thus reducing manufacturing costs.

[0030] There can be multiple system chips 210, arranged side-by-side in the first direction X; multiple memory chips 230 are arranged on opposite sides of each system chip 210 in the second direction Y. The multiple memory chips can be electrically connected to the system chip 210 for its operational needs. It should be noted that "multiple system chips 210" and "multiple memory chips 230" here refer to two or more system chips 210 and memory chips 230.

[0031] like Figure 2 As shown, in some embodiments, there can be two system chips 210, arranged side-by-side in a first direction; two memory chips 230 are arranged on opposite sides of each system chip 210 in a second direction. The two system chips 210 are arranged side-by-side in the first direction and can be connected via an interface, for example, through a UCIE structure, to ensure data transmission or signal interaction. It should be noted that the two system chips 210 can also be connected via a PCIe structure, as long as data transmission and signal interaction are guaranteed.

[0032] Two memory chips 230 are arranged on each side of the system chip 210 in the second direction, and both the system chip 210 and the memory chips 230 are arranged on the interfacing layer 211 and connected through the interfacing layer 211. This can shorten the physical distance of data transmission. A shorter transmission distance means lower resistance and capacitance, thereby reducing energy loss during signal transmission.

[0033] The memory chip 230 and the system chip 210 can be connected using any suitable structure. For example, the memory chip 230 and the system chip 210 can be connected through a silicon bridge structure arranged on the interposer layer 211. The interposer layer 211 plays a crucial supporting and connecting role in the entire chip structure, providing the physical basis and electrical connection platform for the arrangement of the silicon bridge structure. The silicon bridge structure itself has unique performance and characteristics; it is typically made of silicon-based materials and has excellent conductivity and signal transmission characteristics. The silicon bridge contains a large number of fine metal lines and connection interfaces. These lines and interfaces are precisely designed and laid out to provide an efficient and stable channel for data transmission between the memory chip 230 and the system chip 210. Through these lines, data stored in the memory chip 230 can be quickly and accurately transmitted to the system chip 210 for processing, and the results processed by the system chip 210 can be promptly fed back to the memory chip 230 for storage or further operation.

[0034] It is understandable that the aforementioned silicon bridge structure is common knowledge in related technologies, and those skilled in the art can design it as needed, so it will not be elaborated here.

[0035] The memory chip 230 can be constructed using any suitable structure, such as Figure 3 , Figure 5 and Figure 6 As shown, in some embodiments of this disclosure, the memory chip 230 may include a computing module 231 having a UCIE interface 2311, and a plurality of memory modules 232 stacked sequentially on the computing module 231.

[0036] In traditional chip design, it is often difficult to achieve efficient collaboration between chips from different manufacturers. UCIE, as an open standard, enables the computing module 231 using this interface to seamlessly connect the memory chip 230 with other chiplets that also support the UCIE standard. Regardless of the manufacturer of these chiplets, as long as they conform to the UCIE standard, they can interact with the memory chip 230 and work collaboratively, greatly enhancing the versatility of the memory chip 230 across different systems.

[0037] Furthermore, modern computing systems typically require the integration of various chips with different functions, such as processors, accelerators, and memory chips 230. The computing module 231 with a UCIE interface 2311 enables the memory chip 230 to be easily integrated with other types of chiplets to build a heterogeneous computing system.

[0038] Among them, UCIE (Universal Chiplet Interconnect Express) is an open standard that is not dependent on specific technologies or manufacturers. Any company can develop and produce chiplet products based on this standard, promoting the division of labor and collaboration throughout the semiconductor industry. UCIE enables high-speed interconnection: it provides high-bandwidth, low-latency interconnect solutions to meet the needs of rapid transmission of large amounts of data between different chiplets, ensuring the efficient operation of systems composed of multiple chiplets.

[0039] For example, the memory chip 230 can be HBM (High Bandwidth Memory), which includes multiple DRAM (Dynamic Random Access Memory) modules stacked sequentially. Compared with traditional memory architectures, HBM can significantly reduce power consumption during data transmission and improve energy efficiency.

[0040] To better achieve stability between various components, such as Figure 3As shown, in some embodiments, the system chip 210, the memory chip 230, and the interposer layer 211 are packaged to form a package structure 210a. The system chip 210 and the memory chip 230, connected above the interposer layer 211, can be packaged together using a packaging material to form the package structure 210a. The package structure 210a may have a protruding ball grid array underneath for connection with the substrate 100. The system chip 210 and the memory chip 230 located inside the package structure 210a can achieve a more stable connection, avoiding the influence of the external environment.

[0041] There can be multiple interface chips 220, which can be respectively connected to the substrate 100 and located on the side of the packaging structure 210a. In some embodiments, at least one interface chip 220 is provided on each opposite side of the packaging structure 210a in the first direction. Figure 3 As shown, an interface chip 220 can be arranged on both sides of the first direction of the package structure 210a. The interface chip 220 can be connected to the intermediate connection layer 211 through the metal wiring arranged on the substrate 100, thereby realizing the connection with the system chip 210 through the intermediate connection layer 211.

[0042] Because the chip unit 200 generates heat during operation, it can cause the substrate 100 to warp. Significant warping of the substrate 100 may affect the chip's operation. To further prevent warping of the substrate 100, such as... Figure 2 and Figure 3 As shown, the semiconductor structure also includes a reinforcing ring 300, which is fixedly connected to the substrate 100 and surrounds the chip unit 200 circumferentially. The reinforcing ring 300 can be constructed using any suitable structure; for example, it can be an integral ring structure fixedly connected to the surface of the substrate 100 and located circumferentially in the chip unit 200. The reinforcing ring 300 reduces or suppresses warping of the substrate 100, thereby ensuring the stable and reliable operation of the chip unit 200.

[0043] According to a second aspect of this disclosure, an electronic device is also provided, which includes the semiconductor structure described above. Therefore, the electronic device also has the advantages of the semiconductor structure described above, which will not be repeated here.

[0044] The semiconductor structure and electronic device disclosed herein involve removing the interface chip 220 from the original system chip 210 and connecting it to a substrate 100. The system chip 210 is connected to the substrate 100 via an interposer layer 211, which is connected to the interface chip 220 via wiring in the substrate 100. In other words, the system chip 210 and the interface chip 220 are connected to the substrate 100 through a multi-chip module package. This approach reduces the size of the system chip 210 and allows the system chip 210 and interface chip 220 to be fabricated using different wafers. For example, the system chip 210 can use a higher-tech wafer node, while the interface chip 220 can use a lower-tech wafer node, thereby reducing manufacturing costs.

[0045] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0046] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0047] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor structure, characterized in that, Includes substrate and chip unit; The chip unit includes a system chip and an interface chip; The system chip is connected to the substrate via an intermediary connection layer, and the interface chip is connected to the substrate and is located laterally to the system chip in a first direction.

2. The semiconductor structure according to claim 1, characterized in that, The chip unit further includes a memory chip, which is located laterally to the system chip in a second direction and is connected to the interfacing layer; The second direction is perpendicular to the first direction.

3. The semiconductor structure according to claim 2, characterized in that, The system chips are multiple and arranged side by side in the first direction; Each of the system chips has a plurality of memory chips arranged on opposite sides in the second direction.

4. The semiconductor structure according to claim 3, characterized in that, The system chips are interconnected via a UCIE structure; and / or The memory chip and the system chip are connected via a silicon bridge structure disposed in the interfacing layer.

5. The semiconductor structure according to claim 2, characterized in that, The memory chip includes a computing module with a UCIE interface and multiple memory modules stacked sequentially on the computing module.

6. The semiconductor structure according to any one of claims 2-5, characterized in that, The system chip, the memory chip, and the intermediary connection layer are packaged to form a package structure.

7. The semiconductor structure according to claim 6, characterized in that, In the first direction, at least one interface chip is provided on each of the opposite sides of the packaging structure.

8. The semiconductor structure according to any one of claims 1-5, characterized in that, The semiconductor structure further includes a reinforcing ring connected to the substrate and surrounding the circumference of the chip unit.

9. The semiconductor structure according to any one of claims 1-5, characterized in that, The system chip and the interface chip are manufactured using different processes.

10. An electronic device, characterized in that, The electronic device includes the semiconductor structure described in any one of claims 1-9.

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