Packaging structure

Abstract

The utility model provides a kind of packaging structure, the packaging structure includes rewiring layer;Preset piece DRAM area, setting in the upper of rewiring layer;Reinforcing structure, setting below preset piece DRAM area and reinforcing structure presents transparent characteristic under visible condition.The utility model presents transparent characteristic under visible condition by setting reinforcing structure, not only can realize the mechanical support to packaging structure, and, since the reinforcing structure has transparent characteristic, it can also avoid shielding positioning mark in packaging structure upper board process, ensure accurate alignment, avoid the problem caused by inaccurate alignment, prevent laser processing from causing damage to positioning mark simultaneously, to effectively improve the mounting precision and production yield.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and specifically to a packaging structure. Background Technology

[0002] Due to the high cost of DRAM (Dynamic Random-Access Memory), while DRAM can be mounted on top of the AP (Application Processor) in a FOPoP (Fan-Out Package on Package) architecture, this stacking method hinders AP heat dissipation and affects product performance. To improve heat dissipation, a design is typically used where the system-on-a-chip (SoC) and DRAM are placed side-by-side, with reserved DRAM mounting area. However, because the redistribution layer is thin and has low mechanical strength, it is easily damaged during DRAM mounting. Therefore, a reinforcing structure can be added below the adjacent DRAM placement area to improve structural strength. However, since current reinforcing structures are generally made of molding materials, they not only obstruct positioning marks during board mounting, leading to inaccurate chip location identification and alignment deviations, but also may damage nearby positioning marks when laser-drilled holes, thus affecting mounting yield. Utility Model Content

[0003] This utility model proposes a packaging structure.

[0004] Firstly, this utility model proposes a packaging structure, including:

[0005] Rewire layer;

[0006] A pre-installed DRAM region is disposed above the redistribution layer;

[0007] A reinforcing structure is disposed below the DRAM region of the pre-installed component, and the reinforcing structure is transparent under visible conditions.

[0008] In some optional embodiments, the packaging structure further includes:

[0009] A molding layer is disposed above the redistribution layer, and the thickness of the reinforcing structure is greater than the thickness of the molding layer.

[0010] In some alternative embodiments, the reinforcing structure is made of glass.

[0011] In some alternative embodiments, the reinforcing structure does not contain silicon filler.

[0012] In some optional embodiments, the reinforcing structure has conductive holes inside, and the diameter of the conductive holes gradually decreases from bottom to top, presenting a tapered structure.

[0013] In some optional embodiments, the rewiring layer is provided with vias, the diameter of which gradually increases from bottom to top, presenting a tapered structure.

[0014] In some optional embodiments, the packaging structure further includes:

[0015] A positioning mark is disposed below the DRAM region of the pre-installed component and the positioning mark is located between the redistribution layer and the reinforcement structure.

[0016] In some alternative implementations, the locating marker contacts the reinforcing structure.

[0017] In some alternative implementations, the locating marker is embedded within the redistribution layer.

[0018] In some optional embodiments, the packaging structure further includes:

[0019] The chip is disposed on the redistribution layer and located on one side of the preset DRAM region.

[0020] To address the current issues where reinforcement structures, typically made of molding materials, not only obscure positioning marks during board mounting, leading to inaccurate chip identification and alignment deviations, but also potentially damage nearby positioning marks during laser drilling, thus affecting mounting yield, this invention proposes a packaging structure. By placing the pre-installed DRAM area above the redistribution layer and the reinforcement structure below it, and by ensuring the reinforcement structure is transparent under visible conditions, this not only provides mechanical support for the packaging structure but also, due to its transparency, avoids obscuring positioning marks during board mounting, ensuring precise alignment and preventing problems caused by misalignment. Furthermore, it prevents damage to positioning marks during laser processing, thereby effectively improving mounting accuracy and production yield. Attached Figure Description

[0021] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0022] Figure 1 This is a schematic diagram of an existing packaging structure for mounting DRAM on an AP;

[0023] Figure 2 This is a schematic diagram of an existing packaging structure that arranges AP and DRAM side by side;

[0024] Figure 3This is a schematic diagram of a packaging structure for an existing reserved DRAM mounting area;

[0025] Figure 4 This is a schematic diagram of the packaging structure 4a according to an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of the packaging structure 5a according to an embodiment of the present invention;

[0027] Figures 6-16 This is a schematic diagram of the manufacturing steps of the packaging structure 4a according to an embodiment of the present invention;

[0028] Figures 17-28 This is a schematic diagram of the manufacturing steps of the packaging structure 5a according to an embodiment of the present invention.

[0029] Explanation of reference numerals / symbols in the attached diagram:

[0030] 101-DRAM; 102-AP; 103-System-on-a-Chip; 104-DRAM; 105-DRAM Placement Area; 106-Rewiring Layer; 201-Rewiring Layer; 202-Pre-placed DRAM Area; 203-Reinforcement Structure; 204-Molding Layer; 205-Conductive Hole; 206-Through Hole; 207-Position Marker; 208-Chip; 209-Solder Paste; 210-Metal Frame; 211-Solder Ball; 212-Dummy Chip; 213-Silicon Heatsink; 214-DRAM; 215-Thin Film. Detailed Implementation

[0031] The specific embodiments of this utility model will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this utility model and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0032] It should be readily understood that the meanings of "on," "above," and "on top of" in this utility model should be interpreted in the broadest sense, such that "on" not only means "directly on something," but also means "on something" including intermediate components or layers existing between the two.

[0033] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0034] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0035] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0036] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the implementation conditions of this utility model and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this utility model, should still fall within the scope of the technical content disclosed in this utility model. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of implementation of this utility model. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this utility model.

[0037] It should also be noted that the longitudinal section corresponding to the embodiment of this utility model can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0038] Furthermore, where there is no conflict, the embodiments and features described in these embodiments can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] refer to Figures 1-3 , Figure 1 This is a schematic diagram of an existing packaging structure for mounting DRAM on an application processor (AP). Figure 2 This is a schematic diagram of an existing packaging structure that arranges the AP and DRAM side by side. Figure 3 This is a schematic diagram of a packaging structure for an existing reserved DRAM component area.

[0040] like Figure 1 As shown, DRAM101 is stacked on top of AP102 chip. This stacking layout obstructs the heat dissipation path of AP102, causing heat accumulation and affecting product performance. To improve heat dissipation, the following can be adopted: Figure 2 The side-by-side layout shown places the system-on-a-chip 103 and DRAM 104 side-by-side in the same package level. This design improves overall heat dissipation efficiency, but it requires the system-on-a-chip 103 and DRAM 104 to be integrated simultaneously during the packaging stage. The DRAM 104 cannot be packaged separately as a subsequent process. If the customer does not have an actual product requiring the DRAM 104, it will incur significant costs. Figure 3 A package structure with a reserved DRAM placement area is proposed, allowing for the selection of whether to install DRAM104 based on requirements, thereby reducing costs. However, in this package structure, the redistribution layer 106 is relatively thin and has low mechanical strength, making it susceptible to damage during subsequent DRAM104 mounting. To address this, a reinforcing structure can be added below the adjacent DRAM placement area to improve structural strength. However, since current reinforcing structures are generally made of molding materials, they not only obstruct the positioning marks during board mounting, leading to inaccurate chip location identification and alignment deviations, but also may damage nearby positioning marks when laser apertures are used, thus affecting mounting yield.

[0041] refer to Figure 4 , Figure 4 This is a schematic diagram of the packaging structure 4a according to an embodiment of the present invention.

[0042] The packaging structure 4a of this utility model may include a redistribution layer 201, a pre-installed DRAM region 202, and a reinforcing structure 203.

[0043] The preset DRAM region 202 is disposed above the redistribution layer 201. The reinforcement structure 203 is disposed below the preset DRAM region 202 and is transparent under visible conditions.

[0044] In some alternative embodiments, the package structure 4a further includes a positioning mark 207 disposed below the preset DRAM region 202 and located between the redistribution layer 201 and the reinforcement structure 203.

[0045] In some alternative implementations, the locating marker 207 is embedded in the redistribution layer 201.

[0046] In some alternative implementations, the locating marker 207 contacts the reinforcing structure 203.

[0047] Specifically, the positioning mark 207 can be set at the bottom layer of the redistribution layer 201, on the side close to the reinforcing structure 203.

[0048] Thus, because the reinforcing structure 203 is transparent, when the reinforcing structure 203 is placed below the positioning mark 207, the position of the positioning mark 207 can be clearly captured through the transparent reinforcing structure 203, achieving high-precision visual alignment. Therefore, the reinforcing structure 203 can not only provide the necessary mechanical support for the entire packaging structure 4a, but also, due to its transparent nature, avoid obscuring the positioning mark during the packaging structure 4a board mounting process, ensuring accurate alignment and effectively avoiding problems caused by misalignment. At the same time, it prevents laser processing from damaging the positioning mark, which can effectively improve mounting accuracy and production yield.

[0049] In some alternative embodiments, the reinforcing structure 203 is made of glass material; for example, the reinforcing structure 203 can be a glass carrier plate to provide excellent mechanical support and good transparency.

[0050] In some alternative embodiments, the reinforcing structure 203 does not contain silicon filler. Thus, by avoiding the use of materials containing silicon filler, the uniformity and transparency of the reinforcing structure 203 can be further improved, reducing stress concentration and optical interference caused by filler scattering or uneven thermal expansion, thereby better meeting the dual requirements of structural strength and visibility.

[0051] In some alternative embodiments, the reinforcing structure 203 is provided with a conductive hole 205, the diameter of which gradually decreases from bottom to top, presenting a tapered structure.

[0052] Here, the conductive hole 205 can penetrate the reinforcing structure 203 from bottom to top, forming a tapered structure that is narrower at the top and wider at the bottom, which can help improve the reliability of the electrical connection.

[0053] In some alternative embodiments, the rewiring layer 201 is provided with a via 206, the diameter of which gradually increases from bottom to top, presenting a tapered structure.

[0054] Here, the via 206 can form a reverse tapered structure that is narrow at the bottom and wide at the top. The conductive hole 205 and the via 206 are positioned correspondingly in the stacked structure and can be in direct contact to form a continuous electrical conduction path and improve connection reliability.

[0055] In some alternative embodiments, the packaging structure 4a further includes a molding layer 204 disposed above the redistribution layer 201, and the thickness of the reinforcing structure 203 is greater than the thickness of the molding layer 204.

[0056] Here, the reinforcing structure 203 can be disposed below the pre-installed DRAM region 202 and further extend to cover the area below the entire redistribution layer 201. By extending the reinforcing structure 203 to the area below the entire redistribution layer 201, not only is the local mechanical strength of the pre-installed DRAM region 202 significantly improved, but the thickness of the reinforcing structure 203 is also greater than the thickness of the molding layer 204, providing stronger support and further enhancing the overall rigidity of the entire package structure 4a, thereby ensuring structural stability and reliability during DRAM mounting and subsequent processes.

[0057] In some alternative implementations, the package structure 4a may also include a chip 208 disposed on the redistribution layer 201 and located on one side of the preset DRAM region 202.

[0058] Chip 208 and pre-installed DRAM region 202 can be arranged side by side. The mold layer 204 can cover chip 208 and protect chip 208. The pre-installed DRAM region 202 can be exposed by selectively removing the mold layer 204, forming a reserved area for subsequent DRAM device mounting.

[0059] This packaging structure 4a achieves a planar co-packaging layout of the chip 208 and DRAM, avoiding the heat dissipation problems caused by stacked structures, while retaining the flexibility of DRAM post-mounting through partial windowing, thus balancing heat dissipation performance, structural strength, and production adaptability. Simultaneously, the design of the transparent reinforcing structure 203 and the built-in positioning mark 207 ensures high-precision alignment during DRAM mounting, further improving the overall packaging yield.

[0060] The above describes the packaging structure 4a of one embodiment of the present invention.

[0061] refer to Figure 5 , Figure 5This is a schematic diagram of the packaging structure 5a according to an embodiment of the present invention.

[0062] Figure 5 The package structure 5a shown is similar to Figure 4 The packaging structure 4a shown differs in that:

[0063] The packaging structure 5a may also include solder paste 209 and a metal frame 210. Solder paste 209 may be disposed on the surface of the pre-placed DRAM region 202 for subsequent soldering connection of DRAM devices. The metal frame 210 may be disposed on both sides of the pre-placed DRAM region 202. On the one hand, it provides additional mechanical support for the pre-placed DRAM region 202 and enhances the stability of the local structure. On the other hand, the metal frame 210 can act as a barrier to block the flow of molding material during the molding process and prevent the mold flow from intruding into the pre-placed DRAM region 202. This effectively protects the pre-placed DRAM region 202 from contamination or coverage, ensuring that it can be clearly exposed in subsequent processes and used for accurate DRAM mounting.

[0064] The above describes the packaging structure 5a of one embodiment of the present invention.

[0065] Figures 6-16 This is a schematic diagram of the manufacturing steps of the packaging structure 4a according to an embodiment of the present invention.

[0066] refer to Figure 6 It provides a reinforcing structure 203, a rewiring layer 201, a through hole 206, and a positioning mark 207.

[0067] The reinforcing structure 203 is transparent under visible conditions. The reinforcing structure 203 can be set below the redistribution layer 201. The positioning mark 207 can be embedded in the redistribution layer 201 and contacts the reinforcing structure 203.

[0068] Specifically, the positioning mark 207 can be set at the bottom layer of the redistribution layer 201, on the side close to the reinforcing structure 203.

[0069] The rewiring layer 201 has a via 206 inside, and the diameter of the via 206 gradually increases from bottom to top, presenting a tapered structure.

[0070] refer to Figure 7 The chip 208 can be bonded to the redistribution layer 201 using a flip-chip bonding process. After bonding is completed, the gap between the chip 208 and the redistribution layer 201 can be filled with bottom filler glue.

[0071] refer to Figure 8 A virtual chip 212 is set on the redistribution layer 201.

[0072] The virtual chip 212 can be set up side by side with the chip 208 to more accurately define and reserve the position and range of the preset DRAM area 202 in subsequent processes.

[0073] refer to Figure 9 The chip 208 and the virtual chip 212 are molded to form a molding layer 204.

[0074] The mold layer 204 can cover the chip 208 and the virtual chip 212.

[0075] refer to Figure 10 The reinforcing structure 203 is thinned and ground.

[0076] refer to Figure 11 Laser ablation is performed to form the location of the conductive hole 205.

[0077] Here, the conductive hole 205 can penetrate the reinforcing structure 203 from bottom to top. This allows for better control of the behavior of the filling material, avoiding hole deformation or incomplete filling due to the compression of the filling material. The wider end of the trapezoidal conductive hole 205 faces the surface, which facilitates the flow and filling of molten solder or other conductive materials, reducing the risk of being squeezed by surrounding materials, thereby ensuring the quality and reliability of the electrical connection.

[0078] refer to Figure 12 Fill the conductive hole 205 and set the solder ball 211.

[0079] refer to Figure 13 The molding layer 204 is polished to make its surface basically flush with the chip 208.

[0080] refer to Figure 14 Laser cutting is performed on the molding layers 204 on both sides of the virtual chip 212.

[0081] In this way, the boundary of the pre-placed DRAM area 202 can be precisely defined, ensuring that the area remains clear and intact in subsequent processing, and reserving ideal space for DRAM mounting.

[0082] refer to Figure 15 The overall structure is cut into individual packaged structures.

[0083] refer to Figure 16 Remove the virtual chip 212 to form the pre-built DRAM region 202.

[0084] Figures 17-28 This is a schematic diagram of the manufacturing steps of the packaging structure 5a according to an embodiment of the present invention.

[0085] refer to Figure 17It provides a reinforcing structure 203, a rewiring layer 201, a through hole 206, and a positioning mark 207.

[0086] refer to Figure 18 Solder paste 209 is applied to the surface of the redistribution layer 201 corresponding to the preset DRAM region 202.

[0087] refer to Figure 19 Metal frames 210 are installed on both sides of the area where solder paste 209 has been applied.

[0088] The metal frame 210 is located outside the pre-installed DRAM area 202 and serves to support and enclose it.

[0089] refer to Figure 20 Chip 208 is installed on redistribution layer 201, and flux removal cleaning is performed after installation.

[0090] The chip 208 is arranged side by side with the metal frame 210, located near the preset DRAM area 202.

[0091] refer to Figure 21 A silicon heat sink 213 is placed over the chip 208 and the metal frame 210.

[0092] Specifically, you can refer to Figure 22 A thin film 215 is used to cover a silicon heat sink 213 over the chip 208 and the metal frame 210.

[0093] refer to Figure 22 The chip 208 and the silicon heat sink 213 are molded to form a molding layer 204.

[0094] At this time, since the metal frame 210 is located on both sides of the pre-installed DRAM area 202 and a silicon heat sink 213 is provided above it, the two together form an effective physical barrier structure, which can prevent the mold flow during molding from flowing into the pre-installed DRAM area 202. This sealing and blocking mechanism ensures that the area remains clean during the packaging process, reserving complete and precise space for the subsequent individual mounting of DRAM devices.

[0095] It should be noted that in subsequent processes, when the reinforcing structure 203 is made of glass, the following can be referenced. Figures 10-12 The same processing steps can also be applied when the reinforcing structure 203 is replaced with a molding material, such as... Figures 23-28 Process it.

[0096] refer to Figure 23 Remove the reinforcing structure 203 and form solder balls 211 on the redistribution layer.

[0097] refer to Figure 24The solder ball 211 is ground to make its surface flat and reach the required height. Then, the solder ball 211 is molded to form a reinforced structure 203 with the molding material.

[0098] refer to Figure 25 Laser ablation is performed on both sides of the location of the solder ball to form a trapezoidal structure.

[0099] The trapezoidal structure provides better support and more precise filling space, ensuring that the solder balls are not deformed by the pressure of the surrounding materials during the remelting process, thus guaranteeing the consistency and reliability of the solder balls.

[0100] refer to Figure 26 Then, the solder ball 211 is replaced.

[0101] refer to Figure 27 The molding layer 204 and the silicon heat sink 213 are polished to remove excess material and define the DRAM region 202 that forms the preform.

[0102] refer to Figure 28 DRAM214 can be set in the preset DRAM area 202.

[0103] The following is a brief introduction to the thickness of each component in package structure 4a and package structure 5a.

[0104] The thickness of chip 208 can be 500μm with a tolerance of ±7.5μm, and the thickness of the bottom solder joint of chip 208 can be 50μm.

[0105] The thickness of film 215 can be 50.

[0106] The thickness of the virtual chip 212 can be 300μm, with a tolerance of ±7.5μm.

[0107] The thickness of solder ball 211 can be 180μm, with a tolerance of ±30μm.

[0108] The thickness of the redistribution layer 201 can be 41 μm.

[0109] The thickness of the sealing layer 204 can be 1100μm, with a tolerance of ±30μm.

[0110] The width of the metal frame 210 can be 1.2 / 1.0 / 1.2 / 0.9 mm, and the height can be 530 μm.

[0111] The thickness of solder paste 209 can be 20μm.

[0112] The distance between the outer edges of the frame 210 and the sealing layer 204 can be 300 μm.

[0113] Although the present invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of the invention. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation of the invention and actual implementation due to variables in the manufacturing process, etc. Other embodiments of the invention may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the invention.

Claims

1. A packaging structure, characterized in that, The packaging structure includes: Rewire layer; A pre-installed DRAM region is disposed above the redistribution layer; A reinforcing structure is disposed below the DRAM region of the pre-installed component, and the reinforcing structure is transparent under visible conditions.

2. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: A molding layer is disposed above the redistribution layer, and the thickness of the reinforcing structure is greater than the thickness of the molding layer.

3. The packaging structure according to claim 1, characterized in that, The reinforcing structure is made of glass.

4. The packaging structure according to claim 1, characterized in that, The reinforcing structure does not contain silicon filler.

5. The packaging structure according to claim 1, characterized in that, The reinforcing structure has conductive holes inside, and the diameter of the conductive holes gradually decreases from bottom to top, forming a conical structure.

6. The packaging structure according to claim 1, characterized in that, The rewiring layer has through holes inside, and the diameter of the through holes gradually increases from bottom to top, presenting a tapered structure.

7. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: A positioning mark is disposed below the DRAM region of the pre-installed component and the positioning mark is located between the redistribution layer and the reinforcement structure.

8. The packaging structure according to claim 7, characterized in that, The positioning mark contacts the reinforcing structure.

9. The packaging structure according to claim 8, characterized in that, The positioning marker is embedded in the rewire layer.

10. The packaging structure according to claim 2, characterized in that, The packaging structure further includes a chip disposed on the redistribution layer and located on one side of the preset DRAM region.

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