Wafer package bonding structure

Abstract

The utility model provides a kind of wafer packaging bonding structure, including bearing substrate, release layer is set on the upper surface of bearing substrate, metal buffer layer covers the upper surface of release layer, release layer is used to adhere metal buffer layer with bearing substrate, temporary bonding layer covers the upper surface of metal buffer layer, wafer is located temporary bonding layer upper surface, temporary bonding layer is used to adhere metal buffer layer with wafer, by adding a layer of metal buffer layer with high thermal conductivity between temporary bonding layer and release layer, heat is conducted to temporary bonding layer by the buffering effect of metal buffer layer from release layer, so that the heat distribution of temporary bonding layer is more uniform, so as to improve the temperature uniformity of wafer on the upper surface of temporary bonding layer, and then improve the uniformity and stability of thin film on the upper surface of wafer obtained by chemical vapor deposition.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor packaging technology and relates to a wafer packaging bonding structure. Background Technology

[0002] As integrated circuits evolve towards higher performance, higher integration, and smaller size, the requirements for packaging processes are becoming increasingly stringent. 2.5D packaging technology, as an advanced packaging process, is widely used due to its advantages such as high performance, large capacity, and high yield. Fabricating copper electrode structures using exposed copper technology is a crucial step in 2.5D packaging, requiring the formation of an insulating layer on the thinned silicon wafer surface.

[0003] Forming a high-quality, uniform insulating layer (such as oxide or nitride) on the thinned silicon wafer surface is a key step in 2.5D packaging. A complex process flow is typically employed to obtain the final insulating layer surface, generally including: chemical mechanical polishing (CMP), silicon etching, growth of the nitride or oxide insulating layer via chemical vapor deposition (CVD), and a final oxide planarization step via CMP. Because thinned wafers are fragile, a carrier substrate is needed to provide support by bonding it to the wafer with a temporary bonding layer, forming a wafer-supporting packaging bonding structure. Currently, the materials used for the temporary bonding layers between the wafer and the carrier substrate are not heat-resistant and have low thermal conductivity. During low-temperature CVD deposition, the heat transfer between the wafer and the carrier substrate deteriorates, resulting in poor temperature uniformity of the wafer, which in turn affects the uniformity and stability of the insulating layer formed on the wafer surface.

[0004] Therefore, how to effectively improve the uniformity of wafer temperature during low-temperature CVD deposition is an urgent problem to be solved in the current semiconductor packaging field. Utility Model Content

[0005] In view of the shortcomings of the prior art described above, the purpose of this utility model is to provide a wafer packaging bonding structure to solve the problem of poor uniformity of wafer surface temperature during low-temperature CVD deposition in the prior art.

[0006] To achieve the above and other related objectives, this utility model provides a wafer packaging bonding structure, comprising:

[0007] Supporting substrate;

[0008] A release layer is disposed on the upper surface of the supporting substrate;

[0009] A metal buffer layer covers the upper surface of the release layer, the release layer is used to bond the metal buffer layer to the bearing substrate, and the metal buffer layer includes a first buffer layer and a second buffer layer stacked in sequence.

[0010] A temporary bonding layer covers the upper surface of the metal buffer layer;

[0011] A wafer is located on the upper surface of the temporary bonding layer, which is used to bond the metal buffer layer to the wafer.

[0012] Preferably, the thermal conductivity of the second buffer layer is greater than 100 W / (m·K).

[0013] Preferably, the first buffer layer and the second buffer layer are made of different materials.

[0014] Preferably, the thickness of the first buffer layer is less than the thickness of the second buffer layer.

[0015] Preferably, the thickness of the first buffer layer is in the range of 800 Å to 1200 Å.

[0016] Preferably, the thickness of the second buffer layer is in the range of 1000 Å to 3000 Å.

[0017] Preferably, the thickness of the temporary bonding layer is greater than the thickness of the metal buffer layer.

[0018] Preferably, the thickness of the temporary bonding layer is in the range of 20~50 μm.

[0019] Preferably, the thickness of the release layer is less than the thickness of the metal buffer layer.

[0020] Preferably, the thickness of the release layer is in the range of 800 Å to 1200 Å.

[0021] As described above, the wafer packaging bonding structure provided by this utility model has the following beneficial effects: by adding a metal buffer layer with high thermal conductivity between the temporary bonding layer and the release layer in the wafer packaging bonding structure, heat is conducted from the release layer to the temporary bonding layer through the buffering effect of the metal buffer layer. Since the thermal conductivity of the metal buffer layer is greater than that of the temporary bonding layer and the release layer, the heat distribution of the temporary bonding layer is more uniform, which improves the uniformity of wafer temperature in the wafer packaging bonding structure, thereby improving the uniformity and stability of the thin film obtained by chemical vapor deposition. Attached Figure Description

[0022] Figure 1 The diagram shown is a schematic diagram of a wafer packaging bonding structure according to this utility model.

[0023] Explanation of reference numerals in the attached figures: 1-Substrate; 2-Release layer; 3-Metal buffer layer; 4-Temporary bonding layer; 5-Wafer. Detailed Implementation

[0024] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.

[0025] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0026] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0027] In the detailed description of the embodiments of this utility model, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this utility model. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0028] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0029] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0030] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0031] This application provides a wafer packaging bonding structure; please refer to the specific details. Figure 1 As shown, the device includes a carrier substrate 1, a release layer 2, a metal buffer layer 3, a temporary bonding layer 4, and a wafer 5. The release layer 2 is disposed on the upper surface of the carrier substrate 1. The metal buffer layer 3 covers the upper surface of the release layer 2 and includes a first buffer layer and a second buffer layer stacked sequentially. The release layer 2 is used to bond the metal buffer layer 3 to the carrier substrate 1. The temporary bonding layer 4 covers the upper surface of the metal buffer layer 3. The wafer 5 is located on the upper surface of the temporary bonding layer 4 and is used to bond the metal buffer layer 3 to the wafer 5.

[0032] Specifically, the shape, planar dimensions, and thickness of the support substrate 1 can be set according to actual needs. The material of the support substrate 1 includes glass, silicon, diamond, sapphire, silicon carbide, or other suitable substrate materials. For example, glass is used as the support substrate 1, and the thickness range of the support substrate 1 is preferably 700~1000 μm, such as 700 μm, 750 μm, 800 μm, 860 μm, 900 μm, 980 μm, and 1000 μm.

[0033] Specifically, the material, planar dimensions, thickness, and shape of wafer 5 can be selected according to actual needs. Wafer 5 includes wafers made of single-crystal silicon, silicon germanium, gallium arsenide, gallium nitride, silicon carbide, diamond, or other suitable materials. For example, silicon wafers are used as wafer 5.

[0034] Specifically, the metal buffer layer 3 is made of a material with high thermal conductivity. The thermal conductivity of the metal buffer layer 3 is higher than that of the temporary bonding layer 4 and the release layer 2. The material and thickness of the metal buffer layer 3 can be set according to actual needs. The first buffer layer covers the upper surface of the release layer 2, and the second buffer layer covers the upper surface of the first buffer layer.

[0035] In this embodiment, the thermal conductivity of the second buffer layer is greater than 100 W / (m·K).

[0036] Specifically, the material of the second buffer layer includes copper, nickel, silver, gold, aluminum, or other suitable thermally conductive materials. For example, a copper layer is used as the second buffer layer (approximately 400 W / (m·K)), or an aluminum layer is used as the second buffer layer (approximately 237 W / (m·K)).

[0037] In this embodiment, the first buffer layer and the second buffer layer are made of different materials.

[0038] Specifically, the material of the first buffer layer includes copper, nickel, silver, gold, aluminum, titanium, or other suitable high-adhesion metal materials. For example, a titanium layer is used as the first buffer layer to provide a good process platform for the subsequent formation of the second buffer layer, and at the same time to enhance the bonding force between the second buffer layer and the release layer 2.

[0039] In this embodiment of the application, the thickness of the first buffer layer is less than the thickness of the second buffer layer.

[0040] Specifically, the thickness of the first buffer layer can be set according to actual needs, and the thickness of the second buffer layer can be set according to actual needs.

[0041] In this embodiment of the application, the thickness of the first buffer layer ranges from 800 Å to 1200 Å.

[0042] For example, the thickness of the first buffer layer can be selected as 800 Å, 830 Å, 870 Å, 910 Å, 1100 Å, 1200 Å or other suitable thickness values, with 1000 Å being preferred.

[0043] In this embodiment of the application, the thickness of the second buffer layer ranges from 1000 Å to 3000 Å.

[0044] For example, the thickness of the first buffer layer can be selected as 1100 Å, 1800 Å, 1930 Å, 2200 Å, 2910 Å, 3000 Å or other suitable thickness values.

[0045] In this embodiment, the thickness of the temporary bonding layer 4 is greater than the thickness of the metal buffer layer 3.

[0046] Specifically, the material and thickness of the temporary bonding layer 4 can be selected according to actual needs. The temporary bonding layer 4 is used to bond the wafer 5 and the metal buffer layer 3. In specific implementation, the thickness of the temporary bonding layer 4 needs to be matched with the height of the adapter board that is matched with the wafer packaging bonding structure.

[0047] In this embodiment, the thickness of the temporary bonding layer 4 ranges from 20 to 50 μm.

[0048] For example, the thickness of the temporary bonding layer 4 can be selected as 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, or 50 μm.

[0049] In this embodiment, the thickness of the release layer 2 is less than the thickness of the metal buffer layer 3.

[0050] Specifically, this application takes into account that the material of the release layer 2 includes photolytic organic materials, and takes into account that the thermal conductivity of the release layer 2 is lower than that of the metal buffer layer 3, so that the thickness of the release layer 2 is set to be less than that of the metal buffer layer 3, in order to reduce the impact of the thickness of the release layer 2 on the thermal uniformity of the wafer packaging bonding structure.

[0051] In this embodiment, the thickness of the release layer 2 ranges from 800 Å to 1200 Å.

[0052] Specifically, this application takes into account not only the influence of the thermal conductivity of the release layer 2 on the thermal uniformity of the wafer packaging bonding structure, but also the fact that an excessively low thickness of the release layer 2 would reduce the adhesion between the support substrate 1 and the metal buffer layer 3. To avoid delamination between the support substrate 1 and the metal buffer layer 3, the thickness of the release layer 2 can be selected from the range of 800 Å to 1200 Å according to actual needs. For example, the thickness of the release layer 2 can be selected as 800 Å, 900 Å, 950 Å, 1000 Å, 1100 Å, or 1200 Å, with 1000 Å being preferred.

[0053] Specifically, by adding a metal buffer layer 3 between the temporary bonding layer 4 and the release layer 2 in the wafer packaging bonding structure, and the thermal conductivity of the metal buffer layer 3 being greater than that of the temporary bonding layer 4 and the release layer 2, the high thermal conductivity of the metal allows the wafer packaging bonding structure provided in this application to be applied to the low-temperature plasma enhanced chemical vapor deposition (LPECVD) thin film process. The heat conducted from the release layer 2 to the temporary bonding layer 4 through the buffering effect of the metal buffer layer 3 is more uniform, effectively improving the temperature uniformity of the wafer 5 surface on the upper surface of the temporary bonding layer 4, thereby improving the uniformity and stability of the thin film obtained by LPECVD, while also avoiding the problem of film layer peeling off the upper surface of the wafer 5.

[0054] In summary, the wafer packaging bonding structure provided by this invention adds a high thermal conductivity metal buffer layer between the temporary bonding layer and the release layer in the wafer packaging bonding structure. Heat is conducted from the release layer to the temporary bonding layer through the buffering effect of the metal buffer layer. Since the thermal conductivity of the metal buffer layer is greater than that of the temporary bonding layer and the release layer, the heat distribution of the temporary bonding layer is more uniform, improving the uniformity of the wafer temperature on the upper surface of the temporary bonding layer, thereby improving the uniformity and stability of the thin film obtained by chemical vapor deposition. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0055] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A wafer packaging bonding structure, characterized in that, include: Supporting substrate; A release layer is disposed on the upper surface of the supporting substrate; A metal buffer layer covers the upper surface of the release layer, the release layer is used to bond the metal buffer layer to the bearing substrate, and the metal buffer layer includes a first buffer layer and a second buffer layer stacked in sequence. A temporary bonding layer covers the upper surface of the metal buffer layer; A wafer is located on the upper surface of the temporary bonding layer, which is used to bond the metal buffer layer to the wafer.

2. The wafer packaging bonding structure according to claim 1, characterized in that: The thermal conductivity of the second buffer layer is greater than 100 W / (m·K).

3. The wafer packaging bonding structure according to claim 2, characterized in that: The first buffer layer and the second buffer layer are made of different materials.

4. The wafer packaging bonding structure according to claim 2, characterized in that: The thickness of the first buffer layer is less than the thickness of the second buffer layer.

5. The wafer packaging bonding structure according to claim 4, characterized in that: The thickness of the first buffer layer ranges from 800 Å to 1200 Å.

6. The wafer packaging bonding structure according to claim 4, characterized in that: The thickness of the second buffer layer ranges from 1000 Å to 3000 Å.

7. The wafer packaging bonding structure according to claim 1, characterized in that: The thickness of the temporary bonding layer is greater than the thickness of the metal buffer layer.

8. The wafer packaging bonding structure according to claim 7, characterized in that: The thickness of the temporary bonding layer ranges from 20 to 50 μm.

9. The wafer packaging bonding structure according to claim 1, characterized in that: The thickness of the release layer is less than the thickness of the metal buffer layer.

10. The wafer packaging bonding structure according to claim 9, characterized in that: The thickness of the release layer ranges from 800 Å to 1200 Å.

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