A general-purpose circuit board interface detection circuit

Abstract

This utility model discloses a universal circuit board interface testing circuit, including a testing module. Its voltage divider unit consists of resistors R1 and R2, the filtering unit includes capacitors C1 and C2, the signal amplification unit is a programmable gain amplifier, the analog-to-digital converter unit is connected to the amplifier output, and the main control unit is connected to the amplifier gain control terminal, the analog-to-digital converter unit, and the test port of the board under test. The main control unit can determine the over-range state and adjust the amplification factor, and receive digital signals to obtain complete data by combining the pin logic levels. This design adapts to various interfaces through programmable gain adjustment and wide-range voltage divider without requiring hardware replacement; combined with filtering and adaptive gain adjustment, it filters out noise and avoids saturation, with weak signal errors ≤ ±2%; the main control unit's automatic operation improves efficiency, and the use of high-impedance voltage divider structures reduces electromagnetic interference.

Description

Technical Field

[0001] This utility model belongs to the field of circuit board testing technology, specifically a general-purpose circuit board interface testing circuit. Background Technology

[0002] With the rapid iteration of electronic information technology, the integration of circuit boards has increased exponentially, and interface types have expanded towards multiple protocols and high bandwidth (covering mainstream types such as TTL, RS232, RS485, CAN, and Ethernet). Due to significant differences in signal level threshold ranges (e.g., TTL single-ended level 0-5V, RS485 differential level ±2-±6V), logic level definitions (e.g., RS232 negative logic "1" corresponds to -3~-15V), and signal transmission protocols among different interfaces, most current circuit board interface testing equipment adopts a "dedicated design architecture," which generally suffers from the following technical defects: A single testing device typically supports testing requirements for only 2-3 specific interfaces. Its hardware circuit signal conditioning module and firmware driver are highly bound to the target interface. When facing new interfaces (such as USB4 and PCIe5.0), it is necessary to reconstruct the voltage divider network, design the signal matching circuit, and iterate the driver, resulting in poor equipment scalability and a long development cycle.

[0003] Traditional detection circuits lack effective noise suppression mechanisms (such as differential filtering and electromagnetic shielding design), making them unable to withstand common-mode interference and crosstalk in industrial environments. Furthermore, they lack adaptive gain adjustment algorithms based on signal amplitude. When detecting weak signals (such as low-level amplitude <0.5V and signal-to-noise ratio <10dB), they are prone to amplitude deviations exceeding ±5% and timing jitter >10ns, failing to meet the detection requirements of precision circuits.

[0004] When switching between different testing interfaces, manual intervention is required to replace the voltage divider resistor module, switch the operational amplifier gain level, and calibrate the reference voltage. This not only extends the testing preparation cycle (the time for a single interface switch is ≥10 minutes), but also increases the false judgment rate to more than 3% due to manual parameter configuration errors, significantly reducing the efficiency of batch testing.

[0005] Based on the aforementioned technical pain points, the development of a universal circuit board interface testing circuit with multi-interface adaptation capabilities has become an urgent industry need. This circuit needs to systematically solve the core problems of existing technologies in terms of interface compatibility, testing accuracy, and operational efficiency through modular architecture design (such as pluggable interface conditioning modules and standardized signal acquisition units) and adaptive signal conditioning mechanisms (including real-time noise suppression and dynamic gain adjustment algorithms). Utility Model Content

[0006] The purpose of this invention is to provide a universal circuit board interface testing circuit to solve the problems of limited compatibility, low testing accuracy, and cumbersome operation of existing circuit board interface testing equipment mentioned in the background art.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows: A general-purpose circuit board interface testing circuit includes a testing module connected to the interface of the circuit board under test. The testing module includes a voltage divider unit, a filter unit, a signal amplification unit, an analog-to-digital conversion unit, and a main control unit. The voltage divider unit includes resistors R1 and R2. One end of resistor R1 is connected to the pin under test on the circuit board under test, and the other end of resistor R1 is connected to one end of resistor R2 and the input terminal of the filter unit. The other end of resistor R2 is grounded. The filtering unit includes capacitors C1 and C2. One end of capacitor C1 is connected to the connection point of resistors R1 and R2, and the other end of capacitor C1 is grounded. One end of capacitor C2 is connected to the output of the signal amplification unit, and the other end of capacitor C2 is grounded. The signal amplification unit is a programmable gain amplifier, and its input is connected to the output of the filtering unit to acquire the signal level change of the pin under test. The input terminal of the analog-to-digital converter is connected to the output terminal of the programmable gain amplifier to convert analog signals into digital signals; The main control unit is connected to the gain control terminal of the programmable gain amplifier, the output terminal of the analog-to-digital converter, and the test port of the circuit board under test. The main control unit is used to determine whether the circuit is in an over-range state based on the output of the programmable gain amplifier, and adjust the amplification factor of the programmable gain amplifier through the gain control terminal; it receives the digital signal output by the analog-to-digital converter and combines it with the logic level of the pin under test obtained from the test port to obtain the complete data information of the pin under test.

[0008] According to the above technical solution, the resistance values ​​of resistors R1 and R2 are in the megaohm range.

[0009] According to the above technical solution, the capacitance values ​​of capacitors C1 and C2 are in the pF range.

[0010] According to the above technical solution, the voltage division ratio of resistor R1 to resistor R2 is 9:1.

[0011] According to the above technical solution, the detection module also includes an anti-aliasing filter circuit, which is connected in series between the output of the programmable gain amplifier and the input of the analog-to-digital conversion unit to suppress high-frequency interference signals and avoid aliasing distortion during analog-to-digital conversion.

[0012] According to the above technical solution, the anti-aliasing filter circuit includes a signal conditioning chip U1, resistors R3, R4, and R5, and capacitors C3 and C4. One end of resistor R4 is connected to the output of the programmable gain amplifier, and the other end of resistor R4 is connected to pin 2 of signal conditioning chip U1, capacitor C3, and one end of resistor R3; the other end of capacitor C3 is grounded. Pin 5 of the signal conditioning chip U1 is connected to the other end of resistor R3, one end of capacitor C4, and the input terminal of the analog-to-digital converter unit, respectively. The other end of resistor R5 and the other end of capacitor C4 are grounded together. The signal conditioning chip U1 is used to linearly condition the signal output by the programmable gain amplifier. Resistors R3 and R4, together with capacitor C3, form an input stage anti-aliasing filter, and resistor R5, together with capacitor C4, form an output stage anti-aliasing filter, which together suppresses the high-frequency signal of the Nyquist frequency of the super analog-to-digital converter unit.

[0013] According to the above technical solution, the resistance values ​​of resistors R3, R4, and R5 are all 10KΩ, and the capacitance values ​​of capacitors C3 and C4 are both 1nF.

[0014] According to the above technical solution, it also includes a low-noise, high PSRR linear regulated power supply to provide stable power to the detection module, and a low-noise, low-temperature drift voltage reference to provide a reference voltage for the analog-to-digital conversion unit; the linear regulated power supply is shielded with a metal shield during use to reduce external electromagnetic interference; the low-noise, low-temperature drift voltage reference is model REF5025, and its output terminal is connected to the reference voltage input terminal of the analog-to-digital conversion unit to ensure the stability of the voltage reference for analog-to-digital conversion.

[0015] Furthermore, the amplification factor adjustment range of the programmable gain amplifier is adapted to the signal level range of the interface of the circuit board under test.

[0016] Compared with the prior art, the present invention has the following beneficial effects: In this invention, a wide range of signal voltage division is achieved through a voltage divider unit. Combined with a programmable gain amplifier (signal amplification unit) and a main control unit for dynamic adjustment of the amplification factor, it can be adapted to a variety of mainstream interfaces without the need to reconstruct the voltage divider network, replace the amplification module, or iterate the driver program. This solves the pain points of traditional detection equipment, such as specialized design, support for only 2-3 interfaces, and poor expandability, and significantly reduces the hardware cost and R&D cycle of interface switching.

[0017] The filtering unit uses pF-level capacitors C1 (to filter out high-frequency noise in the voltage divider signal) and C2 (to filter out post-stage noise in the amplifier output signal) to form a dual-layer noise suppression structure. On the other hand, a megohm-level high-impedance voltage divider structure is used to reduce signal shunting and external interference coupling. Combined with the short-distance differential trace design during PCB routing, it can effectively resist common-mode interference and crosstalk in the industrial environment, ensuring the stability and reliability of the test results in complex electromagnetic environments. Attached Figure Description

[0018] Figure 1 This is a block diagram of the circuit implementation of this utility model; Figure 2 This is a circuit block diagram illustrating the application of this utility model. Figure 3 This is a circuit diagram of the anti-aliasing filter of this utility model; Figure 4 This is the circuit diagram of the voltage divider unit of this utility model. Detailed Implementation

[0019] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model. Example

[0020] like Figure 1 As shown, a general-purpose circuit board interface testing circuit includes a testing module connected to the interface of the circuit board under test. The testing module includes a voltage divider unit, a filtering unit, a signal amplification unit, an analog-to-digital conversion unit, and a main control unit. like Figure 4 As shown, the voltage divider unit includes resistors R1 and R2. One end of resistor R1 is connected to the pin under test on the circuit board under test, and the other end of resistor R1 is connected to one end of resistor R2 and the input terminal of the filter unit. The other end of resistor R2 is grounded. The filtering unit includes capacitors C1 and C2. One end of capacitor C1 is connected to the connection point of resistors R1 and R2, and the other end of capacitor C1 is grounded. One end of capacitor C2 is connected to the output terminal of the signal amplification unit, and the other end of capacitor C2 is grounded. The signal amplification unit is a programmable gain amplifier, whose input is connected to the output of the filtering unit, and is used to acquire the signal level change of the pin under test. The input terminal of the analog-to-digital converter is connected to the output terminal of the programmable gain amplifier to convert analog signals into digital signals; like Figure 2As shown, the main control unit is connected to the gain control terminal of the programmable gain amplifier, the output terminal of the analog-to-digital converter, and the test port of the circuit board under test. The main control unit is used to determine whether the circuit is in an over-range state based on the output of the programmable gain amplifier, and adjust the amplification factor of the programmable gain amplifier through the gain control terminal; it receives the digital signal output by the analog-to-digital converter, and combines it with the logic level of the pin under test obtained from the test port to obtain the complete data information of the pin under test.

[0021] In this invention, a wide range of signal voltage division is achieved through a voltage divider unit. Combined with a programmable gain amplifier (signal amplification unit) and a main control unit for dynamic adjustment of the amplification factor, it can be adapted to a variety of mainstream interfaces without the need to reconstruct the voltage divider network, replace the amplification module, or iterate the driver program. This solves the pain points of traditional detection equipment, such as specialized design, support for only 2-3 interfaces, and poor expandability, and significantly reduces the hardware cost and R&D cycle of interface switching.

[0022] The filtering unit uses pF-level capacitors C1 (to filter out high-frequency noise in the voltage divider signal) and C2 (to filter out post-stage noise in the amplifier output signal) to form a dual-layer noise suppression structure. On the other hand, a megohm-level high-impedance voltage divider structure is used to reduce signal shunting and external interference coupling. Combined with the short-distance differential trace design during PCB routing, it can effectively resist common-mode interference and crosstalk in the industrial environment, ensuring the stability and reliability of the test results in complex electromagnetic environments. Example

[0023] This embodiment is a further refinement of Embodiment 1. This utility model provides a universal circuit board interface detection circuit. Through modular design and collaborative control, it achieves automatic identification and high-precision detection of various interface signals, significantly improving compatibility and anti-interference capabilities. The specific implementation of this circuit will be described in detail below with reference to the accompanying drawings and embodiments.

[0024] The circuit in this invention adopts a modular architecture, mainly comprising two parts: a detection module and an auxiliary protection circuit. The detection module comprises, in sequence, a voltage divider unit, a filter unit, a programmable gain amplifier (PGA), an anti-aliasing filter circuit, an analog-to-digital converter (ADC), and a main control unit. The units are connected via short-distance differential traces. The voltage divider and filter units are equipped with metal shielding structures to suppress electromagnetic interference.

[0025] The auxiliary protection circuit includes a low-noise, high power supply rejection ratio (PSRR) linear regulated power supply and a low-temperature drift voltage reference source, which provide stable power supply and ADC reference voltage for the detection module, respectively, ensuring reliability in complex industrial environments.

[0026] This circuit supports the detection of multiple interface signals, including TTL (0–5V), RS232 (-15V–+15V), RS485 (±2V–±6V), and CAN (±1.5V–±3.5V). Interface switching can be achieved through software configuration of the main control unit without changing the hardware.

[0027] The voltage divider unit attenuates higher voltage interface signals to a range that subsequent circuits can handle. It employs a resistor divider structure, where R1 = 9MΩ and R2 = 1MΩ, both being ±1% precision metal film resistors, with a voltage division ratio of 9:1. The output signal satisfies the following relationship:

[0028] This structure achieves voltage attenuation while maintaining high input impedance (≥10MΩ), avoiding load impact on the circuit under test.

[0029] The filtering unit is used to suppress high-frequency noise and improve signal quality. It employs a two-stage capacitor filter structure: C1 = 100pF, located at the voltage divider output terminal to ground, to filter out high-frequency interference introduced during the voltage division process; C2 = 200pF, located at the PGA output terminal to ground, to suppress amplifier output noise. All capacitors are made of NP0 material, exhibiting low temperature drift, stable performance, and excellent suppression of high-frequency noise, while providing minimal attenuation of low-frequency signals.

[0030] The signal amplification unit employs a programmable gain amplifier (PGA), whose gain can be dynamically adjusted by the main control unit via an SPI interface between 1 / 16 and 16 times. By monitoring the ADC output in real time, the main control unit can automatically adjust the gain to ensure the signal amplitude is within the optimal sampling range of the ADC, avoiding measurement errors caused by weak or saturated signals.

[0031] like Figure 3 As shown, the anti-aliasing filter circuit is a key signal conditioning unit located between the programmable gain amplifier (PGA) and the analog-to-digital converter (ADC). Its core function is to filter out high-frequency components in the signal that are higher than the Nyquist frequency of the ADC, preventing spectral aliasing during sampling and thus ensuring the accuracy of the analog-to-digital conversion results.

[0032] This circuit employs an active filter architecture based on a low-noise operational amplifier (model: OPA2340), specifically implemented as an improved multi-stage low-pass filter structure. Its circuit configuration and connections are as follows: Operational amplifier U1 (OPA2340) serves as the core conditioning device. Resistors R3 (10 kΩ) and R4 (10 kΩ), along with capacitor C3 (1 nF), form the RC low-pass filter network for the input stage. One end of R4 is connected to the output of the PGA, and the other end is connected to pin 2 of operational amplifier U1, one end of capacitor C3, and one end of resistor R3. The other end of capacitor C3 is grounded.

[0033] Resistor R3 serves a dual function of feedback and filtering in this circuit. Its other end is connected to the output terminal (pin 5) of operational amplifier U1, forming a voltage follower structure. This is intended to utilize the high input impedance and low output impedance characteristics of the op-amp to achieve good impedance transformation and isolation, effectively driving the subsequent ADC load while avoiding mutual interference between the preceding and following circuits.

[0034] In the output stage, capacitor C4 (1nF) and resistor R5 (10kΩ) form an additional passive RC low-pass filter network. The output of operational amplifier U1 is connected to one end of capacitor C4 and one end of resistor R5. The other end of resistor R5 and the other end of capacitor C4 are connected to the analog input terminal (AIN0) of the ADC and grounded at this node, forming the final stage of filtering for the ADC input signal.

[0035] The transfer function and frequency characteristics of this filter network have been carefully designed. Both the input stage (R4, C3) and the output stage (R5, C4) are set with the same cutoff frequency of approximately 15.9 kHz. The combination of these two filtering stages reduces the overall -3 dB cutoff frequency of the anti-aliasing filter circuit to approximately 11 kHz. This frequency is significantly lower than the 12.5 kHz Nyquist frequency corresponding to the 250 kHz sampling rate set for the ADC in this circuit, thus providing ample safety margin to ensure aliasing-free sampling.

[0036] The analog-to-digital conversion uses a 16-bit ADC chip, ADS1115, with a sampling rate of 860 SPS. The reference voltage is provided by REF5025, and its output is 2.5V. The noise is less than 10μVrms, and the temperature drift is ≤5ppm / ℃. The ADC resolution is 0.1526mV / LSB, enabling high-precision signal conversion with a detection error of no more than ±0.5%. For example, when the ADC output value exceeds 90% of its full-scale range (±2.5V) (i.e., ±2.25V), it is determined to be over-range; when the output value is less than 10% of the full-scale range (i.e., ±0.25V), it is determined to be under-range.

[0037] When the range is exceeded, the PGA gain is reduced to half of the current multiple (minimum 1 / 16 times); when the range is under-ranged, the gain is increased to twice the current multiple (maximum 16 times), and after adjustment, a 10μs delay is applied before resampling for verification.

[0038] The main control unit uses an STM32F103C8T6 microcontroller to coordinate the work of various modules, including PGA gain control, ADC data reading, voltage calculation, and logic state judgment. This unit identifies the interface type and outputs the detection results by restoring the actual voltage value, and supports multi-channel parallel detection.

[0039] The auxiliary protection circuit includes a linear regulated power supply LT1763 and a voltage reference REF5025. The LT1763 provides a 3.3V regulated output with a PSRR exceeding 80dB and output noise below 20μVrms; the REF5025 provides a highly stable 2.5V reference voltage with low temperature drift and high long-term stability. Together, they provide clean and stable operating conditions for the detection circuit.

[0040] The circuit described in this utility model has the following significant advantages: First, it is widely compatible with a variety of common interface signals and can be quickly switched via software, making it easy to operate; second, it has high detection accuracy, with weak signal detection error not exceeding ±2% and strong signal detection error not exceeding ±0.5%; at the same time, it has excellent anti-interference performance and can maintain stable measurement even in a field strength environment of 30V / m; in addition, it supports multi-channel parallel detection, which can greatly improve the efficiency of batch detection.

[0041] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0042] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A general-purpose circuit board interface detection circuit, characterized in that: It includes a detection module that connects to the interface of the circuit board under test. The detection module includes a voltage divider unit, a filter unit, a signal amplification unit, an analog-to-digital conversion unit, and a main control unit. The voltage divider unit includes resistors R1 and R2. One end of resistor R1 is connected to the pin under test on the circuit board under test, and the other end of resistor R1 is connected to one end of resistor R2 and the input terminal of the filter unit. The other end of resistor R2 is grounded. The filtering unit includes capacitors C1 and C2. One end of capacitor C1 is connected to the connection point of resistors R1 and R2, and the other end of capacitor C1 is grounded. One end of capacitor C2 is connected to the output of the signal amplification unit, and the other end of capacitor C2 is grounded. The signal amplification unit is a programmable gain amplifier, and its input is connected to the output of the filtering unit to acquire the signal level change of the pin under test. The input terminal of the analog-to-digital converter is connected to the output terminal of the programmable gain amplifier to convert analog signals into digital signals; The main control unit is connected to the gain control terminal of the programmable gain amplifier, the output terminal of the analog-to-digital converter, and the test port of the circuit board under test. The main control unit is used to determine whether the output of the programmable gain amplifier is in an over-range state, and adjust the amplification factor of the programmable gain amplifier through the gain control terminal. The system receives the digital signal output from the analog-to-digital converter unit and combines it with the logic level of the pin under test obtained from the test port to obtain the complete data information of the pin under test.

2. The universal circuit board interface detection circuit of claim 1, wherein: The resistance values ​​of resistors R1 and R2 are in the megaohm range.

3. The universal circuit board interface detection circuit of claim 1, wherein: The capacitance values ​​of capacitors C1 and C2 are in the pF range.

4. The universal circuit board interface detection circuit of claim 1, wherein: The voltage division ratio of resistor R1 to resistor R2 is 9:

1.

5. The universal circuit board interface detection circuit of claim 1, wherein: The detection module also includes an anti-aliasing filter circuit, which is connected in series between the output of the programmable gain amplifier and the input of the analog-to-digital converter unit to suppress high-frequency interference signals and avoid aliasing distortion during analog-to-digital conversion.

6. A universal circuit board interface detection circuit according to claim 5, wherein: The anti-aliasing filter circuit includes signal conditioning chip U1, resistors R3, R4, and R5, and capacitors C3 and C4. One end of resistor R4 is connected to the output of the programmable gain amplifier, and the other end of resistor R4 is connected to pin 2 of signal conditioning chip U1, capacitor C3, and one end of resistor R3; the other end of capacitor C3 is grounded. Pin 5 of the signal conditioning chip U1 is connected to the other end of resistor R3, one end of capacitor C4, and the input terminal of the analog-to-digital converter unit, respectively. The other end of resistor R5 and the other end of capacitor C4 are grounded together. The signal conditioning chip U1 is used to linearly condition the signal output by the programmable gain amplifier. Resistors R3 and R4, together with capacitor C3, form an input stage anti-aliasing filter, and resistor R5, together with capacitor C4, form an output stage anti-aliasing filter, which together suppresses the high-frequency signal of the Nyquist frequency of the super analog-to-digital converter unit.

7. A universal circuit board interface detection circuit according to claim 6, wherein: Resistors R3, R4, and R5 all have a resistance of 10KΩ, and capacitors C3 and C4 both have a capacitance of 1nF.

8. A universal circuit board interface detection circuit according to claim 7, wherein: It also includes a low-noise, high PSRR linear regulated power supply to provide stable power to the detection module, and a low-noise, low-temperature drift voltage reference to provide a reference voltage for the analog-to-digital conversion unit. The linear regulated power supply is shielded with a metal shield during use to reduce external electromagnetic interference. The low-noise, low-temperature drift voltage reference is model REF5025, and its output is connected to the reference voltage input of the analog-to-digital conversion unit to ensure the stability of the voltage reference for analog-to-digital conversion.

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