Chip testing device and system based on FPGA and MCU collaborative control

Abstract

This utility model provides a chip testing device and system based on FPGA and MCU collaborative control. The testing device includes a chip socket for mounting the chip under test; an FPGA control module connected to the chip for performing functional and / or performance testing on the chip; an MCU control module connected to the chip for performing voltage calibration and OTP code programming on the chip; and a power supply control circuit for supplying power to the chip. This chip testing device and system based on FPGA and MCU collaborative control integrates the FPGA control module, MCU control module, and power supply control circuit into a single unit. Through coordinated testing equipment, it achieves full automation from basic parameter testing to advanced functional testing, greatly improving testing efficiency.

Description

Technical Field

[0001] This utility model relates to the field of chip testing, and in particular to a chip testing device and system based on FPGA and MCU collaborative control. Background Technology

[0002] In the chip mass production process, final testing (FT) is a critical step to ensure that chip performance, functionality, and quality meet design specifications, but the FT testing process is particularly cumbersome. Traditional FT testing solutions rely on different testing equipment, resulting in difficulties in debugging, low automation, and inefficient test process integration, leading to low chip testing efficiency. There is an urgent need for an innovative, highly integrated, automated, and easily debuggable dedicated testing solution. Utility Model Content

[0003] This invention provides a chip testing device and system based on FPGA and MCU collaborative control, which solves the technical problem of low chip testing efficiency in the prior art.

[0004] On the one hand, this utility model provides the following technical solution: A chip testing device based on FPGA and MCU collaborative control, comprising: Chip socket, used to install the chip under test; An FPGA control module, which is connected to the chip, is used to perform functional and / or performance testing on the chip; An MCU control module, which is connected to the chip, is used to perform voltage calibration and OTP code programming operations on the chip; A power supply control circuit is provided to supply power to the chip.

[0005] Optionally, the chip includes an RGMII interface; the FPGA control module is used to perform functional and / or performance tests on the RGMII interface.

[0006] Optionally, the MCU control module includes an SPI interface, and the MCU control module connects to the chip through the SPI interface.

[0007] Optionally, the MCU control module further includes a communication unit, through which the MCU control module interacts with the host computer.

[0008] Optionally, the communication unit includes a USB interface and a Wi-Fi module, and the communication unit can interact with the host computer through the USB interface and / or the Wi-Fi module.

[0009] Optionally, the power supply control circuit includes a relay, the control terminal of which is connected to the test machine, and the controlled terminal of which is connected to the power supply pin of the chip.

[0010] Optionally, the testing device further includes a test bench interface, which is used to connect all pins of the chip, except those connected to the FPGA control module, MCU control module, and power supply control circuit, to the test bench.

[0011] Optionally, the testing device further includes a recording module for recording test results.

[0012] On the other hand, this utility model also provides the following technical solution: A chip testing system based on FPGA and MCU collaborative control is characterized in that the testing system includes the testing device and testing machine as described above; the testing machine is used to control the FPGA control module, the MCU control module, and the power supply control circuit.

[0013] Optionally, the testing system may also include a host computer.

[0014] One or more technical solutions provided by this utility model have at least the following technical effects or advantages: This utility model provides a chip testing device and system based on FPGA and MCU collaborative control. By integrating the FPGA control module, MCU control module and power supply control circuit into one unit, and through the coordination of the testing machine, it realizes full-process automation from basic parameter testing to advanced function testing, which greatly improves testing efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a chip testing device in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a chip testing system in one embodiment of this application; Figure 3 This is a schematic flowchart of a chip testing method in one embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0019] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0020] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0021] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more.

[0022] Before providing a detailed description of the solution in this application, the terms used in this application are explained as follows: FPGA: A Field-Programmable Gate Array (FPGA) is a semiconductor device whose circuit functionality can be reconfigured post-manufacturing using hardware description languages ​​such as Verilog or VHDL. It consists of programmable logic blocks, interconnect resources, and configurable I / O units, enabling the implementation of arbitrary digital circuits, from simple logic gates to complex processor systems. Unlike the fixed circuitry of traditional ASICs, FPGAs allow users to flexibly reconfigure hardware functions by programming configuration files, combining the high efficiency of hardware parallel processing with the flexibility of software programmability. They are widely used in prototyping, communication acceleration, industrial control, and embedded systems.

[0023] RGMII Interface: RGMII (Reduced Gigabit Media Independent Interface) is an interface standard widely used in Gigabit Ethernet communication. It achieves a data transmission rate of 1Gbps by using a combination of data, control, and clock signals at a 125MHz clock frequency and employing dual-edge (rising and falling edge) sampling technology to transmit 4 bits of data per clock cycle. Its biggest advantage lies in reducing the 16 data and control signals of the traditional GMII interface to 12, significantly reducing PCB routing complexity and cost. It is one of the most mainstream interfaces connecting the Gigabit Ethernet MAC (Media Access Controller) and PHY (Physical Layer Interface Chip).

[0024] Final chip testing (FT) refers to the final comprehensive electrical functional and performance testing performed after the wafer has been diced and packaged into individual chips. Its purpose is to verify that no defects were introduced during the packaging process and to ensure that each chip meets design specifications in terms of speed, power consumption, functionality, and reliability.

[0025] SPI Interface: SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous serial communication bus protocol widely used for short-distance communication between microcontrollers and peripheral chips (such as sensors, memory, ADCs, etc.). It adopts a master-slave architecture, typically containing one master device and one or more slave devices, communicating via four basic signal lines: Master Output Slave Input (MOSI), Master Input Slave Output (MISO), Serial Clock (SCLK), and Slave Select (SS / CS). SPI's outstanding advantages lie in its simple protocol, high data transfer rate, and low hardware implementation cost. However, due to the lack of hardware flow control and acknowledgment mechanisms, its reliability highly depends on the stability of the system design. COM: Serial Communication Port, is an interface used for data communication, allowing data exchange and information transmission between electronic devices. This interface is very common in computers and other digital devices and is a key component for implementing inter-device communication.

[0026] OTP code programming: OTP code programming refers to the process of writing programs or data into a "one-time programmable" memory in a single operation. Before programming, the fuses or antifuse cells inside the OTP memory are in an initial state. By applying high voltage or other programming operations, their physical characteristics undergo irreversible changes, thus permanently storing the information. Once programming is complete, the data cannot be erased or modified. This characteristic ensures extremely high code security and reliability, making it widely used in cost-sensitive consumer electronics and IoT device key storage where firmware upgrades are not required, as well as in industrial and automotive electronics fields where firmware tamper-proofing is required.

[0027] Chip OS testing: Chip OS testing refers to the functional, performance, and stability verification of the integrated operating system (usually lightweight firmware or a real-time operating system, such as an RTOS) during the chip design process. This testing is performed on actual hardware after chip tape-out and aims to ensure that the operating system can correctly schedule and manage various chip resources (such as CPU cores, memory, peripherals, and interrupts) and work flawlessly with the underlying hardware. As a crucial bridge connecting hardware and application software, chip OS testing is a vital step in verifying the overall functional integrity of the chip, discovering potential defects between hardware and firmware, and ensuring the reliability of the final product.

[0028] In the chip mass production process, final testing (FT) is a critical step to ensure that the chip's performance, functionality, and quality meet design specifications. For complex chips like the AXS9601 (a dedicated control chip designed by Aisen Technology for LED display control systems, mainly used to drive and manage the display effects of LED screens), which integrates multiple interfaces (such as RGMII and SPI) and functional modules (such as those requiring voltage calibration and OTP programming), the FT testing process is particularly cumbersome.

[0029] Traditional testing methods typically have the following problems: 1. Discrete test systems: Different test items (such as DC parameter testing, high-speed interface testing, calibration and programming) may require different test equipment, resulting in a lack of smooth connection of the test process, low degree of automation, and low test efficiency.

[0030] 2. Debugging difficulties: During testing, engineers find it difficult to obtain detailed status and data from the test board in real time. When tests fail, troubleshooting and debugging are time-consuming and labor-intensive.

[0031] 3. Lack of flexibility: The test logic is fixed in the test equipment. If the test vector or process needs to be adjusted, the modification cost is high and the cycle is long.

[0032] 4. High-speed interface testing challenges: Testing high-speed interfaces such as RGMII has strict timing requirements, and general-purpose testing equipment is difficult to meet the needs of high cost-effectiveness and high efficiency testing. Therefore, there is an urgent need in the field for a highly integrated, automated and easy-to-debug dedicated test system to efficiently and reliably complete the FT test of complex chips such as the AXS9601.

[0033] On the one hand, such as Figure 1 As shown, this application embodiment provides a chip testing device based on FPGA and MCU collaborative control, including: Chip socket, used to install the chip under test; An FPGA control module is connected to the chip and is used to perform functional and / or performance testing on the chip. The MCU control module is connected to the chip and is used for voltage calibration and OTP code programming operations on the chip. The power supply control circuit is used to supply power to the chip.

[0034] This utility model provides a chip testing device based on FPGA and MCU collaborative control. By integrating the FPGA control module, MCU control module, and power supply control circuit into one unit, and through the coordination of the testing machine, it realizes full-process automation from basic parameter testing to advanced function testing, which greatly improves testing efficiency.

[0035] In one embodiment, specifically as follows Figure 2 As shown, the chip includes an RGMII interface; the FPGA control module is used to perform functional and / or performance testing on the RGMII interface. Preferably, the FPGA is a Xilinx XC6SLX45 FPGA chip, mainly used in embedded, industrial and consumer applications, based on a 45nm process, providing medium to high density logic resources and programmability.

[0036] In one embodiment, the MCU control module includes an SPI interface, through which the MCU control module connects to the chip. Preferably, the MCU uses the ESP32-S2, a highly integrated, cost-effective, low-power, and security-focused single-core Wi-Fi microcontroller chip from Espressif Systems, suitable for various application scenarios such as the Internet of Things, smart homes, and wearable devices.

[0037] In one embodiment, the MCU control module further includes a communication unit, through which the MCU control module interacts with the host computer. Preferably, the communication unit includes a USB interface and a Wi-Fi module. The communication unit can interact with the host computer through the USB interface and / or the Wi-Fi module, enabling the host computer to exchange data with the test board via a wired USB connection or a wireless Wi-Fi connection, thereby realizing command issuance, data readback, and real-time debugging.

[0038] In one embodiment, the power supply control circuit includes a relay. The control terminal of the relay is connected to the test equipment, and the controlled terminal of the relay is connected to the power supply pin of the chip, thereby enabling the test equipment to precisely manage the chip's power supply. Preferably, the power supply control circuit is a set of relays.

[0039] In one embodiment, the testing apparatus further includes a test bench interface, which connects all pins of the chip, except those connected to the FPGA control module, MCU control module, and power supply control circuit, to the test bench for basic parameter testing such as open circuit / short circuit. Preferably, the test bench interface is a series of connectors.

[0040] In one embodiment, the testing apparatus further includes a recording module for recording test results.

[0041] In one embodiment, the testing apparatus is integrated onto a test board.

[0042] In one embodiment, the chip tested was the AXS9601.

[0043] In one embodiment, the test method based on the above-described test apparatus, such as... Figure 3 As shown, it includes the following steps: Initialization and OS testing: The test equipment disconnects the chip by controlling the relay in the power supply control circuit, and performs open / short circuit tests on each pin of the chip through the test equipment interface.

[0044] Calibration and programming stage: After the OS test is passed, the test machine sends a start command to the MCU control module through its interface; after receiving the command, the MCU control module performs voltage calibration on the chip through the SPI interface, and programs the preset OTP code after calibration; after programming is completed, the MCU control module resets the chip and sends a "MCU test completed" signal back to the test machine through the SPI interface.

[0045] Interface testing phase: After receiving the "MCU test complete" signal, the test machine sends a test command to the FPGA control module; the FPGA control module begins to test the chip's RGMII interface; after the test is completed, the FPGA control module sends back the "FPGA test complete" signal to the test machine.

[0046] Data monitoring and debugging: Throughout the testing process, engineers can monitor the test status in real time, read detailed test logs and data, and perform online debugging through host computer software connected to the dual-mode communication unit (USB or Wi-Fi).

[0047] The testing apparatus provided in this application has the following advantages: High integration and automation: It integrates high-speed interface testing (FPGA-based) and complex logic control (MCU-based) into one unit. Through the coordination of test equipment, it realizes full-process automation from basic parameter testing to advanced function testing, which greatly improves testing efficiency.

[0048] Optimized architecture and superior performance: Leveraging the parallel processing and timing controllability of FPGAs, high-speed RGMII interface testing is completed efficiently and reliably; utilizing the flexibility and ease of programming of MCUs, complex calibration and programming processes are handled. The two work together to maximize resource utilization.

[0049] Powerful debugging capabilities: The innovative dual-mode (USB + Wi-Fi) communication design provides engineers with great convenience. Wired connections are stable, while wireless connections are flexible, supporting remote real-time debugging and significantly reducing troubleshooting time.

[0050] Flexibility and scalability: Both the FPGA logic and the MCU software are reconfigurable / upgradeable, enabling this test board to easily adapt to changes in test requirements or updates to test vectors, resulting in a long lifespan.

[0051] High test reliability: The chip is powered directly by the test machine via a relay, ensuring the purity of the power supply domain and the accuracy of basic parameter tests.

[0052] On the other hand, such as Figure 3 As shown, this utility model embodiment also provides a chip testing system based on FPGA and MCU collaborative control, including: The testing system includes the testing device and testing machine as described above; the testing machine is used to control the FPGA control module, MCU control module, and power supply control circuit.

[0053] The specific functions of the testing device can be found in the various embodiments of the testing device in this application, and will not be repeated here.

[0054] In one embodiment, the testing system further includes a host computer.

[0055] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0056] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0057] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0058] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0059] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0060] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0061] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A chip testing device based on FPGA and MCU cooperative control, characterized in that, include: Chip socket, used to install the chip under test; An FPGA control module, which is connected to the chip, is used to perform functional and / or performance testing on the chip; An MCU control module, which is connected to the chip, is used to perform voltage calibration and OTP code programming operations on the chip; A power supply control circuit is provided to supply power to the chip.

2. The test device of claim 1, wherein, The chip includes an RGMII interface; the FPGA control module is used to perform functional and / or performance tests on the RGMII interface.

3. The test device of claim 1, wherein, The MCU control module includes an SPI interface, and the MCU control module is connected to the chip through the SPI interface.

4. The test device of claim 1, wherein, The MCU control module also includes a communication unit, through which the MCU control module interacts with the host computer.

5. The test device of claim 4, wherein, The communication unit includes a USB interface and a Wi-Fi module, and the communication unit can interact with the host computer through the USB interface and / or the Wi-Fi module.

6. The test device of claim 1, wherein, The power supply control circuit includes a relay, the control terminal of which is connected to the test machine, and the controlled terminal of which is connected to the power supply pin of the chip.

7. The test device of claim 1, wherein, The testing device also includes a test bench interface, which is used to connect all pins of the chip, except those connected to the FPGA control module, the MCU control module, and the power supply control circuit, to the test bench.

8. The test device of claim 1, wherein, The testing device also includes a recording module, which is used to record the test results.

9. A chip test system based on FPGA and MCU cooperative control, characterized in that, The testing system includes the testing device and testing machine as described in any one of claims 1-8; the testing machine is used to control the FPGA control module, the MCU control module, and the power supply control circuit.

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