A delay circuit and a graphics card
By designing a two-stage delay circuit and a clamping diode combination, the delay requirement between the power signal and the reset signal of the graphics card chip was solved, the timing requirements of the graphics card were met, and the reset signal delay requirement of non-standard graphics cards was satisfied.
Patent Information
- Application Number
- CN202522633448.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-11
- Publication Date
- 2026-11-06
- Estimated Expiration
- 2035-12-11
AI Technical Summary
Existing technology cannot meet the large time delay requirements between the power signal and the reset signal of some graphics card chips, and conventional delay circuits cannot meet the timing requirements of non-standard graphics cards.
A delay circuit including a power supply, a first delay unit, a second delay unit, and a switching unit is designed. By combining two-stage delay and clamping diodes, the time delay between the power supply signal and the reset signal is extended. The specific implementation method includes the use of RC delay circuit and clamping diode.
A longer time delay between the power signal and the reset signal of the graphics card chip is achieved, which meets the timing requirements of non-standard graphics cards and ensures the delay effect of the reset signal.
Smart Images
Figure CN224946402U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electrical technology, and in particular to a delay circuit and a graphics card. Background Technology
[0002] Delay technology is commonly used in various circuit designs to delay the transmission or processing of one or more signals in order to achieve the overall circuit function. Hardware delay circuits can be built by combining components such as registers, counters, power devices, capacitors, resistors, and transistors to adjust the time delay of signal transmission, thereby completing the delay function.
[0003] A graphics card is a crucial component of a personal computer. Its primary function is to process image and video signals output by the computer, converting these signals into a format that the monitor can understand and ultimately displaying them on the screen. A graphics card typically consists of a graphics processing unit (GPU), video memory, and related circuitry. Besides the standard graphics card designs provided by GPU manufacturers, manufacturers can also design various non-standard graphics cards based on their own GPU chips, according to their specific needs.
[0004] When designing non-standard graphics cards, the reset signal of the graphics card chip cannot be directly provided by the motherboard because the connector pin definitions are not standard. This forces graphics card manufacturers to build their own delay circuits according to the graphics card chip's specifications. However, some graphics card chips have significant time delay requirements between the power signal and the reset signal, and conventional single-stage delay circuits cannot meet their timing requirements. Therefore, delay circuits with larger time delays are needed to meet the needs of these types of graphics card designs. Summary of the Invention
[0005] The purpose of this invention is to provide a delay circuit and a graphics card that can provide sufficient time delay between receiving a power signal and generating a reset signal.
[0006] To achieve the above objectives, this utility model provides a delay circuit, including a power supply, a first delay unit, a second delay unit, and a switching unit; wherein: The first delay unit has a first input terminal and a first output terminal. The first input terminal is connected to the power supply, and the first output terminal is connected to the second delay unit. The first delay unit is used to receive a power signal from the power supply and output a first delay signal to the second delay unit. The second delay unit has a second input terminal and a second output terminal. The second input terminal is connected to the first output terminal, and the second output terminal is connected to the switching unit. The second delay unit is used to receive the first delay signal and output a second delay signal to the switching unit. The second delay unit includes a first resistor, a first capacitor, a clamping diode, and a first switching transistor. The first end of the first resistor serves as the second input terminal and is connected to the first output terminal. The second end of the first resistor is grounded through the first capacitor. The cathode of the clamping diode is connected to the second end of the first resistor, and the anode of the clamping diode is connected to the control terminal of the first switching transistor. The output terminal of the first switching transistor serves as the second output terminal. The switching unit is connected to the second output terminal and is used to receive the second delay signal and output a reset signal.
[0007] Preferably, the second delay unit further includes a second resistor and a third resistor; the first switching transistor is a transistor, the base of the transistor serves as the control terminal of the first switching transistor; the collector of the transistor serves as the output terminal of the first switching transistor, is connected to the switching unit via the second resistor, and is connected to the power supply via a series circuit of the second resistor and the third resistor; the emitter of the transistor is grounded.
[0008] Preferably, the transistor is an NPN transistor.
[0009] Preferably, the second delay unit further includes a fourth resistor, one end of which is connected to the anode of the clamping diode, and the other end of which is grounded.
[0010] Preferably, the first delay unit includes a fifth resistor, a second capacitor, and a second switch. The first end of the fifth resistor serves as the first input terminal and is connected to the power supply. The second end of the fifth resistor is connected to the control terminal of the second switch and grounded through the second capacitor. The output terminal of the second switch serves as the first output terminal.
[0011] Preferably, the second switch is an NMOS transistor, the gate of the second switch serves as the control terminal of the second switch and is connected to the second terminal of the fifth resistor; the source of the second switch serves as the output terminal of the second switch and is connected to the first terminal of the first resistor; and the drain of the second switch is connected to the power supply.
[0012] Preferably, the first delay unit further includes a bleed diode, the cathode of which is connected to the power supply, and the anode of which is connected to the second terminal of the fifth resistor.
[0013] Preferably, the switching unit includes a third switching transistor, a sixth resistor, and a third capacitor. The control terminal of the third switching transistor is connected to the second output terminal, the output terminal of the third switching transistor is used to output the reset signal, and the output terminal of the third switching transistor is also connected to the power supply via the sixth resistor and grounded via the third capacitor.
[0014] Preferably, the third switching transistor is an NMOS transistor; the first switching transistor is an NPN transistor, with its base serving as the control terminal and its collector serving as the output terminal, connected to the gate of the third switching transistor via a second resistor and connected to the power supply via a series circuit of the second and third resistors; the emitter of the NPN transistor is grounded; the source of the third switching transistor is grounded; and the drain of the third switching transistor serves as its output terminal. When the first switching transistor is on, the third switching transistor is off, and the drain of the third switching transistor outputs the reset signal.
[0015] This utility model also provides a graphics card, including the aforementioned delay circuit.
[0016] The beneficial effects of this invention are as follows: The delay circuit of this invention sends a reset signal only after two stages of delay (first and second delay units) upon receiving a power signal. Therefore, it can maintain a relatively long time delay between the power signal and the reset signal. Furthermore, the second delay unit is equipped with a clamping diode, ensuring that after the first delayed signal from the first delay unit is output to the second delay unit, a longer delay is required for the first switching transistor of the second delay unit to turn on. This further delays the time it takes for the second delay unit to output the second delayed signal to the switching unit, and consequently, further delays the time it takes for the switching unit to output the reset signal. Therefore, it can significantly extend the time delay between the power signal output upon power-on and the final reset signal output by the switching unit, achieving a longer delay effect for the reset signal relative to the power signal. When applied to graphics cards, especially non-standard graphics cards, this delay circuit can meet the delay requirements of the graphics card chip for the reset signal, thus satisfying the timing requirements of the graphics card chip. Attached Figure Description
[0017] To further understand the features and technical content of this utility model, please refer to the following detailed description and accompanying drawings. However, the drawings are provided for reference and illustration only and are not intended to limit the scope of this utility model. In the drawings,
[0018] Figure 1 This is a block diagram of the delay circuit of this utility model.
[0019] Figure 2This is a circuit wiring diagram of a delay circuit according to an embodiment of the present invention. Detailed Implementation
[0020] To further illustrate the technical means and effects of this utility model, the following detailed description is provided in conjunction with the preferred embodiments of this utility model and their accompanying drawings.
[0021] This invention provides a delay circuit and a graphics card. The delay circuit can provide a sufficient time delay between receiving a power signal and generating a reset signal. When applied to a graphics card, especially a non-standard graphics card, it can meet the delay requirements of the graphics card chip for the reset signal.
[0022] like Figure 1 As shown, the delay circuit of this utility model includes a power supply 10, a first delay unit 20, a second delay unit 30, and a switching unit 40.
[0023] The first delay unit 20 has a first input terminal and a first output terminal. The first input terminal is connected to the power supply 10, and the first output terminal is connected to the second delay unit 30. The first delay unit 20 is used to receive a power signal from the power supply 10 and output a first delay signal to the second delay unit 30.
[0024] The second delay unit 30 has a second input terminal and a second output terminal. The second input terminal is connected to the first output terminal of the first delay unit 20, and the second output terminal is connected to the switch unit 40. The second delay unit 30 is used to receive the first delay signal and output a second delay signal to the switch unit 40.
[0025] The switching unit 40 is connected to the second output terminal of the second delay unit 30, and is used to receive the second delay signal and output a reset signal.
[0026] Therefore, when the power supply signal is received, the delay circuit of this invention sends out a reset signal only after two stages of delay by the first delay unit 20 and the second delay unit 30. Thus, a longer time delay is maintained between the power supply signal and the reset signal, achieving a longer delay effect for the reset signal relative to the power supply signal.
[0027] Furthermore, the first delay unit 20 and the second delay unit 30 can be formed using resistors, capacitors, and switching transistors. The resistors and capacitors form an RC delay circuit to delay the turn-on time of the switching transistor, thereby delaying the issuance of the reset signal. Specifically, clamping diodes can also be included in the first delay unit 20 and the second delay unit 30 to further delay the turn-on time of the switching transistor, thereby further extending the time delay for issuing the reset signal. The switching transistor can be a transistor, MOSFET, etc.
[0028] In a preferred embodiment, the second delay unit 30 may include a first resistor, a first capacitor, a clamping diode, and a first switching transistor. The first end of the first resistor serves as the second input terminal of the second delay unit 30, connected to the first output terminal of the first delay unit 20. The second end of the first resistor is grounded via the first capacitor. The cathode of the clamping diode is connected to the second end of the first resistor, and the anode of the clamping diode is connected to the control terminal of the first switching transistor. The output terminal of the first switching transistor serves as the second output terminal of the second delay unit 30. Thus, the second delay unit 30 forms an RC delay circuit through the first resistor and the first capacitor. Based on the clamping voltage of the clamping diode, after the first delay signal is output to the second delay unit 30, a relatively long delay is required before the first switching transistor is turned on. This significantly delays the time when the second delay unit 30 outputs the second delay signal to the switching unit 40, and consequently significantly delays the time when the switching unit 40 outputs the reset signal.
[0029] Specifically, such as Figure 2 The diagram shown is a circuit wiring diagram of a delay circuit according to an embodiment of the present invention. In this embodiment, the delay circuit includes a power supply 10, a first delay unit 20, a second delay unit 30, and a switching unit 40. The power supply 10 is a P5V power supply.
[0030] The first delay unit 20 includes a fifth resistor R5, a second capacitor C2, and a second switch Q2. The first end of the fifth resistor R5 serves as the first input terminal of the first delay unit 20 and is connected to the power supply 10. The second end of the fifth resistor R5 is connected to the control terminal of the second switch Q2 and grounded via the second capacitor C2. The output terminal of the second switch Q2 serves as the first output terminal of the first delay unit 20. Thus, the fifth resistor R5 and the second capacitor C2 constitute an RC delay circuit, delaying the time it takes for the first delay unit 20 to receive a power signal from the power supply 10 and then activate the second switch Q2 to output a first delayed signal to the second delay unit 20.
[0031] Further, the second switch Q2 can be an NMOS transistor (but is not limited to this), the gate of the second switch Q2 serves as the control terminal of the second switch Q2 and is connected to the second terminal of the fifth resistor R5; the source of the second switch Q2 serves as the output terminal of the second switch Q2 and is connected to the second delay unit 30 for outputting the first delay signal; the drain of the second switch Q2 is connected to the power supply 10.
[0032] The second delay unit 30 includes a first resistor R1, a first capacitor C1, a clamping diode D1, and a first switching transistor Q1. The first end of the first resistor R1 serves as the second input terminal of the second delay unit 30, connected to the first output terminal of the second delay unit 20, i.e., the source of the second switching transistor Q2. The second end of the first resistor R1 is grounded through the first capacitor C1. The cathode of the clamping diode D1 is connected to the second end of the first resistor R1, and the anode of the clamping diode D1 is connected to the control terminal of the first switching transistor Q1. The output terminal of the first switching transistor Q1 serves as the second output terminal of the second delay unit 30. In this way, the first resistor R1 and the first capacitor C1 form an RC delay circuit. Based on the clamping voltage of the clamping diode D1, after the first delay signal of the first delay unit 20 is output to the first end of the first resistor R1, a relatively long delay is required before the first switching transistor Q1 is turned on. This significantly delays the time it takes for the second delay unit 30 to receive the first delay signal and turn on the first switching transistor Q1 to output the second delay signal to the switching unit 40.
[0033] In one embodiment, the clamping diode D1 can be implemented using a Zener diode.
[0034] The switching unit 40 includes a third switching transistor Q3, a sixth resistor R6, and a third capacitor C3. The control terminal of the third switching transistor Q3 is connected to the second output terminal of the second delay unit 30. The output terminal of the third switching transistor Q3 is used to output a reset signal. The output terminal of the third switching transistor Q3 is connected to the power supply 10 via the sixth resistor R6 and grounded via the third capacitor C3.
[0035] Furthermore, the second delay unit 30 may also include a second resistor R2 and a third resistor R3; the first switching transistor Q1 is a transistor, the base of the transistor serves as the control terminal of the first switching transistor Q1 and is connected to the anode of the clamping diode D1; the collector of the transistor serves as the output terminal of the first switching transistor Q1, is connected to the switching unit 40 via the second resistor R2, and is connected to the power supply 10 via a series circuit of the second resistor R2 and the third resistor R3; the emitter of the transistor is grounded.
[0036] Preferably, the first switching transistor Q1 is an NPN transistor, and the third switching transistor Q3 is an NMOS transistor, but not limited thereto. The base of the NPN transistor serves as the control terminal of the first switching transistor Q1 and is connected to the anode of the clamping diode D1; the collector of the NPN transistor serves as the output terminal of the first switching transistor Q1, is connected to the gate of the third switching transistor Q3 via the second resistor R2, and is connected to the power supply 10 via a series circuit of the second resistor R2 and the third resistor R3; the emitter of the NPN transistor is grounded. The source of the third switching transistor Q3 is grounded, and the drain of the third switching transistor Q3 serves as the output terminal of the third switching transistor Q3 for outputting a reset signal, and the drain of the third switching transistor Q3 is also connected to the power supply 10 via the sixth resistor R6 and grounded via the third capacitor C3.
[0037] In this embodiment, the resistance ratio of the second resistor R2 and the third resistor R3 must meet certain requirements, such that when the first switch Q1 is turned on, the voltage across the gate of the third switch Q3 is less than its turn-on voltage, causing the third switch Q3 to turn off, and allowing the drain of the third switch to output a high-level reset signal. In this embodiment, the resistance of the second resistor R2 is 1K ohms, the resistance of the third resistor R3 is 20K ohms, and the turn-on voltage Vgs of the third switch Q3 is 0.5~1.5V, but it is not limited to these values.
[0038] Figure 2 The working process of the delay circuit embodiment of this utility model shown is described below: The delay circuit does not operate when the power supply 10 (P5V power supply) is not powered on.
[0039] When the power supply 10 is powered on, firstly, when the power supply 10 is just powered on, the first switch Q1 of the second delay unit 30 is in the off state, the third switch Q3 of the switching unit 40 is turned on, the drain of the third switch Q3 is in the low level state, and no high level reset signal is output.
[0040] After the power supply 10 is powered on, the RC delay circuit formed by the fifth resistor R5 and the second capacitor C2 of the first delay unit 20 is slowly powered on. When the voltage at the second end of the fifth resistor R5 rises to the conduction voltage of the second switch Q2 (e.g., 2.5V), the second switch Q2 turns on and outputs the first delay signal to the second delay unit 30. That is, the power supply 10 provides voltage to the second delay unit 30 through the second switch Q2, and the second delay unit 30 starts to work. Specifically, the RC delay circuit formed by the first resistor R1 and the first capacitor C1 of the second delay unit 30 is slowly powered on, charging the voltage at the cathode of the clamping diode D1. Since the reverse conduction voltage (clamping voltage) of the clamping diode D1 is relatively high, such as 2.7V, and the conduction voltage of the first switch Q1 is 0.7V, the voltage at the cathode of the clamping diode D1 needs to rise to 3.4V to turn on the first switch Q1. After the first switch Q1 is turned on, the voltage at the drain of the third switch Q3 (the voltage of the second delay signal RST_Q) is approximately 0.25V, which is insufficient to turn on the third switch Q3 (the turn-on voltage is 0.5~1.5V). Therefore, the third switch Q3 is turned off, and its drain outputs a high-level reset signal (DISPLAY_RST signal).
[0041] Therefore, it can be seen that the delay circuit of this utility model can sufficiently extend the time delay between the power supply 10 power-on output power signal and the final output reset signal of the delay circuit.
[0042] In this embodiment, the function of the third capacitor C3 is to ensure the delay of the rising edge of the reset signal. This is because when the power supply 10 is first powered on, the first switch Q1 is cut off and the third switch Q3 is turned on. The third capacitor C3 can prevent the third switch Q3 from turning on too slowly and abnormally pulling up the drain voltage of the third switch Q3.
[0043] Furthermore, the second delay unit 30 may also include a fourth resistor R4, one end of which is connected to the anode of the clamping diode D1, and the other end of which is grounded. The fourth resistor R4 serves as a pull-down resistor for the base of the first switching transistor Q1, preventing abnormal conduction of the first switching transistor Q1.
[0044] Furthermore, the first delay unit 20 also includes a bleeder diode D2, the cathode of which is connected to the power supply 10, and the anode of which is connected to the second terminal of the fifth resistor R5. The bleeder diode D2 is used to quickly discharge the current on the second capacitor C2 when the power is off or there is an abnormal power failure, preventing leakage to the power supply 10.
[0045] This utility model also provides a graphics card, which includes the above-mentioned delay circuit.
[0046] When the delay circuit is applied to the graphics card, its power supply 10 is the power supply for the graphics card, and the reset signal DISPLAY_RST output by the delay circuit is the reset signal for the graphics card chip on the graphics card.
[0047] In summary, the delay circuit of this invention sends a reset signal only after two stages of delay (first and second delay units) upon receiving a power signal. This allows for a longer time delay between the power signal and the reset signal. Furthermore, the second delay unit includes a clamping diode, ensuring that after the first delayed signal from the first delay unit is output to the second delay unit, a longer delay is required for the first switching transistor of the second delay unit to turn on. This significantly delays the time it takes for the second delay unit to output the second delayed signal to the switching unit, and consequently, the time it takes for the switching unit to output the reset signal. Therefore, this effectively extends the time delay between the power signal output upon power-on and the final reset signal output by the delay circuit, achieving a longer delay effect for the reset signal relative to the power signal. When applied to graphics cards, especially non-standard graphics cards, this delay circuit can meet the delay requirements of the graphics card chip for the reset signal, thus satisfying the timing requirements of the graphics card chip.
[0048] As described above, those skilled in the art can make various other corresponding changes and modifications based on the technical solution and concept of this utility model, and all such changes and modifications should fall within the protection scope of the claims of this utility model.
Claims
1. A delay circuit, characterized in that, It includes a power supply, a first delay unit, a second delay unit, and a switching unit; wherein: The first delay unit has a first input terminal and a first output terminal. The first input terminal is connected to the power supply, and the first output terminal is connected to the second delay unit. The first delay unit is used to receive a power signal from the power supply and output a first delay signal to the second delay unit. The second delay unit has a second input terminal and a second output terminal. The second input terminal is connected to the first output terminal, and the second output terminal is connected to the switching unit. The second delay unit is used to receive the first delay signal and output a second delay signal to the switching unit. The second delay unit includes a first resistor, a first capacitor, a clamping diode, and a first switching transistor. The first end of the first resistor serves as the second input terminal and is connected to the first output terminal. The second end of the first resistor is grounded through the first capacitor. The cathode of the clamping diode is connected to the second end of the first resistor, and the anode of the clamping diode is connected to the control terminal of the first switching transistor. The output terminal of the first switching transistor serves as the second output terminal. The switching unit is connected to the second output terminal and is used to receive the second delay signal and output a reset signal.
2. The delay circuit according to claim 1, characterized in that, The second delay unit further includes a second resistor and a third resistor; the first switching transistor is a transistor, the base of which serves as the control terminal of the first switching transistor; the collector of which serves as the output terminal of the first switching transistor, is connected to the switching unit via the second resistor, and is connected to the power supply via a series circuit of the second resistor and the third resistor; the emitter of the transistor is grounded.
3. The delay circuit according to claim 2, characterized in that, The transistor is an NPN transistor.
4. The delay circuit according to claim 1, 2, or 3, characterized in that, The second delay unit further includes a fourth resistor, one end of which is connected to the anode of the clamping diode, and the other end of which is grounded.
5. The delay circuit according to claim 1, characterized in that, The first delay unit includes a fifth resistor, a second capacitor, and a second switch. The first end of the fifth resistor serves as the first input terminal and is connected to the power supply. The second end of the fifth resistor is connected to the control terminal of the second switch and is grounded through the second capacitor. The output terminal of the second switch serves as the first output terminal.
6. The delay circuit according to claim 5, characterized in that, The second switch is an NMOS transistor. The gate of the second switch serves as the control terminal of the second switch and is connected to the second terminal of the fifth resistor. The source of the second switch serves as the output terminal of the second switch and is connected to the first terminal of the first resistor. The drain of the second switch is connected to the power supply.
7. The delay circuit according to claim 5 or 6, characterized in that, The first delay unit further includes a bleed diode, the cathode of which is connected to the power supply, and the anode of which is connected to the second terminal of the fifth resistor.
8. The delay circuit according to claim 1, characterized in that, The switching unit includes a third switching transistor, a sixth resistor, and a third capacitor. The control terminal of the third switching transistor is connected to the second output terminal, and the output terminal of the third switching transistor is used to output the reset signal. The output terminal of the third switching transistor is also connected to the power supply via the sixth resistor and grounded via the third capacitor.
9. The delay circuit according to claim 8, characterized in that, The third switching transistor is an NMOS transistor; the first switching transistor is an NPN transistor, with its base serving as the control terminal and its collector serving as the output terminal, connected to the gate of the third switching transistor via a second resistor and connected to the power supply via a series circuit of the second and third resistors; the emitter of the NPN transistor is grounded; the source of the third switching transistor is grounded; and the drain of the third switching transistor serves as its output terminal. When the first switching transistor is on, the third switching transistor is off, and the drain of the third switching transistor outputs the reset signal.
10. A graphics card, characterized in that, The delay circuit includes any one of claims 1-9.