A display driver chip, a display module, a lamp driver integrated chip, and a display panel.

Abstract

This application provides a display driver chip, a display module, a lamp driver integrated chip, and a display panel, relating to the field of display technology. It aims to reduce the number of chip pins, simplify circuit layout, and lower power consumption within the limited area of ​​the display driver chip. The display driver chip includes a signal analysis circuit and a digital logic circuit. The first input terminal of the signal analysis circuit receives a reference voltage, the second input terminal is the data terminal of the display driver chip, the first output terminal of the signal analysis circuit is connected to the data terminal of the digital logic circuit, and the second output terminal of the signal analysis circuit is connected to the clock terminal of the digital logic circuit. The signal analysis circuit is used to generate a second data signal and a first clock signal based on the received first data signal and the reference voltage, respectively. The digital logic circuit is used to output a drive signal based on the second data signal and the first clock signal.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driver chip, a display module, a lamp driver integrated chip, and a display panel. Background Technology

[0002] In recent years, as display technology has continued to develop towards higher resolution, higher refresh rates, and lower power consumption, the design of display driver chips has also faced many challenges. In traditional architectures, display driver chips typically require a large number of input / output pins to work with peripheral circuits, resulting in complex overall circuit layouts, high wiring density, and consequently, problems such as signal interference, increased power consumption, and increased manufacturing costs.

[0003] Therefore, how to reduce the number of chip pins, simplify circuit layout, and reduce power consumption under the limited area of ​​display driver chips has become an urgent technical problem to be solved. Utility Model Content

[0004] The purpose of this application is to provide a display driver chip, a display module, a lamp driver integrated chip, and a display panel, which can reduce the number of chip pins, simplify circuit layout, and reduce power consumption when the area of ​​the display driver chip is limited.

[0005] To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0006] A first aspect of this application provides a display driver chip, including a signal parsing circuit and a digital logic circuit. A first input terminal of the signal parsing circuit is used to receive a reference voltage, a second input terminal of the signal parsing circuit is a data terminal of the display driver chip, a first output terminal of the signal parsing circuit is connected to the data terminal of the digital logic circuit, and a second output terminal of the signal parsing circuit is connected to the clock terminal of the digital logic circuit. The signal parsing circuit is used to generate a second data signal and a first clock signal based on the received first data signal and the reference voltage, respectively; the digital logic circuit is used to output a driving signal based on the second data signal and the first clock signal.

[0007] In the above technical solution, the signal analysis circuit can process the first data signal to obtain a second data signal representing the data information and a first clock signal providing a timing reference for the drive signal, enabling the digital logic circuit to output the drive signal normally based on the second data signal and the first clock signal. Therefore, in the absence of an internal clock source and no external clock input required, the display driver chip provided in this application only needs one chip pin to provide the first data signal. Compared to the prior art, where the clock data recovery circuit requires two pins to provide two differential signals to generate the data signal and the clock signal, the solution provided in this application reduces the number of pads (PADs) soldered to the chip interface and the number of pins occupied. Moreover, compared to the clock data recovery circuit based on a phase-locked loop structure, the circuit structure of this application is simpler, which is beneficial for reducing chip area and power consumption.

[0008] In conjunction with the first aspect, in one possible implementation, the first data signal has a first pulse width indicating first data and a second pulse width indicating second data, the first pulse width being different from the second pulse width.

[0009] Based on the above technical solution, different pulse widths can be used to indicate different data. Therefore, the display driver chip provided in this application embodiment only requires one chip pin to provide the first data signal to generate the second data signal and the first clock signal, which can reduce the number of PADs soldered to the chip interface and the number of pins occupied. In addition, using pulse width to represent different data, and then processing the first data signal to parse the first clock signal and the second data signal from the first data signal, the implementation method is simpler and can further simplify the circuit topology.

[0010] In one possible implementation, the signal parsing circuit includes a data signal generation module and a clock signal generation module. A first input terminal of the data signal generation module is used to receive a reference voltage. The second input terminal of the data signal generation module and the input terminal of the clock signal generation module are connected together to form the second input terminal of the signal parsing circuit. A third input terminal of the data signal generation module is connected to the first output terminal of the clock signal generation module. The output terminal of the data signal generation module is the first output terminal of the signal parsing circuit, and the second output terminal of the clock signal generation module is the second output terminal of the signal parsing circuit. The clock signal generation module is used to: generate a first clock signal and a second clock signal based on the first data signal, wherein the second clock signal is the inverted signal of the first clock signal; and the data signal generation module is used to: generate a second data signal based on the reference voltage, the first data signal, and the second clock signal.

[0011] Based on the above technical solution, the data signal generation module and the clock signal generation module can process the first data signal respectively to obtain a second data signal for representing data information, and a first clock signal and a second clock signal for providing timing reference. The second clock signal is used to provide the timing reference for the second data signal, and the first clock signal is used to provide the timing reference for the drive signal. It should be understood that when the second clock signal provides the timing reference for the second data signal, the rising edge of the second data signal will coincide with the rising edge of the second clock signal. The second data signal cannot provide a stable time window for data sampling to the second clock signal. Therefore, the first clock signal, which is inversely phase to the second clock signal, can be used to sample the second data signal after the second data signal transition and during the stable high-level process. This allows the digital logic circuit to output the drive signal normally based on the second data signal and the first clock signal.

[0012] In conjunction with the first aspect, in one possible implementation, the data signal generation module includes an integration unit, a comparison unit, and a flip-flop. The input terminal of the integration unit is used to receive a first data signal, the output terminal of the integration unit is connected to the first input terminal of the comparison unit, the second input terminal of the comparison unit is used to receive a reference voltage, the output terminal of the comparison unit is connected to the data terminal of the flip-flop, the clock terminal of the flip-flop is used to receive a second clock signal, and the output terminal of the flip-flop is the first output terminal of the signal analysis circuit. The integration unit is used to: generate an integrated signal based on the first data signal; the comparison unit is used to: generate a comparison signal based on the reference voltage and the integrated signal; and the flip-flop is used to: output a second data signal based on the second clock signal and the comparison signal.

[0013] Based on the above technical solution, a simple circuit structure for a data signal generation module is provided. Through an integration unit, a comparison unit, and a flip-flop, the first data signal can be converted into a second data signal. Compared with the equalizer, edge sampler, data sampler, decoder, and serial-to-parallel conversion module used in the prior art to recover data signals, the circuit structure provided in this application embodiment is simple and the signal transmission link is shorter, which is beneficial to saving chip area and reducing power consumption.

[0014] In conjunction with the first aspect, in one possible implementation, the integrating unit includes a first buffer and an integrating subunit. The input terminal of the first buffer is used to receive a first data signal, and the output terminal of the first buffer is connected to the input terminal of the integrating subunit. For example, the integrating subunit may include a resistor and a capacitor.

[0015] Based on the above technical solution, a simple circuit structure for an integrating unit is provided. The first buffer can enhance the driving capability of the first data signal to ensure the integrity of the first data signal transmission on the signal link. The integrating subunit can integrate the first data signal to output an integrated signal that can be compared with a reference voltage.

[0016] In conjunction with the first aspect, in one possible implementation, the comparison unit includes a second buffer and a hysteresis comparator. The non-inverting input of the hysteresis comparator is connected to the output of the integration unit, the inverting input of the hysteresis comparator is used to receive a reference voltage, the output of the hysteresis comparator is connected to the input of the second buffer, and the output of the second buffer is connected to the data terminal of the trigger.

[0017] Based on the above technical solution, a simple circuit structure for a comparison unit is provided. The hysteresis comparator has a fixed hysteresis time. After the integral signal and the reference voltage are input to the input terminal of the hysteresis comparator, the hysteresis comparator will delay for a fixed period before outputting the comparison result to meet the sampling setup time of the flip-flop and ensure the accuracy of the flip-flop's output. A second buffer is placed between the hysteresis comparator and the flip-flop, which can enhance the driving capability of the comparison signal and ensure the integrity of the comparison signal transmission in subsequent signal links.

[0018] In conjunction with the first aspect, in one possible implementation, the clock signal generation module includes a first inverter and a second inverter. The input terminal of the first inverter is used to receive a first data signal, and the output terminal of the first inverter is connected to the third input terminal of the data signal generation module and the input terminal of the second inverter, respectively. The output terminal of the second inverter is the second output terminal of the signal parsing circuit. The first inverter is used to invert the first data signal to output a second clock signal; the second inverter is used to invert the second clock signal to output a first clock signal.

[0019] Based on the above technical solution, inverting the first data signal and outputting a second clock signal enables the second clock signal to accurately sample the high and low levels of the comparison signal generated in the data signal generation module. Inverting the second clock signal and outputting a first clock signal allows the first clock signal to sample the second data signal after the second data signal transitions and during its stable high-level period, thereby outputting a stable drive signal.

[0020] In conjunction with the first aspect, in one possible implementation, the display driver chip further includes a voltage generation circuit. The input terminal of the voltage generation circuit is the power supply terminal of the display driver chip, and the output terminal of the voltage generation circuit is connected to the first input terminal of the signal analysis circuit. The voltage generation circuit is used to output a reference voltage based on the power supply voltage. The voltage generation circuit provided in this application embodiment can be a resistor voltage divider circuit, a capacitor voltage divider circuit, a circuit that uses diode clamping to achieve voltage division, or a circuit that uses other voltage divider structures to achieve voltage division.

[0021] Based on the above technical solution, the reference voltage can be obtained by voltage division of the power supply voltage. That is, by reusing the pins of the power supply voltage, a reference voltage can be provided to the signal analysis circuit, which can reduce the number of pins used.

[0022] A second aspect of this application provides a display module, which includes a display driver chip and a display array provided in the first aspect or any possible implementation of the first aspect, wherein the display driver chip is used to drive the display array according to a drive signal.

[0023] A third aspect of this application provides a lamp driver integrated chip, which includes a display driver chip provided in the first aspect or any possible implementation of the first aspect, and at least one set of lamps; the output terminal of the display driver chip is connected to the drive signal input terminal of the at least one set of lamps; the clock data pin of the lamp driver integrated chip is the data terminal of the display driver chip and is used to receive a first data signal; the first power supply pin of the lamp driver integrated chip is the power supply terminal of the display driver chip; and the second power supply pin of the lamp driver integrated chip is the power supply terminal of the at least one set of lamps.

[0024] A fourth aspect of the embodiments of this application provides a display panel, the display panel including a plurality of coupled lamp driver integrated chips as provided in the third aspect, or the display panel including at least one display module as provided in the second aspect.

[0025] The descriptions of the second to fourth aspects in this application can be referred to the detailed description of the first aspect; and the beneficial effects of the second to fourth aspects can be referred to the analysis of the beneficial effects of the first aspect, which will not be repeated here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams.

[0027] Figure 1This is a schematic diagram of a clock data recovery circuit.

[0028] Figure 2 This is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0029] Figure 3 This is a schematic diagram of another display device provided in an embodiment of this application;

[0030] Figure 4 This is a schematic diagram of the structure of another display device provided in an embodiment of this application;

[0031] Figure 5 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0032] Figure 6 This is a schematic diagram of a lamp driver integrated chip soldered to a pad.

[0033] Figure 7 This is a schematic diagram of the structure of a lamp driver integrated chip provided in an embodiment of this application;

[0034] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0035] Figure 9 This is a schematic diagram of the structure of a display driver chip provided in an embodiment of this application;

[0036] Figure 10 This is a schematic diagram of another display driver chip provided in an embodiment of this application;

[0037] Figure 11 A waveform diagram of a first data signal provided in an embodiment of this application;

[0038] Figure 12 A circuit topology diagram of a display driver chip provided in an embodiment of this application;

[0039] Figure 13 A waveform diagram related to a data signal generation module provided in an embodiment of this application;

[0040] Figure 14 A waveform diagram related to another data signal generation module provided in an embodiment of this application;

[0041] Figure 15 This is a waveform diagram related to a display driver chip provided in an embodiment of this application.

[0042] Figure label:

[0043] 100-Display driver chip, 1000-Display device, 1100-Display panel, 1200-Main unit, 1301-Row driver chip, 1302-Column driver chip, 1101-Lamp driver integrated chip, 1102-Display array, 1103-Display module, 110-Signal parsing circuit, 111-Data signal generation module, 112-Clock signal generation module, 120-Digital logic circuit, 1111-Integrator unit, 1112-Comparator unit, 1113-Flip-flop, 1111a-First buffer, 1112a-Hysteresis comparator, 1112b-Second buffer, 1121-First inverter, 1122-Second inverter, 130-Voltage generation circuit. Detailed Implementation

[0044] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0047] The terms "coupled" and "connected," and their derivative expressions, may be used in describing some embodiments. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0048] Before introducing the embodiments of this application, the relevant technologies involved in this application will be described first.

[0049] To reduce the area of ​​display driver chips, current technologies mainly combine data and clock signals into a single pin, and then separate the clock and data signals based on the received clock and data signals. Currently, common clock and data signal separation techniques primarily employ clock-data recovery circuits. Figure 1 This is a schematic diagram of a clock data recovery circuit. Figure 1 As shown, the clock and data recovery (CDR) circuit is a clock recovery circuit based on a phase-locked loop (PLL) structure. The CDR circuit includes a differential receiver, an equalizer, a phase detector, a loop filter, a voltage-controlled oscillator, an edge sampler and a data sampler, a decoder, and a serial-to-parallel conversion module.

[0050] Specifically, the differential receiver receives the input differential data signals (DATAP and DATAN) and inputs them to the equalizer to compensate for channel loss and improve signal quality. The equalizer outputs the equalized data signal to both the phase detector and the edge sampler. The phase detector compares the transition edges of the input data with the phase of the locally recovered clock, generating a phase error signal. This phase error signal is filtered by a loop filter to remove high-frequency noise, outputting a smooth control voltage. This control voltage drives the voltage-controlled oscillator (VCO) to adjust the frequency and phase of its output clock, gradually aligning it with the edges of the input data. The clock output from the VCO is divided into two paths: one path is fed back to the phase detector, forming a closed-loop control to continuously correct the phase error of the output clock; the other path is sent to the data sampler to provide a synchronous clock for data sampling and decoding. The data sampler samples the data at the center position of the recovered clock (provided by locking the VCO), avoiding transition edges to ensure sampling stability. The data sampler sends the sampled data to the decoder, and the decoder outputs it to the serial-to-parallel conversion module to convert the high-speed serial data into parallel low-speed data for easier subsequent processing.

[0051] See Figure 1 The structure and function of this CDR circuit are relatively complex, which not only occupies more chip area but also leads to higher power consumption. Furthermore, since the inputs of this CDR circuit are differential signal pairs, it still requires two pins to provide differential data signals. Although the CDR circuit does not require a clock signal from the CK pin, it still occupies two pins for providing differential data signals, thus failing to achieve the goal of reducing pin occupancy.

[0052] In view of this, embodiments of this application provide a display driver chip, a display module, a lamp driver integrated chip, and a display panel, which are used to reduce the number of chip pins, simplify circuit layout, and reduce power consumption when the area of ​​the display driver chip is limited.

[0053] The following is combined with Figures 2 to 4 The application scenarios of the embodiments of this application will be described.

[0054] Figure 2 An example of a display device provided in an embodiment of this application is illustrated. The display device 1000 can be any device for displaying moving (e.g., video), fixed (e.g., still image), text, or images.

[0055] For example, see Figure 2 and Figure 3 The display device 1000 can be any product or component with display function, such as electronic billboards, shopping mall displays, signs, televisions, computers, in-flight displays, in-vehicle displays, clocks, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0056] Depending on the application scenario, the display device 1000 can be a flat display device or a curved display device, and the shape of the display surface of the display device 1000 can be any one of a circle, an ellipse, a polygon, or an irregular shape.

[0057] For example, such as Figure 2 As shown, the display device 1000 can be a flat panel display device; for example, the display device 1000 can be... Figure 2 The electronic billboard shown. For example, such as... Figure 3 As shown, the display device 1000 can be a curved display device; for example, the display device 1000 can be... Figure 3 The wave-shaped curved surface display device shown.

[0058] In some embodiments, see Figures 2 to 4 The display device 1000 may include one or more display panels 1100. The number of display panels 1100 can be set as needed. Figure 2 and Figure 3 The following example uses four display panels 1100 for illustration. The display driver chip provided in this embodiment can be located in the non-display area of ​​the display panel 1100.

[0059] For further details, please refer to [link / reference]. Figure 4The display device 1000 may further include a host 1200, with the display panel 1100 connected to the host 1200. The host 1200 controls the display panel 1100 to display data, enabling functions such as video splicing and synchronized playback. The display driver chip provided in this embodiment is located in the display panel 1100. The host 1200 may be an electronic device such as a display controller, timing controller, TV box, server, mobile phone, or tablet; this embodiment does not specifically limit its functionality.

[0060] For example, when the display device 1000 includes a plurality of display panels 1100, each display panel 1100 can display a portion of the image when displaying an image. The images displayed by each display panel 1100 can be stitched together to form the complete content of the image, thereby achieving a larger screen effect and providing users with a better visual experience.

[0061] Figure 5 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 5 As shown, the display device 1000 includes a display panel 1100, a plurality of row driver chips 1301 and a plurality of column driver chips 1302.

[0062] The display panel 1100 includes a plurality of integrated lamp driver chips 1101 arranged in a matrix. For example, the plurality of integrated lamp driver chips 1101 are arranged along a first direction X and a second direction Y, respectively. It should be noted that the first direction X is the row direction in which the plurality of integrated lamp driver chips 1101 are arranged, and the second direction Y is the column direction in which the plurality of integrated lamp driver chips 1101 are arranged. The integrated lamp driver chips 1101 arranged along the X direction can also be referred to as pixel rows, and the integrated lamp driver chips 1101 arranged along the Y direction can also be referred to as pixel columns. The first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y are perpendicular.

[0063] The output of any one of the multiple row driver chips 1301 is connected to the power supply pin VRGB of at least one row lamp driver integrated chip 1101, for providing power supply VGRB to the lamp groups in the at least one row lamp driver integrated chip 1101. The output of any one of the multiple column driver chips 1302 is connected to the clock data pin of at least one column lamp driver integrated chip 1101, for outputting clock data signal DATA to the at least one column lamp driver integrated chip 1101.

[0064] Specifically, the VRGB signal provided by the row driver chip 1301 is used to select a row of integrated lamp driver chips 1101. The column driver chip 1302 provides clock data signals DATA to the corresponding row of integrated lamp driver chips 1101. After the column driver chip 1302 finishes sending data to a row, that row is displayed. For example, after the row driver chip 1301 sends the row selection signal VRGB to the first row of integrated lamp driver chips 1101, the column driver chip 1302 sends clock data signals DATA to each column of integrated lamp driver chips 1101 in the first row, so as to send the clock data signals DATA into the driver chip of the integrated lamp driver chip 1101. When the data of the first row is written, the integrated lamp driver chip 1101 controls that row to enter the display stage, and the second row begins the above selection and data writing operation. Alternatively, after all driver chips 1302 have sent data to the integrated lamp driver chips 1101, all row integrated lamp driver chips 1101 enter the display stage.

[0065] Figure 6 This is a schematic diagram of a lamp driver integrated chip 1101 soldered to pads. It is intended as an example and not a limitation. Figure 6 The following example illustrates how the five pins of the 1101 integrated lamp driver chip are soldered to five pads. Figure 6 As shown, these five pins include at least the VCC pin, DI pin, GND pin, VRGB pin, and CK pin. The VCC pin provides the power supply voltage required by the display driver chip, the DI pin provides the data signal required by the display driver chip, the GND pin provides the ground voltage, the CK pin provides the clock signal required by the display driver chip, and the VRGB pin provides the power supply voltage for the pixel unit, i.e., the light-emitting diode.

[0066] See Figure 6 As can be seen, the size of the 1101 integrated lamp driver chip is similar to that of the PAD. This makes it easy for short circuits to occur on the side with more PADs, such as the side where the VCC pin, DI pin, and GND pin are located, which poses a huge challenge to the soldering yield of the PCB.

[0067] Therefore, in this embodiment of the application, the DI pin and the CK pin are combined to further reduce the number of pins in the lamp driver integrated chip 1101.

[0068] like Figure 7 As shown, the integrated lamp driver chip 1101 provided in this embodiment includes a display driver chip 100 and at least one set of lamps. As an example and not a limitation, the lamp set may include red sub-pixels, green sub-pixels, and blue sub-pixels. Figure 7The integrated lamp driver chip 1101 includes a set of lamp groups, and is illustrated by using "R" to represent red sub-pixels, "G" to represent green sub-pixels, and "B" to represent blue sub-pixels. For example, the integrated lamp driver chip 1101 may include multiple sets of lamp groups, and the output terminal of the display driver chip is connected to the drive signal input terminal of the lamp group. For instance, the output terminal of the display driver chip is connected to "R OUT", "G OUT", and "B OUT" of the lamp group, respectively.

[0069] Please also refer to Figures 5 to 7 The clock data pin DATA of the integrated lamp driver chip 1101 is the data terminal DATA of the display driver chip 100 and is used to receive the first data signal DA1. The first power supply pin VCC of the integrated lamp driver chip 1101 is the power supply terminal VCC of the display driver chip 100, and the second power supply pin VRGB of the integrated lamp driver chip 1101 is the power supply terminal VRGB of at least one group of lamps. It should be noted that in this embodiment, the clock data pin DATA of the integrated lamp driver chip 1101 is the pin formed by merging the CK pin and the DI pin. This reduces the number of pins of the integrated lamp driver chip 1101, facilitates the wiring and connection of the integrated lamp driver chip 1101 on the display panel 1000, and reduces the area and cost of the integrated lamp driver chip 1101. Furthermore, in this embodiment, the VRGB pin serves as both a row selection pin and a power supply pin for the lamp group. That is, VRGB is first used as a row selection signal to select one row, so that the input is written into the display driver chip 100 in the lamp driver integrated chip 1101. Then, VRGB serves as the power supply for the lamp group, so that the lamp driver integrated chip 1101 drives the light-emitting diode to emit light according to the written data.

[0070] Each of the aforementioned sub-pixels may include micro light-emitting diodes (MicroLEDs) and / or mini light-emitting diodes (Mini LEDs). The size (e.g., length) of the MicroLED is less than 50 micrometers, for example, 10 micrometers to 50 micrometers. The size (e.g., length) of the Mini LED is 50 micrometers to 150 micrometers, for example, 80 micrometers to 120 micrometers.

[0071] In another possible implementation, the display panel 1100 may also not include the aforementioned integrated lamp driver chip 1101. For example, as Figure 8 As shown, the display panel includes at least one display module 1103, the display module 1103 includes a display driver chip 100 and a display array 1102, and the display driver chip 100 is used to drive the display array 1102.

[0072] Specifically, such as Figure 8As shown, the display module 1103 may further include a row driver chip 1301. The row driver chip 1301 is used to sequentially and row by row "open" (scan) each row of pixels in the display array 1102. The display driver chip 100 is used to receive display data and convert it into corresponding voltage signals to control the brightness and color of each column of pixels. When a row is activated by the row driver chip 1301, the display driver chip 100 applies the data signals of all pixels in that row synchronously to the column lines of the display array 1102 through multiple parallel data lines. At this time, the pixel circuits located at the intersection of the activated row and these data columns are simultaneously "selected". Each pixel circuit is charged according to the data voltage on its column line, thereby determining its light intensity. After all rows have been scanned, the display of one frame of image is completed. It should be noted that the row driver chip 1301 and the display driver chip 100 can be integrated separately or combined into one. This application embodiment does not specifically limit this. Figure 8 The example shown uses a display array consisting of two rows and three columns of light-emitting diodes, but does not limit its application.

[0073] Figure 9 This is a schematic diagram of the structure of a display driver chip provided in an embodiment of this application.

[0074] In some embodiments, such as Figure 9 As shown, the display driver chip 100 provided in this embodiment includes a signal parsing circuit 110 and a digital logic circuit 120. The first input terminal of the signal parsing circuit 110 is used to receive a reference voltage Vref, the second input terminal of the signal parsing circuit 110 is the data terminal DATA of the display driver chip 100, the first output terminal of the signal parsing circuit 110 is connected to the data terminal Din of the digital logic circuit 120, and the second output terminal of the signal parsing circuit 110 is connected to the clock terminal CK1 of the digital logic circuit 120. This is an example and not a limitation. Figure 9 The diagram also shows the power supply terminal VCC and the ground terminal GND of the display driver chip 100, wherein the power supply terminal VCC is used to provide the power supply voltage VCC, and the ground terminal GND is used to provide the ground voltage GND.

[0075] The signal parsing circuit 110 is used to generate a second data signal DA2 and a first clock signal CLK1 based on the received first data signal DA1 and the reference voltage Vref, respectively.

[0076] The digital logic circuit 120 is used to output a drive signal based on the second data signal DA2 and the first clock signal CLK1.

[0077] Furthermore, such as Figure 10As shown, the signal analysis circuit 110 includes a data signal generation module 111 and a clock signal generation module 112. The first input terminal of the data signal generation module 111 is used to receive a reference voltage Vref. The second input terminal of the data signal generation module 111 and the input terminal of the clock signal generation module 112 are connected together to form the second input terminal of the signal analysis circuit 110. The third input terminal of the data signal generation module 111 is connected to the first output terminal of the clock signal generation module 112. The output terminal of the data signal generation module 111 is the first output terminal of the signal analysis circuit 110, and the second output terminal of the clock signal generation module 112 is the second output terminal of the signal analysis circuit 110.

[0078] The clock signal generation module 112 is used to generate a first clock signal CLK1 and a second clock signal CLK2 based on the first data signal DA1, wherein the second clock signal CLK2 is the inverted signal of the first clock signal CLK1. The first data signal DA1 is the data signal provided by the DATA pin.

[0079] The data signal generation module 111 is used to generate a second data signal DA2 based on the reference voltage Vref, the first data signal DA1 and the second clock signal CLK2.

[0080] The working principle of the aforementioned display driver chip 100 is as follows: The first data signal DA1 provided by the data terminal DATA is processed by the clock signal generation module 112 to generate a first clock signal CLK1 and a second clock signal CLK2. The first data signal DA1 provided by the data terminal DATA, along with the reference voltage Vref, is processed by the data signal generation module 111 and outputs the second data signal DA2 in sequence with the second clock signal CLK2. When the clock terminal CK of the digital logic circuit 120 receives the first clock signal CLK1 and the data terminal Din receives the second data signal DA2, it can output a drive signal to the subsequent circuit under the action of the first clock signal CLK1 to drive the display array or the lamp group display of the integrated lamp driver chip 1101. It should be understood that when the second clock signal CLK2 provides the timing reference for the second data signal DA2, the rising edge of the second data signal DA2 will coincide with the rising edge of the second clock signal CLK2. The second data signal DA2 cannot provide a stable time window for data sampling to the second clock signal CLK2. Therefore, the first clock signal CLK1, which is inversely phase to the second clock signal CLK2, can be used to sample the second data signal DA2 after the transition and during the stable high-level process. This allows the digital logic circuit 120 to output the drive signal normally based on the second data signal DA2 and the first clock signal CLK1.

[0081] In the above technical solution, the signal analysis circuit 110 can process the first data signal DA1 in conjunction with the reference voltage to obtain a second data signal DA2 for representing data information and a first clock signal CLK1 for providing a timing reference, so that the digital logic circuit 120 can output a drive signal normally based on the second data signal DA2 and the first clock signal CLK1. Therefore, in the absence of an internal clock source and no need for an external clock input, the display driver chip 100 provided in this application only requires one chip pin to provide the first data signal DA1. Compared with the prior art, where the clock data recovery circuit requires two pins to provide two differential signals to generate the data signal and the clock signal, the solution provided in this application can reduce the number of PADs soldered to the chip interface and the number of pins occupied. Moreover, compared with the clock data recovery circuit based on the phase-locked loop structure, the circuit structure of this application is simpler, which is beneficial for reducing chip area and power consumption.

[0082] In one embodiment, the first data signal DA1 provided in this application has a first pulse width tp1 indicating the first data and a second pulse width tp2 indicating the second data, and the first pulse width tp1 and the second pulse width tp2 are different, or the duty cycle of the first data is different from the duty cycle of the second data. For example, if the first data is a low-level "logic 0" and the second data is a high-level "logic 1", then the first pulse width tp1 is less than the second pulse width tp2. If the first data is a high-level "logic 1" and the second data is a low-level "logic 0", then the first pulse width tp1 is greater than the second pulse width tp2.

[0083] Figure 11 This is a waveform diagram of a first data signal provided in an embodiment of this application. It is intended as an example and not a limitation. Figure 11 The diagram illustrates logic 0 (low level) for the first data and logic 1 (high level) for the second data. Figure 11 In this context, T1 represents one signal period of the first data, and T2 represents one signal period of the second data. The signal periods T1 of the first data and T2 of the second data can be the same or different, and the duty cycles of the first data and the second data can be the same or different. This application does not impose specific limitations on these aspects.

[0084] like Figure 11 As shown in Figure (a), when the signal period T1 of the first data is less than the signal period T2 of the second data, the duty cycle of the first data is about 50% and the duty cycle of the second data is about 50%. At this time, the first pulse width tp1 and the second pulse width tp2 satisfy: tp1 < tp2.

[0085] like Figure 11As shown in Figure (b), when the signal period T1 of the first data is equal to the signal period T2 of the second data, the duty cycle of the first data is about 30% and the duty cycle of the second data is about 60%. At this time, the first pulse width tp1 and the second pulse width tp2 satisfy: tp1 < tp2.

[0086] like Figure 11 As shown in Figure (c), when the signal period T1 of the first data is greater than the signal period T2 of the second data, the duty cycle of the first data is about 20% and the duty cycle of the second data is about 60%. At this time, the first pulse width tp1 and the second pulse width tp2 still satisfy: tp1 < tp2.

[0087] Figure 12 This is a topology diagram of a display driver chip provided in an embodiment of this application.

[0088] In one embodiment, such as Figure 12 As shown, the display driver chip 100 also includes a voltage generation circuit 130. For example, the input terminal of the voltage generation circuit 130 is the power supply terminal VCC of the display driver chip 100, and the output terminal of the voltage generation circuit 130 is connected to the first input terminal of the signal analysis circuit 110.

[0089] The voltage generation circuit 130 is used to generate a reference voltage Vref based on the power supply voltage VCC.

[0090] Optionally, the reference voltage Vref can be obtained by dividing the power supply voltage VCC. That is, by multiplexing the power supply terminal VCC, the reference voltage Vref can be provided to the data signal generation module 111. The voltage generation circuit 130 can be a resistor voltage divider circuit, a capacitor voltage divider circuit, a circuit that uses diode clamping to achieve voltage division, or a circuit that uses other voltage divider structures to achieve voltage division. The embodiments of this application do not specifically limit the topology of the voltage generation circuit 130.

[0091] The following continues to be combined Figure 12 The specific structure of the display driver chip provided in the embodiments of this application will be further described.

[0092] In one embodiment, such as Figure 12As shown, the data signal generation module 111 includes an integration unit 1111, a comparison unit 1112, and a flip-flop 1113. The input terminal of the integration unit 1111 is used to receive the first data signal DA1. The output terminal of the integration unit 1111 is connected to the first input terminal of the comparison unit 1112. The second input terminal of the comparison unit 1112 is used to receive the reference voltage Vref. The output terminal of the comparison unit 1112 is connected to the data terminal D of the flip-flop 1113. The clock terminal CK2 of the flip-flop 1113 is used to receive the second clock signal CLK2. The output terminal Q of the flip-flop 1113 is the first output terminal of the signal parsing circuit 110 and is connected to the data terminal Din of the digital logic circuit 120.

[0093] The aforementioned integration unit 1111 is used to generate an integral signal C based on the first data signal DA1.

[0094] In one example, such as Figure 12 As shown, the integration unit 1111 includes a first buffer 1111a and an integration subunit. The input terminal of the first buffer 1111a is used to receive the first data signal DA1, and the output terminal of the first buffer 1111a is connected to the input terminal of the integration subunit.

[0095] Specifically, the first buffer 1111a is disposed between the data terminal DATA and the integrating subunit, which can enhance the driving capability of the first data signal DA1 and ensure the integrity of the transmission of the first data signal DA1 on the signal link.

[0096] For example, the integrating subunit includes a resistor R1 and a capacitor C1. The resistor R1 is connected between the output terminal of the first buffer 1111a and one end of the capacitor C1, and the other end of the capacitor C1 is grounded. The connection point between the resistor R1 and the capacitor C1 is the output terminal of the integrating unit 1111. The resistor R1 and the capacitor C1 constitute an RC integrating circuit. Utilizing the charging and discharging characteristics of the capacitor C1 and the current limiting effect of the resistor R1, the first data signal DA1 is integrated to output the integrated signal C.

[0097] The aforementioned comparison unit 1112 is used to generate a comparison signal D1 based on the reference voltage Vref and the integral signal C.

[0098] In one example, such as Figure 12 As shown, the comparison unit 1112 includes a second buffer 1112b and a hysteresis comparator 1112a. The non-inverting input of the hysteresis comparator 1112a is connected to the output of the integration unit 1111, the inverting input of the hysteresis comparator 1112a is used to receive the reference voltage Vref, the output of the hysteresis comparator 1112a is connected to the input of the second buffer 1112b, and the output of the second buffer 1112b is connected to the data terminal D of the flip-flop 1113.

[0099] Specifically, the hysteresis comparator 1112a compares the voltage of the integrated signal C received at the non-inverting input with the reference voltage Vref at the inverting input. When the voltage of the integrated signal C is greater than the reference voltage Vref, the second data signal DA2 output by the hysteresis comparator 1112a is at a high level; when the voltage of the integrated signal C is less than the reference voltage Vref, the second data signal DA2 output by the hysteresis comparator 1112a is at a low level. Furthermore, the hysteresis comparator 1112a has a fixed hysteresis time. After receiving the integrated signal C and the reference voltage Vref, the hysteresis comparator 1112a delays for a fixed period before outputting the comparison result to meet the sampling setup time of the flip-flop 1113, ensuring that the flip-flop 1113 can accurately output the second data signal DA2.

[0100] The aforementioned second buffer 1112b is disposed between the hysteresis comparator 1112a and the flip-flop 1113, which can enhance the driving capability of the comparison signal D1 to ensure the integrity of the comparison signal D1 in the subsequent signal link.

[0101] The following combination Figure 12 ,by Figure 13 and Figure 14 Taking the waveform shown as an example, the working process of the data signal generation module 111 will be further explained.

[0102] like Figure 13 The diagram shown is a waveform diagram related to a data signal generation module provided in an embodiment of this application.

[0103] Specifically, the pulse width between the first rising edge and the first falling edge of the first data signal DA1 is greater than the pulse width between the second rising edge and the second falling edge. Therefore, the first high-level pulse of the first data signal DA1 represents "logic 1", and the second high-level pulse of the first data signal DA1 represents "logic 0". After passing through the integration unit 1111, the first data signal DA1 outputs an integrated signal C. Because the duration of the first high-level pulse is relatively long, that is, the charging time of capacitor C1 is relatively long, the integrated voltage can exceed the reference voltage Vref. However, the duration of the second high-level pulse is relatively short, and the charging time of capacitor C1 is also relatively short, so the integrated voltage cannot meet the judgment condition, that is, it is less than the reference voltage Vref. After the voltage of the integrated signal C exceeds the reference voltage Vref, the hysteresis comparator 1112a outputs a high-level comparison signal D1 after a fixed hysteresis time, and outputs a low-level comparison signal D1 after a fixed hysteresis time when the voltage of the integrated signal C is less than the reference voltage Vref.

[0104] Figure 14This is a waveform diagram related to another data signal generation module provided in an embodiment of this application. Because the waveform of the integral signal C is affected by factors such as voltage, temperature, and circuit parameters, the transition time of the comparison signal D1 shifts. For example, Figure 14 The three integral signals C with different waveforms shown in the example will generate three comparison signals D1 with different waveforms after passing through the hysteresis comparator 1112a. The transition times of the three comparison signals D1 are different.

[0105] As can be seen from the above, in order to avoid the waveform of the second data signal DA2 being deviated due to factors such as voltage, temperature and circuit parameters, the data signal generation module 111 provided in this application also includes a trigger 1113.

[0106] The flip-flop 1113 is used to output a second data signal DA2 according to the first clock signal CLK1 and the comparison signal D1. The flip-flop 1113 involved in this application embodiment is a flip-flop triggered by the rising edge (i.e., the moment when it changes from a low level to a high level, or the moment when it changes from "0" to "1"), such as a D flip-flop (DFF).

[0107] Specifically, the working principle of the D flip-flop is as follows: At the rising edge of the clock signal, the D flip-flop outputs the signal level received at the data terminal. Before the second rising edge of the clock signal arrives, regardless of whether the input at the data terminal is flipped, the D flip-flop continues to output the signal level at the previous rising edge until the next rising edge of the clock signal, at which point the D flip-flop outputs the signal level received at the second rising edge through the output terminal.

[0108] The above describes the specific structure and working principle of the data signal generation module 111. The following will continue to combine... Figure 12 The specific structure and working principle of the clock signal generation module 112 are explained.

[0109] In one embodiment, such as Figure 12 As shown, the clock signal generation module 112 includes a first inverter 1121 and a second inverter 1122. The input terminal of the first inverter 1121 is used to receive the first data signal DA1. The output terminal of the first inverter 1121 is connected to the third input terminal (e.g., the clock terminal CK2) of the data signal generation module 111 and the input terminal of the second inverter 1122. The output terminal of the second inverter 1122 is the second output terminal of the signal parsing circuit 110 and is connected to the clock terminal CK1 of the digital logic circuit 120.

[0110] The first inverter 121 described above is used to invert the first data signal DA1 to output the second clock signal CLK2. That is, the second clock signal CLK2 is the inverted signal of the first data signal DA1.

[0111] The second inverter 1122 is used to invert the first clock signal CLK1 to output the first clock signal CLK1. That is, the first clock signal CLK1 is the inverted signal of the second clock signal CLK2. The first clock signal CLK1 is obtained by inverting the first data signal DA1 twice, so the first clock signal CLK1 and the first data signal DA1 are in phase.

[0112] The following combination Figure 15 The signal waveform shown explains in detail why the clock signal generation module 112 performs two phase inversions on the first data signal DA1.

[0113] like Figure 15 As shown, by comparing the waveforms of the first data signal DA1, the comparison signal D1, and the second clock signal CLK2, it can be seen that if the comparison signal D1 is directly sampled using the first data signal DA1, the comparison signal D1 is in a low-level state at both rising edges of the first data signal DA1, and the high level of the comparison signal D1 cannot be accurately sampled. Therefore, the first data signal DA1 needs to be inverted so that the rising edge of the second clock signal CLK2 can accurately sample both the high and low levels of the comparison signal D1.

[0114] The second data signal DA2 is obtained by sampling the comparison signal D1 using the second clock signal CLK2. Comparing the waveforms of the second clock signal CLK2 and the second data signal DA2 reveals that if the second clock signal CLK2 continues to sample the second data signal DA2, the transition edge (e.g., rising edge) of the second clock signal CLK2 will coincide with the transition edge (e.g., rising edge) of the second data signal DA2. In this case, the second data signal DA2 is in the transition region and cannot provide a stable time window for data sampling, leading to sampling errors. Therefore, the second clock signal CLK2 needs to be inverted again so that the first clock signal CLK1 can sample the second data signal DA2 after the transition has ended and during a stable high-level process, thus outputting a stable drive signal.

[0115] It is understood that the embodiment of this application uses a rising edge sampling D flip-flop as an example to illustrate the signal generation process. If the flip-flop 1113 is triggered by a falling edge, the circuit structure of the clock signal generation module 112 can be changed accordingly. For example, the clock signal generation module 112 can include only one inverter. In this case, the first data signal DA1 can be directly used as the clock signal of the flip-flop 1113. The inverter inverts the first data signal DA1 and outputs it to the digital logic circuit 120 as the clock signal of the digital logic circuit 120.

[0116] This application embodiment also provides a display module, which includes a display driver chip and a display array. The display driver chip is used to drive the display array according to a drive signal. This display module can be... Figure 8 The display module 1103 is shown. The specific working principle of this display module has been described above and will not be repeated here.

[0117] This application also provides a lamp driver integrated chip, which includes a display driver chip and at least one set of lamps. The output terminal of the display driver chip is connected to the drive signal input terminal of the at least one set of lamps. The clock data pin of the lamp driver integrated chip is the data terminal of the display driver chip and is used to receive a first data signal. The first power supply pin of the lamp driver integrated chip is the power supply terminal of the display driver chip, and the second power supply pin of the lamp driver integrated chip is the power supply terminal of the at least one set of lamps. The structure of this lamp driver integrated chip can be referred to the above. Figure 7 The lamp driver integrated chip 1101 is shown. This display driver chip can be referenced from the above. Figure 9 , Figure 10 and Figure 12 The display driver chip 100 shown in any of the attached figures will not be described in detail here.

[0118] This application embodiment also provides a display panel, which includes multiple coupled lamp driver integrated chips, or includes at least one such as display module 1103. The structure of the lamp driver integrated chip can be referred to the above. Figure 7 The lamp driver integrated chip 1101 is shown. The structure of this display panel can be referenced. Figure 8 As shown, you can also refer to... Figure 5 As shown, and related descriptions can be found here. Figure 5 and Figure 8 The relevant descriptions will not be repeated here.

[0119] The above detailed description of the display driver chip 100 and the analysis of its beneficial effects can be applied to the display module, the integrated lamp driver chip, and the display panel, and will not be repeated here in the embodiments of this application.

[0120] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0121] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display driver chip, characterized in that, include: Signal analysis circuits and digital logic circuits; The first input terminal of the signal analysis circuit is used to receive a reference voltage, the second input terminal of the signal analysis circuit is the data terminal of the display driver chip, the first output terminal of the signal analysis circuit is connected to the data terminal of the digital logic circuit, and the second output terminal of the signal analysis circuit is connected to the clock terminal of the digital logic circuit. The signal parsing circuit is used to generate a second data signal and a first clock signal based on the received first data signal and the reference voltage, respectively. The digital logic circuit is used to output a drive signal based on the second data signal and the first clock signal.

2. The display driver chip according to claim 1, characterized in that, The first data signal has a first pulse width indicating first data and a second pulse width indicating second data, wherein the first pulse width is different from the second pulse width.

3. The display driver chip according to claim 1, characterized in that, The signal parsing circuit includes a data signal generation module and a clock signal generation module; The first input terminal of the data signal generation module is used to receive the reference voltage. The second input terminal of the data signal generation module and the input terminal of the clock signal generation module are connected together to form the second input terminal of the signal analysis circuit. The third input terminal of the data signal generation module is connected to the first output terminal of the clock signal generation module. The output terminal of the data signal generation module is the first output terminal of the signal analysis circuit, and the second output terminal of the clock signal generation module is the second output terminal of the signal analysis circuit. The clock signal generation module is used to generate a first clock signal and a second clock signal based on the first data signal, wherein the second clock signal is the inverted signal of the first clock signal; The data signal generation module is used to generate the second data signal based on the reference voltage, the first data signal, and the second clock signal.

4. The display driver chip according to claim 3, characterized in that, The data signal generation module includes an integration unit, a comparison unit, and a flip-flop. The input terminal of the integration unit is used to receive the first data signal, the output terminal of the integration unit is connected to the first input terminal of the comparison unit, the second input terminal of the comparison unit is used to receive the reference voltage, the output terminal of the comparison unit is connected to the data terminal of the flip-flop, the clock terminal of the flip-flop is used to receive the second clock signal, and the output terminal of the flip-flop is the first output terminal of the signal parsing circuit. The integration unit is used to generate an integrated signal based on the first data signal; The comparison unit is configured to generate a comparison signal based on the reference voltage and the integral signal; The trigger is used to output the second data signal according to the second clock signal and the comparison signal.

5. The display driver chip according to claim 4, characterized in that, The integration unit includes a first buffer and an integration subunit. The input terminal of the first buffer is used to receive the first data signal, and the output terminal of the first buffer is connected to the input terminal of the integration subunit.

6. The display driver chip according to claim 4, characterized in that, The comparison unit includes a second buffer and a hysteresis comparator. The non-inverting input of the hysteresis comparator is connected to the output of the integration unit. The inverting input of the hysteresis comparator is used to receive the reference voltage. The output of the hysteresis comparator is connected to the input of the second buffer. The output of the second buffer is connected to the data terminal of the trigger.

7. The display driver chip according to claim 3, characterized in that, The clock signal generation module includes a first inverter and a second inverter. The input terminal of the first inverter is used to receive the first data signal. The output terminal of the first inverter is connected to the third input terminal of the data signal generation module and the input terminal of the second inverter, respectively. The output terminal of the second inverter is the second output terminal of the signal parsing circuit. The first inverter is used to invert the first data signal to output the second clock signal; The second inverter is used to invert the second clock signal to output the first clock signal.

8. The display driver chip according to any one of claims 1-7, characterized in that, The display driver chip further includes a voltage generation circuit; the input terminal of the voltage generation circuit is the power supply terminal of the display driver chip, and the output terminal of the voltage generation circuit is connected to the first input terminal of the signal analysis circuit. The voltage generation circuit is used to generate the reference voltage based on the power supply voltage.

9. A display module, characterized in that, The display module includes a display driver chip as described in any one of claims 1 to 8, and a display array, wherein the display driver chip is used to drive the display array according to the drive signal.

10. A lamp driver integrated chip, characterized in that, The integrated lamp driver chip includes the display driver chip according to any one of claims 1 to 8, and at least one set of lamps; the output terminal of the display driver chip is connected to the drive signal input terminal of the at least one set of lamps; The clock data pin of the integrated lamp driver chip is the data terminal of the display driver chip and is used to receive the first data signal. The first power supply pin of the integrated lamp driver chip is the power supply terminal of the display driver chip, and the second power supply pin of the integrated lamp driver chip is the power supply terminal of the at least one group of lamps.

11. A display panel, characterized in that, The display panel includes a plurality of coupled driver chips as described in claim 10, or the display panel includes at least one display module as described in claim 9.

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