A lamp driver chip, a light-emitting package, and a display device.

Abstract

This disclosure provides an LED driver chip, a light-emitting package, and a display device, relating to the field of display technology. The LED driver chip includes a control circuit and at least one driving circuit connected to the control circuit. The output terminal of the driving circuit is used to connect to a light-emitting diode. The control circuit is configured to receive a clock signal and a data signal, and generate a control signal based on the clock signal and the data signal. The driving circuit is configured to respond to the control signal and generate a driving current based on a first voltage and a second voltage to drive the light-emitting diode to emit light. By eliminating the current reference circuit, the size of the LED driver chip is reduced, which helps to reduce power consumption and improve resolution.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an LED driver chip, a light-emitting package, and a display device. Background Technology

[0002] With the continuous development of display technology, high-resolution, high-brightness, and low-power LED displays are widely used in various fields. Regarding LED display driving technology, in order to achieve finer and higher-quality display effects, the industry is gradually evolving from the traditional passive matrix (PM) driving architecture to an active matrix (AM) driving architecture.

[0003] In AM driver architectures, to achieve higher integration and smaller pixel pitch, a mainstream technical solution is to package the light-emitting diode (LED) chip and the driver chip together to form a "lamp-driver integrated" chip with independent display capabilities. This architecture allows each pixel unit to have its own driving capability and can display independently, effectively avoiding the crosstalk problem in traditional PM architectures.

[0004] However, existing integrated lamp-driver technology has significant limitations. Typically, to ensure the current accuracy and stability of LEDs, each driver chip integrates a temperature-independent reference circuit (BandGap). This reference circuit provides a stable reference current for the current mirror circuit. But in the integrated lamp-driver solution, each pixel unit integrates an independent reference circuit. For example, on a 192*216 resolution display, this means more than 40,000 reference circuits need to operate simultaneously. These redundant reference circuits generate enormous additional power consumption, potentially making the overall screen power consumption 3 to 5 times that of the original lamp board, severely failing to meet the low-power requirements of modern electronic devices. Furthermore, the aforementioned reference circuits are usually complex in structure, requiring a large number of transistors (e.g., 10-20), resistors, and capacitors, thus occupying a large chip area. For chips aiming for miniaturization, such as integrated lamp-drivers, the area of ​​the reference circuit becomes a significant design bottleneck, limiting further reduction in pixel size.

[0005] Therefore, there is an urgent need for a new technical solution to effectively address the problems of high power consumption and large area in the existing "lamp driver integration" solution. Summary of the Invention

[0006] To address the aforementioned technical problems, this disclosure provides an LED driver chip, a light-emitting package, and a display device to reduce the size of the LED driver chip and decrease power consumption.

[0007] In a first aspect, this disclosure provides an LED driver chip, including a control circuit and at least one driver circuit connected to the control circuit. The output terminal of the driver circuit is used to connect to a light-emitting diode (LED). The LED driver chip includes a first clock pin, a first data pin, a first reference power supply pin, and a working power supply pin. The control circuit is connected to the first clock pin and the first data pin of the LED driver chip, and is used to receive clock signals and data signals, and generate scan control signals and pulse control signals based on the clock signals and data signals. The scan control signal terminal of the driver circuit is electrically connected to the control circuit, and is used to receive scan control signals. The pulse control terminal of the driver circuit is electrically connected to the control circuit, and is used to receive pulse control signals. The reference power supply terminal of the driver circuit is connected to the first reference power supply pin of the LED driver chip, and is used to receive a first voltage. The working power supply terminal of the driver circuit is connected to the working power supply pin of the LED driver chip, and is used to receive a second voltage. The driver circuit is configured to generate a drive current based on the scan control signal, the pulse control signal, the first voltage, and the second voltage.

[0008] Optionally, the driving circuit includes a light-emitting control module, a driving module, and a compensation module; the control terminal of the light-emitting control module serves as the pulse control terminal of the driving circuit, used to receive pulse control signals; the first terminal of the light-emitting control module is connected to the first electrode of the light-emitting diode, and the second terminal is connected to the first terminal of the driving module; the second electrode of the light-emitting diode is connected to the working power supply terminal, used to receive a second voltage; the second terminal of the driving module is grounded, and the control terminal of the driving module is connected to the output terminal of the compensation module; the input terminal of the compensation module serves as the reference power supply terminal of the driving circuit, used to receive a first voltage; the control terminal of the compensation module serves as the scan control signal terminal of the driving circuit, used to receive scan control signals.

[0009] Optionally, the driving module includes a first transistor, the light-emitting control module includes a second transistor, or the light-emitting control module includes a TG transmission gate circuit.

[0010] Optionally, the compensation module includes a third transistor, a fourth transistor, a fifth transistor, and a first capacitor. The control terminals of the third transistor and the fourth transistor are connected to the same scan control signal terminal. The first terminal of the third transistor is connected to the operating power supply terminal, and the second terminal is connected to the first terminals of the fourth and fifth transistors. The second terminal of the fourth transistor serves as the output terminal of the compensation module and is electrically connected to the control terminal of the drive module. The second terminal of the fifth transistor is grounded, and the control terminal of the fifth transistor is connected to the reference power supply terminal. The first terminal of the first capacitor is connected to the output terminal of the compensation module, and the second terminal is grounded.

[0011] Optionally, the reference power supply terminal and the working power supply terminal can be multiplexed into the same power supply terminal.

[0012] Optionally, the compensation module includes a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor. The scan control signal terminal includes a first scan control signal terminal and a second scan control signal terminal. The control terminal of the sixth transistor is connected to the first scan control signal terminal, the first terminal is connected to the operating power supply terminal, and the second terminal is connected to the first terminal and the control terminal of the seventh transistor, and is also connected to the control terminal of the drive module. The control terminal of the seventh transistor is connected to the control terminal of the drive module, and the second terminal is connected to the second terminal of the eighth transistor. The first terminal of the eighth transistor is connected to the reference power supply terminal, and the control terminal of the eighth transistor is connected to the second scan control signal terminal. The first terminal of the second capacitor is connected to the output terminal of the compensation module, and the second terminal is grounded.

[0013] Optionally, the driving circuit includes a light-emitting control module, a driving module, a switching module, a compensation module, and a storage module. The control terminal of the light-emitting control module is connected to a pulse control terminal to receive a pulse control signal. The first terminal of the light-emitting control module is connected to a working power supply terminal to receive a second voltage, and the second terminal of the light-emitting control module is connected to a first node. The control terminal of the driving module is connected to a second node, the first terminal is connected to the first node, and the second terminal is connected to the first terminal of the switching module. The control signal generated by the control circuit also includes a light-emitting control signal. The driving circuit includes a light-emitting control signal terminal. The control terminal of the switching module is electrically connected to the light-emitting control signal terminal to receive the light-emitting control signal, and the second terminal is connected to the first electrode of a light-emitting diode, which is grounded. The first input terminal of the compensation module is connected to the first node to receive the second voltage. The second input terminal of the compensation module is connected to a reference power supply terminal to receive the first voltage. The control terminal of the compensation module is connected to a scan control signal terminal to receive the scan control signal. The first output terminal of the compensation module is connected to a third node, and the second output terminal is connected to the second terminal of the driving module. The storage module is connected between the third node and the second node.

[0014] Optionally, the light-emitting control module includes a ninth transistor, the control terminal of which is connected to a pulse control terminal for receiving pulse control signals; the first terminal of the ninth transistor is connected to a working power supply terminal for receiving a second voltage; and the second terminal of the ninth transistor is connected to a first node.

[0015] Optionally, the compensation module includes a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein the control terminals of the tenth, eleventh, and twelfth transistors are connected to the same scan control signal terminal of the control circuit for receiving scan control signals; the first terminal of the eleventh transistor serves as the first input terminal of the compensation module, connected to a first node for receiving a second voltage; the second terminal of the eleventh transistor is connected to a second node; the first terminal of the twelfth transistor serves as the second input terminal of the compensation module, connected to a reference power supply terminal for receiving a first voltage; the second terminal of the twelfth transistor is connected to a third node; the first terminal of the tenth transistor is connected to the third node, and the second terminal is connected to the first terminal of the switching module.

[0016] Optionally, the switching module includes a thirteenth transistor, the control terminal of which is connected to the light emission control signal terminal for receiving the light emission control signal; the first terminal of the thirteenth transistor is connected to the second terminal of the driving module, and the second terminal is connected to the first electrode of the light emission diode.

[0017] Secondly, based on the same inventive concept, this disclosure also provides a light-emitting package, including a light-emitting diode and a lamp driver chip as provided in the first aspect, wherein the lamp driver chip is electrically connected to the light-emitting diode, and the lamp driver chip and the light-emitting diode are packaged in the same package.

[0018] Optionally, the light-emitting package includes at least one light-emitting diode, and the lamp driver chip includes at least one driving circuit. Different driving circuits are connected to different light-emitting diodes respectively. In the same light-emitting package, different driving circuits correspond to the same first reference power supply pin, which is used to transmit a first voltage to the reference power supply terminal of the driving circuit.

[0019] Thirdly, based on the same inventive concept, this disclosure also provides a display device, including a circuit board and a light-emitting package provided in the second aspect, wherein the light-emitting package is electrically connected to the circuit board; the light-emitting package includes a second clock pin for receiving a clock signal and a second data pin for receiving a data signal; a scan driver chip and a data driver chip are disposed on the circuit board, wherein the second clock pin in the light-emitting package is electrically connected to the scan driver chip and the second data pin is electrically connected to the data driver chip.

[0020] Optionally, the light-emitting package includes a second reference power supply pin for receiving a first voltage, and a power supply chip is provided on the circuit board, with the second reference power supply pin in each light-emitting package connected to the same power supply chip.

[0021] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0022] The LED driver chip, light-emitting package, and display device disclosed herein remove the complex current reference circuit from each light-emitting package, replacing it with a reference power signal (first voltage) as the reference. A driving circuit is introduced, which adjusts the current when the LED is lit based on the first voltage and a second voltage. Since the driving circuit introduced in the LED driver chip is simpler and more efficient in design than the complex reference circuit, and eliminates the original reference circuit, it effectively reduces the overall screen power consumption. By replacing the reference circuit with a smaller and simpler pixel driving circuit, the chip area can be significantly reduced, meeting the urgent miniaturization requirements of the "LED-driver integration" solution. Therefore, the solution provided herein, by using a simplified pixel driving circuit to replace the traditional reference circuit, solves the core problems of large area and high power consumption in existing LED-driver integration chips while achieving the driving function. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 The diagram shown is a structural schematic of an LED driver chip provided in an embodiment of this disclosure.

[0026] Figure 2 The diagram shown is a schematic representation of a drive circuit provided in an embodiment of this disclosure.

[0027] Figure 3 The diagram shown is another structural schematic of the LED driver chip provided in this embodiment of the present disclosure;

[0028] Figure 4 The diagram shown is another structural schematic of the LED driver chip provided in this embodiment of the present disclosure;

[0029] Figure 5 The diagram shown is another structural schematic of the driving circuit provided in an embodiment of this disclosure;

[0030] Figure 6 The diagram shown is another structural schematic of the driving circuit provided in an embodiment of this disclosure;

[0031] Figure 7 The diagram shown is a schematic diagram of a driving circuit provided in an embodiment of this disclosure;

[0032] Figure 8 As shown Figure 7 A driving timing diagram of a driving circuit;

[0033] Figure 9 The diagram shown is another schematic diagram of the driving circuit provided in an embodiment of this disclosure;

[0034] Figure 10 As shown Figure 9 A driving timing diagram of a driving circuit;

[0035] Figure 11 The diagram shown is another structural schematic of the driving circuit provided in an embodiment of this disclosure;

[0036] Figure 12 As shown Figure 11 A detailed structural diagram of the driving circuit;

[0037] Figure 13 As shown Figure 11 Another detailed structural diagram of the driving circuit;

[0038] Figure 14 As shown Figure 11 Another detailed structural diagram of the driving circuit;

[0039] Figure 15 As shown Figure 14 A timing diagram of a driving circuit;

[0040] Figure 16 The diagram shown is a structural schematic of a light-emitting package provided in an embodiment of this disclosure;

[0041] Figure 17 The diagram shown is another structural schematic of the light-emitting package provided in this embodiment of the present disclosure;

[0042] Figure 18 The diagram shown is a structural schematic of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0043] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0044] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0045] Figure 1 The diagram shown is a structural schematic of an LED driver chip provided in an embodiment of this disclosure. Please refer to it. Figure 1 This disclosure provides an LED driver chip 10, including a control circuit 11 and at least one driver circuit 12 connected to the control circuit 11. The output terminal of the driver circuit 12 is used to connect to a light-emitting diode. The LED driver chip 10 includes a first clock pin D01, a first data pin D02, a first reference power supply pin D03, and a working power supply pin D04. The control circuit 11 is connected to the first clock pin D01 and the first data pin D02 of the LED driver chip 11, and is used to receive a clock signal CK and a data signal DI, and generate control signals according to the clock signal CK and the data signal DI. The control signals include a scan control signal SCAN and a pulse control signal PWM. The scan control signal terminal D1 of the driver circuit 12 is electrically connected to the control circuit 11 and is used to receive the scan control signal SCAN. The pulse control terminal D2 of the driver circuit 12 is electrically connected to the control circuit 11 and is used to receive the pulse control signal PWM. The reference power supply terminal D3 of the driver circuit 12 is connected to the first reference power supply pin D03 of the LED driver chip 10 and is used to receive a first voltage Vdata. The operating power supply terminal D4 of the driver circuit 12 is connected to the operating power supply pin D04 of the LED driver chip 10 to receive the second voltage ELVDD. The driver circuit is configured to generate a drive current based on the scan control signal SCAN, the pulse control signal PWM, the first voltage Vdata, and the second voltage ELVDD to drive the LED to emit light. It should be noted that the LED driver chip 10 also includes a ground pin and a power supply pin that provides the first power supply voltage VDD to the control circuit.

[0046] This disclosure employs an integrated design, integrating the control circuit 11 and the driving circuit 12 into the LED driver chip 10. This LED driver chip 30 enables independent driving of the light-emitting diodes, facilitating a unified lamp-driver solution. This architecture effectively avoids crosstalk problems found in traditional driving architectures. The control circuit 11 in the LED driver chip 10 receives clock and data signals and generates control signals based on these signals. These control signals are responsible for parsing interface data and performing pulse width modulation control, thereby enabling image display with different colors and brightness. The driving circuit 12 responds to the control signals and generates the current driving the light-emitting diode based on a first voltage Vdata and a second voltage ELVDD. Both the first voltage Vdata and the second voltage ELVDD are fixed voltage signals that work together on the driving circuit 12 to generate the current used to drive the light-emitting diode. It should be noted that the voltage values ​​of the first voltage Vdata and the second voltage ELVDD can be adjusted as needed, and this is not limited here.

[0047] In traditional integrated lamp driver solutions, each chip contains a reference circuit (BandGap), leading to a significant increase in overall screen power consumption, which can be 3 to 5 times that of the original lamp board. Furthermore, traditional reference circuits are typically complex, requiring 10-20 transistors and resistors / capacitors, occupying a large chip area. In the lamp driver chip 10 disclosed herein, the complex current reference circuit is removed from each light-emitting package, and a reference power signal (first voltage Vdata) is used instead as the reference. A driver circuit 12 is introduced, which adjusts the current of the light-emitting diode based on the first voltage Vdata and the second voltage ELVDD. Since the driver circuit 12 introduced in the lamp driver chip 10 is simpler and more efficient in design than the complex reference circuit, and eliminates the original reference circuit, it effectively reduces overall screen power consumption. By replacing the reference circuit with a smaller and simpler pixel driver circuit 12, the chip area can be significantly reduced, meeting the urgent miniaturization requirements of the integrated lamp driver solution. Therefore, the solution provided in this disclosure replaces the traditional reference circuit with a simplified pixel driving circuit 12, which solves the core problems of large area and high power consumption of existing integrated lamp driver chips while realizing the driving function.

[0048] The LED driver chip 10 in this disclosure uses a multi-signal coordinated control method to drive the LED to emit light. The scan control signal SCAN and pulse control signal PWM generated by the control circuit 11 are connected to the scan control signal terminal D1 and pulse control terminal D2 of the driver circuit 12, respectively. The operation of the driver circuit 12 no longer relies solely on a single control signal, but achieves more precise control through the combination of two signals. The reference power supply terminal D3 of the driver circuit 12 receives a first voltage Vdata, while the operating power supply terminal D4 receives a second voltage ELVDD. The driver circuit 12 comprehensively utilizes the scan control signal SCAN, the pulse control signal PWM, the first voltage Vdata, and the second voltage ELVDD to generate the drive current. Among them, the scan control signal SCAN may be used to control the driving circuit 12 to turn on or off, and the pulse control signal PWM is used to control the duty cycle and time of the current, thereby realizing grayscale display. The first voltage Vdata is used to adjust the magnitude of the drive current, while the second voltage ELVDD provides power to the LED.

[0049] In this disclosure, by introducing a scan control signal SCAN and a pulse control signal PWM, more complex driving timing and more precise grayscale control can be achieved. The pulse control signal PWM is directly used to realize the grayscale brightness of the image, resulting in better display effects. This scheme tightly integrates the generation of control signals and the generation of driving current within a single chip, simplifying external circuit design and further improving the integration and reliability of the entire system. Although the complex reference circuit is removed in this disclosure, the driving circuit 12, by receiving the first voltage Vdata (as a reference) and the second voltage ELVDD, and in conjunction with its internal design, can achieve precise adjustment of the output current, thus helping to ensure the consistency of the brightness of the entire screen.

[0050] Figure 2 The diagram shown is a schematic representation of a drive circuit 12 provided in an embodiment of this disclosure. Please refer to it. Figure 1 and Figure 2 The driving circuit 12 includes a light-emitting control module 31, a driving module 32, and a compensation module 33. The control terminal of the light-emitting control module 31 serves as the pulse control terminal of the driving circuit 12, used to receive the pulse control signal PWM. The first terminal of the light-emitting control module 31 is connected to the first electrode of the light-emitting diode D0, and the second terminal is connected to the first terminal of the driving module 32. The second electrode of the light-emitting diode D0 is connected to the working power supply terminal of the driving circuit 12, used to receive the second voltage ELVDD. The second terminal of the driving module 32 is grounded to GND, and the control terminal of the driving module 32 is connected to the output terminal of the compensation module 33. The input terminal of the compensation module 33 serves as the reference power supply terminal of the driving circuit 12, used to receive the first voltage Vdata. The control terminal of the compensation module 33 serves as the scan control signal terminal of the driving circuit 12, used to receive the scan control signal SCAN. The compensation module 33 is also connected to the working power supply terminal of the driving circuit 12, used to receive the second voltage ELVDD, and one end of the compensation module 33 is grounded.

[0051] In this disclosure, the control terminal of the light-emitting control module 31 serves as the pulse control terminal D2, receiving the pulse control signal PWM. One end of the light-emitting control module 31 is connected to the light-emitting diode (LED), and the other end is connected to the driver module 32. This indicates that the light-emitting control module 31 can, for example, function as a switch, controlled by the pulse control signal PWM to determine its on / off state, thereby determining the LED's illumination time and achieving grayscale display. One end of the driver module 32 is connected to the light-emitting control module 31, and the other end is grounded. Its control terminal is connected to the output terminal of the compensation module 33. The function of the driver module 32 is to drive the LED to emit light based on the signal from the compensation module 33 and determine the magnitude of the current flowing through the LED. The input terminal of the compensation module 33 is connected to the reference power supply terminal, receiving the first voltage Vdata, and its control terminal is connected to the scan control signal terminal, receiving the scan control signal SCAN. The output terminal of the compensation module 33 is connected to the control terminal of the driver module 32. The compensation module 33 is the core of the entire current generation process. It is responsible for receiving the first voltage Vdata (reference voltage), the scan control signal SCAN, and the second voltage ELVDD, and generating a compensated control voltage. This compensated control voltage overcomes the influence of transistor bias effect or threshold voltage variation, thereby ensuring the accuracy of the output current. In actual operation, the first voltage Vdata and the scan control signal SCAN enter the compensation module 33. The compensation module 33 generates a compensated control signal, which controls the drive module 32. The drive module 32 then drives the light-emitting diode to emit light through the light-emitting control module 31 and the second voltage ELVDD.

[0052] In the driving circuit 12 provided in this embodiment, the modular structure allows each module to perform its specific function. The compensation module 33 is responsible for providing precise control signals, the driving module 32 is responsible for current output, and the light emission control module 31 is responsible for grayscale display. This division of labor and cooperation design improves the overall system reliability. By using independent scan control signals (SCAN and PWM), this scheme can support more flexible and complex driving timing. The scan control signal can be used to control different working stages (such as the compensation stage and the light emission stage), while the pulse signal is used for grayscale control. The two work together to make the driving system more efficient and controllable.

[0053] Please continue to refer to this. Figure 2In one optional embodiment of this disclosure, the driving circuit 12 includes a compensation phase and a light-emitting phase in one refresh cycle. In the compensation phase, the light-emitting control module 31 is turned off according to the pulse control signal PWM, and the compensation module 33 is configured to respond to the scan control signal SCAN and charge the control terminal of the driving module 32 based on the first voltage Vdata and the second voltage ELVDD. In the light-emitting phase, the light-emitting control module 31 is turned on in response to the pulse control signal PWM at its control terminal, so that the driving module 32 generates a driving current based on the signal at its control terminal to drive the light-emitting diode to emit light.

[0054] This embodiment divides the operation of the driving circuit 12 within one refresh cycle into two key stages: a compensation stage and a light-emitting stage. During the compensation stage, the light-emitting control module 31 is in the off state according to the pulse control signal PWM, meaning the LED will not emit light. At this time, the compensation module 33 is activated, responding to the scan control signal SCAN and charging the control terminal of the driving module 32 based on the first voltage Vdata and the second voltage ELVDD. The purpose of this process is to generate a compensated control signal that can correct errors caused by transistor threshold voltage variations or bias effects, ensuring the accuracy and stability of the subsequently generated drive current. After the compensation stage is completed, the system enters the light-emitting stage. At this time, the light-emitting control module 31 responds to the pulse control signal PWM at its control terminal, turning it on. This allows current to flow through the LED. The driving module 32 then generates a stable drive current based on the signal obtained at its control terminal during the compensation stage, thereby driving the LED to emit light.

[0055] In this embodiment, by pre-charging and calibrating the driving module 32 during the compensation phase, the scheme effectively offsets the effects of transistor manufacturing process deviations and voltage fluctuations, ensuring highly accurate and stable driving current generated during the light-emitting phase. This directly solves the display effect problem caused by the low accuracy (±10%) of the reference circuit in traditional schemes. Compared to the traditional scheme where each driving chip integrates a complex and power-consuming reference circuit, this scheme uses a simplified, time-division-enabled compensation module 33 to provide the reference signal. This design not only reduces the area of ​​each chip but also significantly reduces the additional power consumption of the entire screen. Furthermore, dividing a refresh cycle into two independent phases—compensation and light emission—allows for more precise control of the entire driving process. The scan control signal SCAN is used to control the activation of the compensation phase, while the pulse control signal PWM is used for grayscale control during the light emission phase. This collaborative working mode ensures the accuracy and flexibility of pixel brightness adjustment.

[0056] Please refer to Figure 1It should be noted that the LED driver chip 10 may include two power supply signals: a first power supply voltage VDD supplying power to the driver circuit 12, and a second power supply voltage supplying power to the LED driver chip 10, namely the aforementioned second voltage ELVDD. Both are constant voltage signals. The voltage values ​​of the first power supply voltage VDD and the second power supply voltage ELVDD may be the same or different, and this disclosure does not specifically limit this. When the voltage values ​​of the first power supply voltage VDD and the second power supply voltage ELVDD are the same, power supply pin multiplexing can be achieved, thereby reducing the number of pins in the LED driver chip 10 and reducing costs. It should be noted that the first voltage Vdata mentioned in the embodiments of this disclosure is a reference voltage provided to the driver circuit 12, and the second voltage ELVDD may be, for example, the second power supply voltage supplying power to the light-emitting diode.

[0057] Figure 3 and Figure 4 The following are schematic diagrams illustrating another structure of the LED driver chip 10 provided in this embodiment. Optionally, the reference power supply terminal D3 and the working power supply terminal D4 of the driver circuit 12 are multiplexed into the same power supply terminal. That is, the reference power supply terminal D3 and the working power supply terminal D4 can be connected to the same pin of the LED driver chip 10. During the compensation stage, this multiplexed pin simultaneously undertakes the task of providing working power to the driver circuit 12 and providing a reference voltage (first voltage Vdata). By multiplexing the pins, the number of pins required for the chip is reduced. In highly integrated chip designs pursuing miniaturization, a reduction in the number of pins means a smaller package size, simpler layout and wiring, and a higher yield. At the PCB board level, due to the reduction in the number of pins, wiring becomes simpler, saving space and reducing design and manufacturing costs. The reduction in pins also means a reduction in potential noise and interference sources, which helps to improve the signal integrity and stability of the entire display module. In some other embodiments of this disclosure, the reference power supply terminal D3 and the working power supply terminal D4 of the driving circuit 12, as well as the working power supply terminal of the control circuit 11, can be multiplexed into the same power supply terminal and connected to the same pin of the LED driver chip. For example, please refer to [reference needed]. Figure 4 In this way, the same pin undertakes the task of providing power and reference voltage to the drive circuit 12 and providing operating power to the control circuit 11, thereby further reducing the number of pins contained in the lamp driver chip 10.

[0058] Figure 5 and Figure 6 The following are schematic diagrams illustrating another structure of the driving circuit 12 provided in the embodiments of this disclosure. Please refer to them. Figure 5 and Figure 6In one optional embodiment of this disclosure, the driving module 32 includes a first transistor M1, and the light-emitting control module 31 includes a second transistor M2; alternatively, the light-emitting control module 31 includes a TG transmission gate circuit tg. The gate of the first transistor M1 serves as the control terminal of the driving module 32, connected to the output terminal of the compensation module 33; the first electrode of the first transistor M1 serves as the first terminal of the driving module, connected to the light-emitting control module 31; and the second electrode of the first transistor M1 serves as the second terminal of the driving module, grounded. When the light-emitting control module 31 includes the second transistor M2, the gate of the second transistor M2 serves as the control terminal of the light-emitting control module 31, receiving pulse control signals; the first electrode of the second transistor M2 serves as the first terminal of the light-emitting control module 31, connected to the light-emitting diode D0; and the second electrode of the second transistor M2 serves as the second terminal of the light-emitting control module 31, connected to the driving module 32. When the light-emitting control module 31 includes the TG transmission gate circuit tg, the control terminal of the tg transmission gate circuit serves as the control terminal of the light-emitting control module 31 and is used to receive pulse control signals; the first terminal of the tg transmission gate circuit serves as the first terminal of the light-emitting control module 31 and is used to connect to the light-emitting diode D0; the second terminal of the tg transmission gate circuit serves as the second terminal of the light-emitting control module 31 and is used to connect to the driving module 32.

[0059] Optionally, the first transistor M1 is an NMOS transistor, and the second transistor M2 is a PMOS transistor. It should be noted that both the PMOS and NMOS transistors mentioned in this disclosure are four-terminal devices, including a gate, source, drain, and substrate. For NMOS transistors, the substrate is typically connected to a low potential (ground) to ensure reverse bias of the PN junction. For PMOS transistors, the substrate is typically connected to a high potential (power supply), also to ensure reverse bias of the PN junction. This connection method can be referenced for both PMOS and NMOS transistors mentioned below.

[0060] This embodiment details the specific configuration of the driving module 32 and the light-emitting control module 31, and provides two feasible solutions. For the first solution, please refer to... Figure 5 The driving module 32 uses a first transistor M1, and the light-emitting control module 31 uses a second transistor M2. In this configuration, the first transistor M1 may be used to convert a compensated voltage signal into a driving current, while the second transistor M2 acts as a switch, its conduction and cutoff controlled by a pulse control signal (PWM) to achieve grayscale display. This driving circuit 12 has a simple structure and is easy to implement. For the second scheme, please refer to... Figure 6The driving module 32 uses the first transistor M1, and the light-emitting control module 31 uses a TG transmission gate circuit tg. The TG transmission gate consists of an NMOS and a PMOS transistor connected in parallel, offering advantages such as low on-resistance in the on-state and low leakage current in the off-state. Using the TG transmission gate circuit as the light-emitting control module 31 allows for more precise control of current flow, resulting in a more stable light-emitting effect. By providing two optional implementation methods (light-emitting control module 31 using a second transistor or a TG transmission gate), the flexibility of circuit design is improved, allowing the selection of the most suitable solution based on specific application requirements (such as cost, power consumption, and performance requirements). Both implementation methods can be coordinated with the workflow of the compensation and light-emitting stages. In the compensation stage, the light-emitting control module 31 is turned off to charge the voltage; in the light-emitting stage, it turns on in response to a pulse signal, allowing current to flow through the light-emitting diode. This time-sharing operation mode ensures stable and efficient driving.

[0061] In the embodiments provided in this disclosure, the first transistor M1 is an NMOS transistor, and the second transistor M2 is a PMOS transistor, both of which are DNW (Deep N-Well) devices. When the first transistor M1 and the second transistor M2 are configured as DNW devices, for the first transistor M1 using an NMOS transistor, the NMOS is typically placed in a P-type substrate or a P-well. DNW allows for the formation of a deeper N-well on the P-substrate, and then a separate P-well can be fabricated within the N-well to house the NMOS. This structure better isolates the P-well (i.e., the body terminal) of the NMOS from the main substrate, preventing voltage fluctuations or noise from the substrate from coupling to the body terminal of the first transistor M1, thereby stabilizing its threshold voltage and significantly reducing the substrate bias effect. For the second transistor M2 using a PMOS transistor, the PMOS is always placed in an N-well. DNW is used to isolate the N-well containing the PMOS from the P-type substrate. The DNW acts as an electrical shielding layer, effectively preventing substrate noise from being coupled to the N-well (i.e., the body terminal) of the PMOS, thus ensuring the purity and stability of the PMOS body terminal voltage, thereby reducing the substrate bias effect and enhancing the circuit's anti-interference capability.

[0062] Figure 7 The diagram shown is a schematic of a driving circuit 12 provided in an embodiment of this disclosure. Please refer to it. Figure 7In one optional embodiment of this disclosure, the compensation module 33 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a first capacitor C1. The control terminals of the third transistor M3 and the fourth transistor M4 are connected to the same scan control signal terminal to receive the scan control signal SCAN. The first terminal of the third transistor M3 is connected to the operating power supply terminal to receive the second voltage ELVDD, and the second terminal is connected to the first terminals of the fourth transistor M4 and the fifth transistor M5. The second terminal of the fourth transistor M4 serves as the output terminal of the compensation module 33 and is electrically connected to the control terminal of the drive module 32. The second terminal of the fifth transistor M5 is grounded to GND. The control terminal of the fifth transistor M5 is connected to the reference power supply terminal to receive the first voltage Vdata. The first terminal of the first capacitor C1 is connected to the output terminal of the compensation module 33, and the second terminal is grounded to GND. Optionally, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are all ordinary NMOS transistors, and their substrates are all grounded. It should be noted that... Figure 7 The illustrated embodiment is only used as an example of the light emission control module 31 including the second transistor M2. In some other embodiments of this disclosure, the second transistor M2 in the light emission control module 31 can be replaced with a TG transmission gate circuit.

[0063] This embodiment details the specific circuit structure of the compensation module 33. The control terminals of the third transistor M3 and the fourth transistor M4 are connected to the same scan control signal terminal, receiving the same scan control signal SCAN. This means they will be simultaneously controlled by the scan control signal SCAN and work together. The third transistor M3 is connected to the working power supply terminal and the fourth transistor M4 and the fifth transistor M5. The third transistor M3 may act as a switch to introduce the second voltage ELVDD from the working power supply terminal into the compensation circuit. The control terminal of the fifth transistor M5 is connected to the reference power supply terminal and receives the first voltage Vdata, meaning its state is controlled by the first voltage Vdata (reference voltage). The second terminal of the fourth transistor M4 is the output terminal of the compensation module 33, and its output voltage controls the drive module 32. The first capacitor C1 is connected between the output terminal of the compensation module 33 and ground. Its function is to store the compensated voltage and provide a stable control signal to the drive module 32 in the subsequent light-emitting stage. When the control signal arrives, the third transistor M3 is turned on, transferring the voltage of the second voltage ELVDD from the working power supply terminal to the first terminals of the fourth transistor M4 and the fifth transistor M5. Meanwhile, the fifth transistor M5 controls its conduction level based on the first voltage Vdata received at its gate, thereby setting a current. This current flows out through the fourth transistor M4. The first capacitor C1 is connected between the output of the compensation module 33 and ground. When the control signal disappears and the third transistor M3 and the fourth transistor M4 are turned off, the first capacitor C1 maintains its previous voltage, thus providing a stable control voltage for the drive module 32 until the next control signal cycle arrives.

[0064] Please combine Figure 1 and Figure 7 At the start of each drive cycle, the control circuit 11 sends a brief control signal, turning on the third transistor M3 and the fourth transistor M4. At the instant of turn-on, the fifth transistor M5 establishes a specific voltage on the first capacitor C1 based on the external first voltage Vdata. When the control signal disappears, the third transistor M3 and the fourth transistor M4 turn off, and the first capacitor C1 holds this voltage, which is then continuously supplied to the drive module 32 as the output of the compensation module 33. This disclosure cleverly utilizes the instantaneous turn-on of the control signal to "capture" and adjust the voltage, and then uses the first capacitor to "hold" this voltage, thereby converting a periodic signal into a stable DC control voltage. This achieves both a response to the external analog signal Vdata and, through the filtering and holding effect of the capacitor, ensures the stability of the output signal, ultimately providing the drive module 32 with a precise current control reference.

[0065] Figure 8 As shown Figure 7 A driving timing diagram of the driving circuit 12, please refer to... Figure 7and Figure 8 In one optional embodiment of this disclosure, during one refresh cycle, the driving circuit 12 includes a compensation phase T01 and a light-emitting phase T02. In the compensation phase T01, a first voltage Vdata controls the fifth transistor M5 to turn on, a scan control signal SCAN controls the third transistor M3 and the fourth transistor M4 to turn on, a pulse control signal PWM controls the light-emitting control module 31 to turn off, and a second voltage ELVDD charges the first capacitor C1, that is, charges the gate of the first transistor M1. The current generated by the voltage reaching the gate of the first transistor M1 is independent of the Vth of the first transistor M1. Specifically, assuming that the Vth of the first transistor M1, the third transistor M3, and the fifth transistor M5 are the same, and the currents of the third transistor M3 and the fifth transistor M5 are equal, the current can be calculated using the formula I = (1 / 2)μC(W / L)(Vgs-Vth). 2 This yields (ELVDD-Vg-Vth). 2 =4(Vdata-Vth) 2 The high level of the scan control signal SCAN can be the same as the second voltage ELVDD. The W / L (channel width-to-length ratio) of the fifth transistor M5 is four times that of the third transistor M3. Vg is the gate voltage of the first transistor M1, which is also the output voltage of the compensation module 33. Further, we obtain Vg = ELVDD - 2Vdata + Vth. Substituting Vg into the current formula for the first transistor M1, we get I = (1 / 2)μC(W / L)(ELVDD - 2Vdata). 2 This makes the luminous current independent of the transistor's threshold voltage Vth, and only related to ELVDD and Vdata. Even if the threshold voltage of the driving transistor M1 drifts due to manufacturing process or operating time, the luminous current remains stable, thus ensuring the brightness uniformity and lifespan of the OLED display.

[0066] During the light-emitting phase T02, the scan control signal SCAN controls the third transistor M3 and the fourth transistor M4 to turn off. The control circuit transmits a pulse width modulation signal to the light-emitting control module 31, driving the light-emitting diode D0 to emit light. After the compensation phase ends, the control circuit 11 turns off the third transistor M3 and the fourth transistor M4, thereby disconnecting the first capacitor C1 from the working power supply terminal corresponding to the second voltage ELVDD. At this time, the voltage on the first capacitor C1 is locked and stabilized. The control circuit 11 begins to transmit a pulse width modulation signal, i.e., a pulse control signal PWM, to the light-emitting control module 31. The light-emitting control module 31 periodically turns on and off according to the duty cycle of the pulse width modulation signal, using the current set by the voltage held on the first capacitor C1 to drive the light-emitting diode D0. This allows the light-emitting diode D0 to emit light with a precise current within a specific time ratio, thereby achieving high-precision grayscale display.

[0067] In this embodiment, the analog voltage reference setting (completed during the compensation phase) and the digital PWM light emission control (completed during the light emission phase) are completely separated. This decoupling ensures that the two processes do not affect each other, greatly improving the stability and accuracy of the entire drive system. During the compensation phase, since the light emission control module 31 is turned off, no invalid current flows through the light-emitting diode D0. During the light emission phase, the current reference has been established, and the drive module 32 can operate efficiently. Furthermore, since the current generated by the gate voltage of the first transistor M1 is independent of the Vth of the first transistor M1, the substrate bias effect caused by the four-terminal MOS transistor (causing the threshold voltage of the transistor to change with the voltage difference between the source and the substrate) is effectively overcome, thereby improving the light emission accuracy of the light-emitting diode D0.

[0068] Please continue to refer to this. Figure 2 In one optional embodiment of this disclosure, the driving circuit 12 further includes a discharge phase, which occurs after the compensation phase and before the light-emitting phase in a refresh cycle. During the discharge phase, the control terminal of the driving module 32 discharges through the compensation module 33. Thus, during the compensation phase, the driving circuit 12 is configured to charge the control terminal of the driving module 32 to generate a compensated voltage signal. This process aims to correct errors caused by transistor threshold voltage (Vth) and ensure the accuracy of the drive current. The discharge phase follows the compensation phase and precedes the light-emitting phase. In this phase, the control terminal of the driving module 32 discharges through the compensation module 33. This discharge process precisely controls the voltage, ensuring that the voltage at the control terminal of the driving module 32 reaches a specific, stable value independent of the threshold voltage. This prevents overcharging that may occur during the compensation phase and provides a more accurate starting voltage for the light-emitting phase. After the discharge phase is completed, the light-emitting control module 31 is turned on, and the driving module 32 generates a drive current based on the precisely calibrated voltage signal at its control terminal, thereby driving the light-emitting diode D0 to emit light.

[0069] This embodiment, by adding a discharge calibration step before light emission, ensures that the voltage at the control terminal of the drive module 32 reaches a highly accurate preset value. This is more reliable than simply relying on charging because it eliminates errors caused by voltage overshoot or instability, ultimately making the LED luminous current more precise. A precise starting voltage ensures that the current of each pixel is highly consistent during the light emission stage, which is crucial for preventing uneven brightness between pixels, significantly improving the brightness and color uniformity of the entire display screen. This staged driving timing provides the possibility of implementing more complex compensation algorithms. By precisely controlling the timing and amplitude of charging and discharging, this scheme can better adapt to the characteristics of chips under different processes and temperatures, thereby improving overall performance.

[0070] Figure 9 The diagram shown is another circuit diagram of the driving circuit 12 provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 9 In one optional embodiment of this disclosure, the compensation module 33 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a second capacitor C2. The scan control signal terminal D1 includes a first scan control signal terminal D11 and a second scan control signal terminal D12. The control terminal of the sixth transistor M6 is connected to the first scan control signal terminal D11 to receive the first scan control signal SCAN1. The first terminal of the sixth transistor M6 is connected to the working power supply terminal. The working power supply terminal can be, for example, a first power supply voltage VDD that provides power to the control circuit 11, or a second power supply voltage ELVDD that provides power to the drive circuit 12. The first power supply voltage VDD and the second power supply voltage ELVDD can be the same or different. This embodiment is only described with the first terminal of the sixth transistor M6 receiving the first power supply voltage VDD as an example, but it is not limited thereto. The second terminal of the sixth transistor M6 is connected to the first terminal and the control terminal of the seventh transistor M7, and is also connected to the control terminal of the drive module 32; the control terminal of the seventh transistor M7 is connected to the control terminal of the drive module 32, and the second terminal is connected to the second terminal of the eighth transistor M8; the first terminal of the eighth transistor M8 is connected to the reference power supply terminal to receive the first voltage Vdata, and the control terminal of the eighth transistor M8 is connected to the second scan control signal terminal D12 to receive the second scan control signal SCAN2; the first terminal of the second capacitor C2 is connected to the output terminal of the compensation module 33, i.e., the control terminal of the first transistor M1, and the second terminal is grounded to GND.

[0071] In this embodiment, the sixth transistor M6 is controlled to turn on and off by the first scan control signal SCAN1 of the control circuit 11, and is responsible for introducing the voltage VDD from the working power supply terminal into the compensation module 33. The eighth transistor M8 is controlled by the second scan control signal SCAN2 of the control circuit 11 and receives the first voltage Vdata from the reference power supply terminal, which will be used as the basis for adjusting the current reference. When the first scan control signal terminal D11 of the control circuit 11 sends a control signal, the sixth transistor M6 turns on, transferring the voltage VDD from the working power supply terminal to the first terminal of the seventh transistor M7. At this time, the seventh transistor M7 and the eighth transistor M8 form a current mirror or similar circuit structure. The eighth transistor M8 sets a current based on the first voltage Vdata from the reference power supply terminal, and the seventh transistor M7 replicates this current. The second capacitor C2 is connected between the output terminal of the compensation module 33 and ground, and its function is to maintain voltage stability. When the sixth transistor M6 is turned off, the second capacitor C2 will maintain this voltage, thereby providing a stable control signal for the drive module 32. The control terminal, i.e., the gate, of the seventh transistor M7 is directly connected to the control terminal of the drive module 32, i.e., the gate of the first transistor M1. The seventh transistor M7 directly controls the gate voltage of the first transistor M1 in the drive module 32. Connecting the gate of the seventh transistor M7 directly to the gate of the first transistor M1 allows for a more direct and precise current mirroring, ensuring that the output current of the drive module 32 is highly consistent with the current set by the eighth transistor M8. By using two independent scan control signal terminals D1 of the control circuit 11 to control the sixth transistor M6 and the eighth transistor M8 respectively, more complex timing control can be achieved, such as setting the reference current first and then sampling the voltage. The gate voltage of the eighth transistor M8 is used to precisely set the current, and this setting is transmitted to the drive module 32 via the seventh transistor M7, thus achieving a high-precision current reference.

[0072] Optionally, in this embodiment, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all NMOS transistors, and their substrates are all grounded. It should be noted that the light-emitting control module 31 in this embodiment is illustrated using the TG transmission gate as an example, but it is not limited to this and the second transistor M2 can also be used.

[0073] Figure 10 As shown Figure 9 Please refer to one of the driving timing diagrams for the driving circuit 12. Figure 10 In one optional embodiment of this disclosure, during a refresh cycle, the driving circuit 12 includes a compensation phase T11, a discharge phase T12, and a light emission phase T13.

[0074] During the compensation phase T11, the first scan control signal SCAN1 is sent to the sixth transistor M6, turning it on. This allows the second capacitor C2 to be charged via the voltage VDD at the operating power supply terminal, and also turns on the seventh transistor M7. The purpose of this phase is to rapidly charge capacitor C2, establishing an initial, approximate voltage value. This provides the foundation for subsequent precise compensation.

[0075] During the discharge phase T12, a second scan control signal SCAN2 is sent to the eighth transistor M8, causing it to turn on. The second capacitor C2 discharges through the seventh transistor M7 and the eighth transistor M8. The speed and extent of the discharge depend on the conduction level of the eighth transistor M8, which in turn is controlled by the first voltage Vdata in the reference power supply. Using an externally voltage-controlled discharge path, the voltage on the second capacitor C2 is precisely adjusted to eventually stabilize at a precise value proportional to the first voltage Vdata signal. Specifically, the second capacitor C2 discharges through the seventh transistor M7 and the eighth transistor M8 until the gate voltage of the first transistor M1 is too low, causing the seventh transistor M7 to turn off. At this point, the gate voltage of the first transistor M1 is VA = (Vdata + Vth). As shown by the current formula, the current at this point is independent of Vth: I = (1 / 2)μC(W / L)(VA - Vth). 2 =(1 / 2)μC(W / L)(Vdata+Vth-Vth) 2 = (1 / 2)μC(W / L)Vdata 2 This effectively avoids the bias effect caused by four-terminal devices. Even if the threshold voltage of the driving transistor M1 drifts due to manufacturing process or operating time, the luminous current can remain stable, thus ensuring the brightness uniformity and lifespan of the OLED display.

[0076] During the light-emitting stage, both the sixth transistor M6 and the eighth transistor M8 are turned off, transmitting a pulse width modulation (PWM) signal to the light-emitting control module 31 to drive the light-emitting diode D0 to emit light. The light-emitting control module 31 periodically turns on and off according to the duty cycle of the PWM signal, using the current set by the voltage locked on the second capacitor C2 to drive the light-emitting diode D0.

[0077] This disclosure achieves a more accurate voltage reference than simple sampling by first rapidly initializing and then compensating through controlled discharge. This solves the previously mentioned problem of insufficient reference accuracy. Separating the initialization and discharge phases allows for independent control of the duration of each phase, thereby optimizing the charging and discharging process for optimal performance. During the light-emitting phase, since the current reference has been locked through precise adjustments in the two phases, the current of the light-emitting diode D0 will be very stable, ensuring high consistency and uniformity of display brightness.

[0078] Figure 11 The diagram shown is another structural schematic of the driving circuit 12 provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 11 In one optional embodiment of this disclosure, the driving circuit 12 includes a light-emitting control module 31, a driving module 32, a switching module 34, a compensation module 33, and a storage module 35. The control terminal of the light-emitting control module 31 is connected to the pulse control terminal to receive the pulse control signal PWM. The first terminal of the light-emitting control module 31 is connected to the working power supply terminal to receive the second voltage ELVDD. The second terminal of the light-emitting control module 31 is connected to the first node N1. The control terminal of the driving module 32 is connected to the second node N2, the first terminal is connected to the first node N1, and the second terminal is connected to the first terminal of the switching module 34. The control signal generated by the control circuit 11 also includes a light-emitting control signal EM. The driving circuit 12 includes a light-emitting control signal terminal. The control terminal of the switching module is electrically connected to the light-emitting control signal terminal to receive the light-emitting control signal EM. The second terminal of the switch module 34 is connected to the first terminal of the light-emitting diode D0, and the second terminal of the light-emitting diode D0 is grounded; the first input terminal of the compensation module 33 is connected to the first node N1 to receive the second voltage ELVDD; the second input terminal of the compensation module 33 is connected to the reference power supply terminal to receive the first voltage Vdata; the control terminal of the compensation module 33 is connected to the scan control signal terminal to receive the scan control signal SCAN; the first output terminal of the compensation module 33 is connected to the third node N3; and the second output terminal is connected to the second terminal of the drive module 32. The storage module 35 is connected between the third node N3 and the second node N2.

[0079] In this embodiment, the light-emitting control module 31 is no longer directly connected to the light-emitting diode D0, but is connected between the operating power supply terminal of the driving circuit 12 and the first node N1. Its control terminal receives a pulse width modulation (PWM) signal. Its function is to control the current flow to the driving module 32. The control terminal of the driving module 32 is connected to the second node N2, its first terminal is connected to the first node N1, and its second terminal is connected to the switching module 34. The driving module 32 is responsible for precisely adjusting the current flowing from the first node N1 to the switching module 34 according to the voltage of the second node N2. The control terminal of the switching module 34 is connected to the light-emitting control signal terminal of the control circuit 11, and its second terminal is directly connected to the light-emitting diode D0. Its function is the final "light-emitting" switch, and the control circuit 11 determines whether current is allowed to flow through the light-emitting diode D0. The compensation module 33 is the current reference source for the entire scheme. It uses the voltage of the first node N1 as the voltage of the first input terminal, the first voltage Vdata of the reference power supply terminal as the input voltage of the second input terminal, and receives the scan control signal SCAN from the control circuit 11. The first output terminal is connected to the third node N3, and the second output terminal is connected to the second terminal of the drive module 32. A storage module 35 is connected between the third node N3 and the second node N2. Optionally, the storage module is a third capacitor.

[0080] Under the control of the control circuit 11, the compensation module 33 receives the voltage at the first node N1 and the first voltage Vdata at the reference power supply terminal. Based on these two inputs, it generates a stable control voltage at the third node N3 and stores it in the storage module 35. The control terminal of the drive module 32 receives the voltage from the storage module 35, thereby precisely setting the magnitude of the current flowing from the first node N1. The light-emitting control module 31 and the switching module 34 work together, both controlled by the control circuit 11. The light-emitting control module 31 controls whether current enters the drive module 32, while the switching module 34 ultimately determines whether current flows to the light-emitting diode D0. This dual control can be used for finer timing control.

[0081] In this embodiment, the compensation module 33 receives the second voltage ELVDD and the first voltage Vdata, and is controlled by the scan control signal SCAN. This multi-input compensation mechanism can more comprehensively correct various errors (such as transistor threshold voltage and power supply fluctuations), thereby generating a more accurate and stable drive signal. The storage module 35 can store the accurate voltage generated by the compensation module 33 and provide a stable control signal to the drive module 32 during the light-emitting phase. This ensures that the drive current of the light-emitting diode remains stable throughout the entire light-emitting cycle, thereby improving display quality and uniformity.

[0082] This embodiment further separates the current drive and the final light-emitting switch by introducing a separate switching module. This layered design makes the control more flexible and precise, enabling the resolution of more complex display performance issues, such as preventing minute currents from flowing through the LEDs during the compensation phase or optimizing the driving timing.

[0083] Please continue to refer to this. Figure 11 In one optional embodiment of this disclosure, in one refresh cycle, the driving circuit 12 includes an initialization phase, a compensation phase, and an illumination phase. In the initialization phase, the compensation module 33 is configured to charge the third node N3 through the first voltage Vdata of the reference power supply terminal and charge the second node N2 through the second voltage ELVDD of the working power supply terminal to charge the storage module 35. In the compensation phase, the storage module 35 is configured to discharge through the second node N2. In the illumination phase, the illumination control module 31 is configured to respond to the pulse control signal PWM of the pulse control terminal D2 and transmit the second voltage ELVDD of the working power supply terminal to the driving module 32. The driving module 32 generates a driving current according to the signal of the second node N2 and the second voltage ELVDD. The switching module 34 turns on in response to the illumination control signal and provides the driving current to the light-emitting diode.

[0084] The initialization phase in this embodiment can be considered a preparation phase. During initialization, the compensation module 33 charges the third node N3 using the first voltage Vdata from the reference power supply terminal and charges the second node N2 using the second voltage ELVDD from the working power supply terminal. This process aims to provide initial charge to the storage module 35, laying the foundation for the subsequent compensation and light-emitting phases. After initialization, the system enters the compensation phase. At this time, the storage module 35 discharges through the second node N2. This discharge process is a crucial calibration step, ensuring that the voltage on the storage module 35 reaches an accurate value independent of the transistor threshold voltage, providing a stable control signal to the drive module 32. The light-emitting phase is the final display phase. The light-emitting control module 31 responds to the pulse control signal PWM and transmits the second voltage ELVDD to the drive module 32. Simultaneously, the drive module 32 generates a drive current based on the accurate signal and the second voltage ELVDD obtained by the storage module 35 during the compensation phase. Finally, the switching module turns on in response to the light-emitting control signal, providing the drive current to the light-emitting diode to emit light.

[0085] This embodiment, by adding initialization and discharge calibration before emission, ensures that the control signal of the driving module reaches a highly precise voltage value. This not only offsets the effects of transistor manufacturing process deviations but also eliminates voltage overshoot or instability, resulting in a highly accurate and stable final driving current. This is crucial for ensuring the uniformity of brightness and color across the entire screen. Precise starting voltage and stable driving current ensure consistent performance of each pixel during the emission phase, effectively avoiding uneven pixel brightness and significantly improving display quality. Furthermore, this instantiation subdivides a refresh cycle into three independent stages: initialization, compensation, and emission, making the control of the entire driving process more precise and flexible. This time-sharing working mode provides the possibility of implementing more complex compensation algorithms and display modes.

[0086] Figure 12 As shown Figure 11 Please refer to a detailed structural diagram of the drive circuit 12. Figure 12 In one optional embodiment of this disclosure, the light-emitting control module 31 includes a ninth transistor M9. The control terminal of the ninth transistor M9 is connected to a pulse control terminal to receive a pulse control signal PWM. The high and low levels of the pulse control signal PWM control the conduction and cutoff of the transistor, thereby acting as a switch. The first terminal of the ninth transistor M9 is connected to the operating power supply terminal to receive a second voltage ELVDD; the second terminal of the ninth transistor M9 is connected to a first node N1. When the ninth transistor M9 is turned on, the second voltage ELVDD is transmitted to its second terminal, i.e., the first node N1. By using the ninth transistor M9 as a switch and controlling it with the pulse control signal PWM, precise control of the lighting time of the light-emitting diode (LED) can be achieved. The duty cycle of the pulse control signal PWM determines the brightness of the LED, thereby achieving high-precision grayscale display. The simple structure of the ninth transistor M9 results in a small footprint and low power consumption. Compared with using more complex circuits to control the power supply, this direct switching control method is more efficient and helps to reduce the overall power consumption and area of ​​the chip. The switching characteristics of this transistor perfectly match the phased operation mode. During the compensation or discharge phase, the pulse control signal PWM can turn off the ninth transistor M9, thereby cutting off the transmission of the second voltage ELVDD and creating conditions for calibration operations of other modules. During the light-emitting phase, it can turn on, allowing current to flow and driving the LED to emit light.

[0087] Figure 13 As shown Figure 11Another detailed structural diagram of the driving circuit 12 is shown. In an optional embodiment of this disclosure, the compensation module 33 includes a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The control terminals of the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are connected to the same scan control signal terminal of the control circuit 11 to receive the scan control signal SCAN. The first terminal of the eleventh transistor M11 serves as the first input terminal of the compensation module 33 and is connected to the first node N1 to receive the second voltage ELVDD. The second terminal of the eleventh transistor M11 is connected to the second node N2. The first terminal of the twelfth transistor M12 serves as the second input terminal of the compensation module 33 and is connected to the reference power supply terminal to receive the first voltage Vdata. The second terminal of the twelfth transistor M12 is connected to the third node N3. The first terminal of the tenth transistor M10 is connected to the third node N3, and the second terminal is connected to the first terminal of the switching module.

[0088] This embodiment further analyzes how the compensation module 33 processes the first voltage Vdata and the second voltage ELVDD through the coordinated operation of three transistors, and ultimately generates a compensation signal. The control terminals of the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are all connected to the same scan control signal terminal. This means that in a specific timing sequence (e.g., the compensation phase), these three transistors will be activated or deactivated simultaneously, forming a synchronous switching array. The eleventh transistor M11 receives the second voltage ELVDD and transmits it to the second node N2. The twelfth transistor M12 receives the first voltage Vdata and transmits it to the third node N3. One end of the tenth transistor M10 is connected to the third node N3, and the other end is connected to the first terminal of the switching module. This indicates that the output of the compensation module 33 (i.e., the second terminal of the tenth transistor M10) is obtained by processing the voltage on the third node N3. According to the aforementioned scheme, a storage module 35 is connected between the third node N3 and the second node N2, which suggests that the tenth transistor M10 may be used to transmit the calibrated voltage signal from the storage module 35 to the drive module 32.

[0089] By inputting the reference voltage and operating voltage to the compensation module 33, the circuit can perform precise voltage calibration within a specific timing sequence. This design effectively eliminates errors caused by transistor threshold voltage (Vth), thereby ensuring highly accurate final drive current. The three transistors are controlled by the same scan control signal, perfectly matching the time-sharing operation mode (e.g., simultaneously conducting during the compensation phase). This synchronous switching design simplifies and controls the entire drive sequence, and efficiently implements functions for different stages such as charging, discharging, and emission. By encapsulating the compensation function in a module consisting of several transistors, this approach simplifies the overall design and provides possibilities for future functional expansion. This modular design makes the chip easier to debug and manufacture.

[0090] Figure 14 As shown Figure 11 For another detailed structural diagram of the drive circuit 12, please refer to... Figure 14 In one optional embodiment of this disclosure, the switching module 34 includes a thirteenth transistor M13. The control terminal of the thirteenth transistor M13 is connected to the light-emitting control signal terminal to receive the light-emitting control signal. The high or low level of this signal directly controls the conduction and cutoff of the transistor. The first terminal of the thirteenth transistor M13 is connected to the second terminal of the driving module 32, and the second terminal is connected to the first terminal of the light-emitting diode D0. When the thirteenth transistor M13 is turned on, the driving current from the driving module 32 will be transmitted through it. By using an independent transistor as the final switch, this scheme can precisely control the on / off of the driving current according to the light-emitting control signal. This ensures that the LED is driven only during specific light-emitting phases, thereby preventing accidental light emission during compensation or initialization phases and improving the accuracy of display timing. As a "safety gate" for the driving circuit 12, the switching module can effectively isolate the light-emitting diode D0 from the driving module 32. In some cases, it can protect the driving module 32 from possible voltage or current abnormalities at the LED terminal, improving the reliability of the entire system. By introducing an independent light-emitting control signal and switching module, this disclosure enables the scheme to support more complex driving timing. For example, after compensation is complete, the switch can be turned on after a certain period to ensure that all voltages have stabilized, thereby achieving more precise pixel control. This solution encapsulates the switching function in a simple transistor module. This modular design makes the circuit structure clearer and easier to understand, implement, and debug.

[0091] Figure 15 As shown Figure 14 Please refer to one timing diagram of the driver circuit 12. Figure 14 and Figure 15 In one optional embodiment of this disclosure, during a refresh cycle, the driving circuit 12 includes an initialization phase T21, a compensation phase T22, and a light emission phase T23.

[0092] During the initialization phase T21, control circuit 11 sends a constant-level signal to the pulse control terminal and control signals to the control terminals of the tenth transistor M10, eleventh transistor M11, twelfth transistor M12, and thirteenth transistor M13. This controls the ninth transistor M9, eleventh transistor M11, and twelfth transistor M12 to turn on, and controls the tenth transistor M10 and thirteenth transistor M13 to turn off. The third node N3 is charged using the first voltage Vdata at the reference power supply terminal, setting the voltage at the third node N3 to an initial value controlled by the reference voltage; specifically, the third node N3 is charged to Vdata. The second node N2 is also charged using the second voltage ELVDD at the working power supply terminal; specifically, the second node N2 is charged to ELVDD. This provides the initial voltage for subsequent discharge compensation.

[0093] During the compensation phase T22, control circuit 11 controls the eleventh transistor M11 and the thirteenth transistor M13 to conduct, and controls the ninth transistor M9 to turn off. The second node N2 discharges through the eleventh transistor M11, the first transistor M1, and the thirteenth transistor M13. Using a controlled discharge process, the voltage at the second node N2 is precisely fine-tuned, eventually stabilizing at a precise value, for example, Vf + Vth, where Vf is the turn-on voltage of the LED D0, and Vth is the threshold voltage of the first transistor M1. The voltage at the third node N3 is Vdata, and the voltage stored in the third capacitor C3 is Vf + Vth - Vdata. That is, the third capacitor C3 stores a compensation voltage related to the turn-on voltage of the LED D0 and the threshold voltage of the first transistor M1.

[0094] During the light-emitting stage T23, the control circuit 11 controls the eleventh transistor M11 and the twelfth transistor M12 to be turned off, and controls the ninth transistor M9, the tenth transistor M10 and the thirteenth transistor M13 to be turned on. The control circuit 11 transmits a pulse width modulation signal to the light-emitting control module 31 to drive the light-emitting diode D0 to emit light.

[0095] During the light-emitting phase, the voltage at the third node N3 is raised to the light-emitting voltage Vled of the LED D0. At this time, the voltage at the third node N3 is Vled. Since the capacitance of the third capacitor C3 remains unchanged, the voltage at the second node N2 is Vled + (Vf + Vth - Vdata). The gate-source voltage of the first transistor M1 is Vgs = VB - VA = Vled + Vf + Vth - Vdata - Vled = Vf + Vth - Vdata. The light-emitting current at this time is I = (1 / 2)μC (W / L))(Vgs - Vth). 2 =(1 / 2)μC(W / L)(Vf+Vth-Vdata-Vth)2 = (1 / 2)μC(W / L)(Vf-Vdata) 2 Similarly, this ensures that the luminous current is not affected by the threshold voltage, thus guaranteeing that the luminous current is independent of the inherent characteristics of the first transistor M1, which is beneficial for improving the luminous uniformity and stability of the light-emitting diode D0.

[0096] By employing a "charge first, then discharge for compensation" strategy, a more accurate reference voltage can be achieved than simple sampling. This solves the accuracy problem of traditional solutions. During the light-emitting phase, because the current reference has been locked through a complex two-stage adjustment, the current of the LED will be very stable, thus ensuring a high degree of consistency in display brightness and color. Dividing the entire process into three stages allows designers to independently control the duration of each stage, thereby optimizing the charging, discharging, and light-emitting processes to achieve optimal performance.

[0097] Secondly, based on the same inventive concept, this disclosure also provides a light-emitting package 100. Figure 16 The diagram shown is a structural schematic of a light-emitting package 100 provided in an embodiment of this disclosure. Please refer to it. Figure 16 The light-emitting package 100 includes a light-emitting diode (LED) D0 and a lamp driver chip 10 as provided in the first aspect. The lamp driver chip 10 is electrically connected to the LED D0, and the lamp driver chip 10 and the LED D0 are packaged in the same package. The light-emitting package 100 and the lamp driver chip 10 have the same technical effects; by removing redundant reference circuitry, the display screen composed of this light-emitting package can significantly reduce overall screen power consumption. Due to the reduced area of ​​the lamp driver chip 10, the package can achieve a smaller pixel pitch (dot pitch), meeting the development trend of high resolution and miniaturization of LED displays. Furthermore, packaging the LED and the lamp driver chip together improves the overall integration, shortens the current transmission path, and reduces external wiring and solder points, thereby improving product reliability and anti-interference capabilities. The phased compensation mechanism (initialization, compensation, discharge) inside the chip ensures the stability and accuracy of the driving current, resulting in higher brightness uniformity and color consistency when the package is displayed. Moreover, as an "integrated lamp and driver" package for active matrix (AM) driving architecture, each pixel unit has independent driving capability, fundamentally avoiding the crosstalk problem in traditional passive matrix (PM) architecture.

[0098] Figure 17 The diagram shown is another structural schematic of the light-emitting package provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 17In one optional embodiment of this disclosure, the light-emitting package includes at least one light-emitting diode (LED) D0, and the LED driver chip 10 includes at least one driving circuit 12. Different driving circuits 12 are connected to different LEDs. This embodiment uses a light-emitting package 100 including two LEDs D0 and two driving circuits 12 as an example, but it is not limited thereto. In the same light-emitting package 100, different driving circuits 12 correspond to the same first reference power supply pin D03. The first reference power supply pin D03 is used to transmit a first voltage Vdata to the reference power supply terminal D3 of the driving circuit 12. When the light-emitting package includes two or more LEDs, the LED driver chip 10 provides different driving circuits 12 for each LED D0, thus enabling independent driving of different LEDs. Optionally, a light-emitting package contains three LEDs, and the three LEDs emit red, green, and blue light, respectively. Of course, in some other embodiments of this disclosure, a light-emitting package may also contain more than three LEDs.

[0099] In this embodiment, within the same light-emitting package 100, different driving circuits 12 correspond to the same first reference power supply pin D03. This first reference power supply pin D03 is used to transmit the first voltage Vdata (reference voltage) to the reference power supply terminal of all driving circuits 12. Traditional "lamp-driver integration" solutions integrate an independent, high-power reference circuit (BandGap) for each driving circuit 12. This solution provides the reference voltage (first voltage Vdata) by sharing an externally introduced reference power supply pin, completely eliminating redundant reference circuits within the chip, thereby minimizing the power consumption of each pixel. This directly solves the serious problem in existing solutions where the overall screen power consumption reaches 3 to 5 times that of the original lamp board. Traditional reference circuits are complex and bulky. By removing the complex reference circuits inside the chip and adopting a pin multiplexing design, the space for transistors and wiring inside the chip is greatly freed up, thereby minimizing the chip area and providing a key technical guarantee for achieving smaller pixel pitch. Regardless of the number of driving circuits in a package (e.g., driving three LEDs R, G, and B), only one first reference power supply pin D03 needs to be shared. This pin reuse design effectively reduces the number of pins in the package, simplifies chip design and subsequent PCB routing, and reduces the overall cost and complexity of the system.

[0100] Thirdly, based on the same inventive concept, this disclosure also provides a display device 200. Figure 18The diagram shows a schematic representation of a display device according to an embodiment of this disclosure. The display device 200 includes a circuit board 00 and a light-emitting package 100 provided in the second aspect. The light-emitting package is electrically connected to the circuit board. The light-emitting package includes a second clock pin D11 for receiving a clock signal CK and a second data pin D12 for receiving a data signal DI. A scan driver chip 51 and a data driver chip 52 are disposed on the circuit board 00. The second clock pin D11 in the light-emitting package 100 is electrically connected to the scan driver chip 51, and the second data pin D12 is electrically connected to the data driver chip 52. It should be noted that the first clock pin D01 in the LED driver chip 10 is electrically connected to the second clock pin D11 in the light-emitting package 100, and the first clock pin D01 obtains the clock signal through the second clock pin D11. The first data pin D02 in the LED driver chip 10 is electrically connected to the second data pin D12 in the light-emitting package 100, and the first data pin D02 obtains the data signal through the second data pin D12.

[0101] In the display device provided in this disclosure, the scan driver chip (typically used for row selection and timing control) and the data driver chip (used for transmitting pixel data and control signals) work together to transmit control and data signals to the internal LED driver chip through pins on the light-emitting package. Because the core light-emitting package completely eliminates redundant reference circuitry, the overall power consumption of this display device is significantly lower than that of displays using a traditional "lamp-driver integration" solution, solving the high power consumption bottleneck. Thanks to the small-area design of the chip, this display device can use smaller, denser light-emitting packages, thereby achieving higher resolution and smaller pixel pitch Mini / Micro LED display effects. The staged compensation mechanism inside the chip ensures high precision and stability of the output current of each light-emitting package, resulting in extremely high uniformity in brightness and color of the terminal display screen, effectively eliminating moiré patterns. The design of this display device is compatible with existing scan and data driver architectures and can be easily integrated into existing display system designs, exhibiting good compatibility and feasibility.

[0102] It should be noted that the embodiments disclosed herein are only illustrated by the example of a display device including multiple scan driver chips and multiple data driver chips, but are not limited thereto. In some other embodiments of this disclosure, the display device may also include only one scan driver chip and one data driver chip, or the scan driver chip and the data driver chip may be combined into one driver chip.

[0103] Please continue to refer to this. Figure 18In one optional embodiment of this disclosure, the light-emitting package 100 includes a second reference power supply pin D13 for receiving a first voltage Vdata. A power supply chip 50 is disposed on the circuit board 00, and the second reference power supply pin D13 in each light-emitting package is connected to the same power supply chip 50. It should be noted that the second reference power supply pin D13 in the light-emitting package is electrically connected to the first reference power supply pin D03 in the LED driver chip 10, and the first reference power supply pin D03 obtains the first voltage Vdata through the second reference power supply pin D13. The power supply chip 50 on the circuit board 00 is responsible for generating or providing a globally shared, constant, and precise reference voltage (first voltage Vdata), and distributing it to all light-emitting packages 100 on the board through the same wiring network or pin. By allowing all packages to share the reference voltage provided by a single power supply chip, it is ensured that the driving circuits 12 of all pixels on the entire display device use a completely consistent reference. This solves the problem of inconsistent references caused by deviations and temperature drift inherent in the circuit itself when each pixel has its own independent reference circuit in conventional solutions, greatly improving the brightness uniformity and color consistency of the entire screen. Since all the light-emitting packages no longer contain complex, high-power reference circuitry (BandGap), but instead rely on an external power chip on the PCB to provide the reference, this design concentrates the high-power circuitry that was originally scattered across tens of thousands of pixels onto one or a few power chips, achieving system-level energy efficiency optimization and making the overall power consumption of the display device significantly lower than existing technologies.

[0104] It should be noted that the operating power supply pin D14 of the light-emitting package 100 is connected to the operating power supply pin D04 in the lamp driver chip 10, and is used to transmit the second voltage ELVDD to the lamp driver chip 10 to provide power to the driving circuit 12. The ground pin of the light-emitting package 100 is electrically connected to the ground pin of the lamp driver chip 10. The light-emitting package 100 also includes a power supply pin that provides operating power to the control circuit 11, which is connected to the pin in the lamp driver chip 10 that provides operating power to the control circuit.

[0105] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0106] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A lamp bead driving chip, characterized in that, The device includes a control circuit and at least one driving circuit connected to the control circuit, wherein the output terminal of the driving circuit is used to connect to a light-emitting diode; the LED driver chip includes a first clock pin, a first data pin, a first reference power supply pin, and a working power supply pin. The control circuit is connected to the first clock pin and the first data pin of the LED driver chip, and is used to receive clock signals and data signals, and generate scan control signals and pulse control signals according to the clock signals and the data signals; The scanning control signal terminal of the driving circuit is electrically connected to the control circuit and is used to receive the scanning control signal. The pulse control terminal of the driving circuit is electrically connected to the control circuit and is used to receive the pulse control signal. The reference power supply terminal of the driving circuit is connected to the first reference power supply pin of the lamp bead driver chip and is used to receive the first voltage. The power supply terminal of the driving circuit is connected to the power supply pin of the LED driver chip to receive the second voltage; the driving circuit is configured to generate a driving current based on the scan control signal, the pulse control signal, the first voltage, and the second voltage.

2. The lamp bead driving chip according to claim 1, characterized in that, The driving circuit includes a light-emitting control module, a driving module, and a compensation module; The control terminal of the light-emitting control module serves as the pulse control terminal of the driving circuit, used to receive the pulse control signal; the first terminal of the light-emitting control module is connected to the first electrode of the light-emitting diode, and the second terminal is connected to the first terminal of the driving module; the second electrode of the light-emitting diode is connected to the working power supply terminal, used to receive the second voltage; The second terminal of the driving module is grounded, and the control terminal of the driving module is connected to the output terminal of the compensation module; the input terminal of the compensation module serves as the reference power supply terminal of the driving circuit and is used to receive the first voltage; the control terminal of the compensation module serves as the scan control signal terminal of the driving circuit and is used to receive the scan control signal.

3. The LED driver chip according to claim 2, characterized in that, The driving module includes a first transistor, and the light-emitting control module includes a second transistor, or the light-emitting control module includes a TG transmission gate circuit.

4. The LED driver chip according to claim 2, characterized in that, The compensation module includes a third transistor, a fourth transistor, a fifth transistor, and a first capacitor. The control terminals of the third transistor and the fourth transistor are connected to the same scan control signal terminal. The first terminal of the third transistor is connected to the operating power supply terminal, and the second terminal is connected to the first terminals of the fourth and fifth transistors. The second terminal of the fourth transistor serves as the output terminal of the compensation module and is electrically connected to the control terminal of the drive module. The second terminal of the fifth transistor is grounded, and the control terminal of the fifth transistor is connected to the reference power supply terminal. The first terminal of the first capacitor is connected to the output terminal of the compensation module, and the second terminal is grounded.

5. The LED driver chip according to claim 1, characterized in that, The reference power supply terminal and the working power supply terminal are multiplexed as the same power supply terminal.

6. The LED driver chip according to claim 2, characterized in that, The compensation module includes a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor. The scan control signal terminal includes a first scan control signal terminal and a second scan control signal terminal. The control terminal of the sixth transistor is connected to the first scan control signal terminal, the first terminal is connected to the working power supply terminal, and the second terminal is connected to the first terminal and the control terminal of the seventh transistor, and also connected to the control terminal of the driving module. The control terminal of the seventh transistor is connected to the control terminal of the driving module, and the second terminal is connected to the second terminal of the eighth transistor. The first terminal of the eighth transistor is connected to the reference power supply terminal, and the control terminal of the eighth transistor is connected to the second scan control signal terminal. The first terminal of the second capacitor is connected to the output terminal of the compensation module, and the second terminal is grounded.

7. The LED driver chip according to claim 1, characterized in that, The driving circuit includes a light-emitting control module, a driving module, a switching module, a compensation module, and a storage module. The control terminal of the light-emitting control module is connected to the pulse control terminal to receive the pulse control signal. The first terminal of the light-emitting control module is connected to the working power supply terminal to receive the second voltage, and the second terminal of the light-emitting control module is connected to the first node. The control terminal of the driving module is connected to the second node, the first terminal is connected to the first node, and the second terminal is connected to the first terminal of the switching module. The control signal generated by the control circuit also includes a light-emitting control signal. The driving circuit includes a light-emitting control signal terminal. The control terminal of the switching module is electrically connected to the light-emitting control signal terminal to receive the light-emitting control signal, and the second terminal is connected to the first electrode of the light-emitting diode, which is grounded. The first input terminal of the compensation module is connected to the first node to receive the second voltage. The second input terminal of the compensation module is connected to the reference power supply terminal to receive the first voltage. The control terminal of the compensation module is connected to the scan control signal terminal to receive the scan control signal. The first output terminal of the compensation module is connected to the third node, and the second output terminal is connected to the second terminal of the driving module. The storage module is connected between the third node and the second node.

8. The LED driver chip according to claim 7, characterized in that, The light-emitting control module includes a ninth transistor, the control terminal of which is connected to the pulse control terminal for receiving the pulse control signal; the first terminal of the ninth transistor is connected to the working power supply terminal for receiving the second voltage; and the second terminal of the ninth transistor is connected to the first node.

9. The LED driver chip according to claim 7, characterized in that, The compensation module includes a tenth transistor, an eleventh transistor, and a twelfth transistor; The control terminals of the tenth, eleventh, and twelfth transistors are connected to the same scan control signal terminal of the control circuit to receive the scan control signal; the first terminal of the eleventh transistor serves as the first input terminal of the compensation module, connected to the first node, and is used to receive the second voltage; the second terminal of the eleventh transistor is connected to the second node; the first terminal of the twelfth transistor serves as the second input terminal of the compensation module, connected to the reference power supply terminal, and is used to receive the first voltage; the second terminal of the twelfth transistor is connected to the third node; the first terminal of the tenth transistor is connected to the third node, and the second terminal is connected to the first terminal of the switching module.

10. The LED driver chip according to claim 7, characterized in that, The switching module includes a thirteenth transistor, the control terminal of which is connected to the light-emitting control signal terminal for receiving the light-emitting control signal; the first terminal of the thirteenth transistor is connected to the second terminal of the driving module, and the second terminal is connected to the first electrode of the light-emitting diode.

11. A light-emitting encapsulation body, characterized in that, It includes a light-emitting diode and a lamp driver chip as described in any one of claims 1 to 10, wherein the lamp driver chip is electrically connected to the light-emitting diode and the lamp driver chip and the light-emitting diode are packaged in the same package.

12. The light-emitting encapsulation body according to claim 11, characterized in that, The light-emitting package includes at least one light-emitting diode, and the lamp driver chip includes at least one driving circuit. Different driving circuits are connected to different light-emitting diodes. In the same light-emitting package, different driving circuits correspond to the same first reference power supply pin, and the first reference power supply pin is used to transmit the first voltage to the reference power supply terminal of the driving circuit.

13. A display device, characterized in that, Includes a circuit board and a light-emitting package as described in claim 11 or 12, wherein the light-emitting package is electrically connected to the circuit board; The light-emitting package includes a second clock pin for receiving the clock signal and a second data pin for receiving the data signal; The circuit board is provided with a scan driver chip and a data driver chip. The second clock pin in the light-emitting package is electrically connected to the scan driver chip, and the second data pin is electrically connected to the data driver chip.

14. The display device according to claim 13, characterized in that, The light-emitting package includes a second reference power pin for receiving the first voltage, and a power chip is disposed on the circuit board. The second reference power pin in each of the light-emitting packages is connected to the same power chip.

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