Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a gate driving circuit, a pixel driving circuit, and power signal lines. The power signal lines include a first power line, a second power line, and a third power line. The first and second power lines are located in a non-display area, and the third power line is located in the display area. One end of the second power line is connected to the first power line, and the other end of the second power line is electrically connected to the third power line. The other end of the third power line is electrically connected to the pixel driving circuit, and the second power line is located between two adjacent gate driving units. By setting a second power line between two adjacent gate driving units, this application transmits the power signal transmitted by the first power line to the third power line electrically connected to the pixel driving circuit, increasing the transmission path of the power signal, reducing the error of the power signal received by the pixel driving circuit, and improving the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In related technologies, OLED (Organic Light-Emitting Diode) display panels typically include pixel driving circuits and gate driving circuits that output control signals to the pixel driving circuits. The pixel driving circuits need to receive power signals to drive the light-emitting devices to emit light.

[0003] In current OLED display panels, due to the limitation of wiring space, the signal lines that transmit low-level source signals are usually arranged vertically in the non-display area of ​​the display panel. However, due to the influence of the resistance and capacitance in the wires, there is a difference between the low-level source signal output from the signal source and the low-level source signal received by the pixel driving circuit, which leads to display abnormalities in the display panel. Utility Model Content

[0004] This application provides a display panel and display device to solve the technical problem that there are errors in the low-level source signals received by the pixel driving circuit in existing display panels.

[0005] This application embodiment provides a display panel, which includes a display area and a non-display area located on one side of the display area. The display panel includes: A gate driving circuit is located in the non-display area, and the gate driving circuit includes a plurality of gate driving units arranged along a first direction. The pixel driving circuit is located within the display area; The power signal line includes a first power line, a second power line, and a third power line, wherein the first power line and the second power line are located in the non-display area, and the third power line is located in the display area; Wherein, one end of the second power line is connected to the first power line, the other end of the second power line is electrically connected to the third power line, the other end of the third power line is electrically connected to the pixel driving circuit, and the second power line is located between two adjacent gate driving units.

[0006] Optionally, the display panel includes a substrate, a light-shielding layer disposed on the substrate, and an array driving layer disposed on the side of the light-shielding layer away from the substrate, wherein the array driving layer includes the gate driving circuit and the pixel driving circuit. The light-shielding layer includes the third power line.

[0007] Optionally, the third power line includes multiple first sub-lines and multiple second sub-lines electrically connected, the first sub-lines extending along the first direction, the second sub-lines extending along the second direction, and the multiple first sub-lines and the multiple second sub-lines forming a mesh structure.

[0008] Optionally, the light-shielding layer further includes a light-shielding bus extending along the first direction, the light-shielding bus being disposed between the second power line and the third power line, and the end of the second power line near the third power line being electrically connected to the light-shielding bus, and the end of the third power line near the second power line being electrically connected to the light-shielding bus.

[0009] Optionally, the width of each of the light-shielding buses is greater than the width of the third power line and the second power line.

[0010] Optionally, the width of the third power line ranges from 1.0 micrometer to 1.2 micrometers, and the width of the light-shielding bus ranges from 15 micrometers to 20 micrometers.

[0011] Optionally, the width of the first power line is greater than the width of the light-shielding bus.

[0012] Optionally, the array driving layer includes a first gate layer, a second gate layer disposed on the side of the first gate layer away from the substrate, a first source-drain layer disposed on the side of the second gate layer away from the substrate, and a second source-drain layer disposed on the side of the first source-drain layer away from the substrate. The second power line includes multiple third sub-lines that are electrically connected, and all of the multiple third sub-lines extend along a second direction. At least one of the light-shielding layer, the first gate layer, the second gate layer, and the first source-drain layer includes the third sub-lines.

[0013] Optionally, two adjacent third sub-lines are arranged in different layers.

[0014] This application provides a display device, which includes the display panel as described above.

[0015] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0017] Figure 1 This is a simplified diagram of the first possible structure of the display panel in this application.

[0018] Figure 2 This is a structural diagram of the pixel driving circuit in the display panel of this application.

[0019] Figure 3 This is a diagram of the film structure in the display panel of this application.

[0020] Figure 4 This is a diagram of the driving architecture for the display panel in this application.

[0021] Figure 5 This is a stacked diagram of the inner film layers in the non-display area of ​​the display panel of this application.

[0022] Figure 6 This is a simplified diagram of the second structural design of the display panel in this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0024] Please see Figures 1 to 6 This application proposes a display panel 100, which includes a display area AA and a non-display area NA located on one side of the display area AA. The display panel 100 includes a gate driving circuit 300, a pixel driving circuit PC and a power signal line 200. The gate driving circuit 300 is located in the non-display area NA. The gate driving circuit 300 includes a plurality of gate driving units 300a arranged along a first direction X. The pixel driving circuit PC is located in the display area AA.

[0025] In this embodiment, the power signal line 200 includes a first power line 210, a second power line 220, and a third power line 230. The first power line 210 and the second power line 220 are located in the non-display area NA, and the third power line 230 is located in the display area AA.

[0026] In this embodiment, one end of the second power line 220 is connected to the first power line 210, the other end of the second power line 220 is electrically connected to the third power line 230, the other end of the third power line 230 is electrically connected to the pixel driving circuit PC, and the second power line 220 is located between two adjacent gate driving units 300a.

[0027] This application increases the transmission path of the power signal by setting a second power line 220 between two adjacent gate driving units 300a, so as to transmit the power signal transmitted by the first power line 210 to the third power line 230 which is electrically connected to the pixel driving circuit PC. This reduces the error of the power signal received by the pixel driving circuit PC and improves the display effect of the display panel 100.

[0028] It should be noted that the power signal line 200 in this embodiment can be a power line for transmitting a low-level source VSS and a power line for transmitting a high-level source VDD. The following description will take the example of the power signal line 200 being a power line for transmitting a low-level source VSS.

[0029] The technical solution of this application will now be described in conjunction with specific embodiments.

[0030] Please see Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA contains multiple sub-pixels PL. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is enclosed by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in displaying information.

[0031] Please see Figure 1 A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0032] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits (PCs) for driving the LEDs can be arrayed within the display area AA. The pixel driving circuit PC can be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C, etc. This application does not impose specific limitations. The following description uses an 8T2C pixel driving circuit PC as an example.

[0033] Please see Figure 2 The pixel driving circuit PC may include a switching transistor T2A, a driving transistor T1A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, a boost capacitor Cboost, and a control capacitor Csta.

[0034] Please see Figure 2 The first electrode of switching transistor T2A is connected to the data signal line Data, the second electrode of switching transistor T2A is connected to the control node Aa, and the gate of switching transistor T2A receives the switching control signal Scan3; the first electrode of driving transistor T1A is connected to the control node Aa, the second electrode of driving transistor T1A is connected to the control node Ba, and the gate of driving transistor T1A is connected to the control node Qa; the first electrode of compensation transistor T3A is connected to the control node Qa, the second electrode of compensation transistor T3A is connected to the control node Ba, and the gate of compensation transistor T3A receives the compensation control signal Scan1; the first electrode of the first reset transistor T4A receives the first reset signal Vi1, the second electrode of the first reset transistor T4A is connected to the control node Qa, and the gate of the first reset transistor T4A receives the first reset control signal Scan2; the first electrode of the second reset transistor T7A is connected to the second reset signal Vi2, and the second electrode of the second reset transistor T7A receives the first reset control signal Scan2. Two electrodes are connected to the anode of the light-emitting device. The gate of the second reset transistor T7A receives the second reset control signal Scan4. The first electrode of the third reset transistor T8A receives the third reset signal Vi3, and the second electrode of the third reset transistor T8A is connected to the control node Aa. The gate of the third reset transistor T8A receives the third reset control signal Vi3. The first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, and the second electrode of the first light-emitting transistor T5A is connected to the control node Aa. The gate of the first light-emitting transistor T5A receives the light-emitting control signal EM. The first electrode of the second light-emitting transistor T6A is connected to the second node Ba, and the second electrode of the second light-emitting transistor T6A is connected to the anode of the light-emitting device. The gate of the second light-emitting transistor T6A receives the light-emitting control signal EM. One end of the control capacitor Csta is connected to the control node Qa, and the other end of the control capacitor Csta is connected to the high-level source VDD. The cathode of the light-emitting device is connected to the low-level source VSS.

[0035] In this embodiment, the high-level source VDD is used to provide a constant high voltage to the pixel driving circuit PC, and the low-level source VSS is used to provide a constant low voltage to the pixel driving circuit PC.

[0036] In this embodiment, the switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, second light-emitting transistor T6A, compensation transistor T3A, and first reset transistor T4A can be either P-type transistors or N-type transistors. For example, this application uses P-type transistors as an example for illustration.

[0037] It should be noted that the compensation transistor T3A and the first reset transistor T4A in this application can both be constructed as two transistors connected in series to reduce the leakage current of the compensation transistor T3A and the first reset transistor T4A.

[0038] It should be noted that in the actual film stack diagram, the signal line transmitting the high-level source VDD also overlaps with the wire of the transmission control node Aa, and the signal line transmitting the high-level source VDD also overlaps with the node between the two series transistors in the compensation transistor T3A and the first reset transistor T4A, and the node between the two series transistors in the first reset transistor T4A, to form corresponding capacitors to ensure the potential stability of the corresponding nodes.

[0039] In this embodiment, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain.

[0040] The film layer of the display panel 100 of this application is described below.

[0041] Please see Figure 3 The display panel 100 may have a substrate 110 and an array driving layer 120 disposed on the substrate 110 in the display area AA and the non-display area NA. Within the display area AA, the display panel 100 may also have a pixel definition layer (PDL) disposed on the array driving layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer (PDL), and an encapsulation layer (TFE) disposed on the pixel definition layer (PDL). The array driving layer 120 includes the gate driving circuit 300 and the pixel driving circuit (PC). The following mainly describes the film layer structure of the display panel 100.

[0042] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0043] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0044] In this embodiment, the substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 stacked together. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0045] Please see Figure 3 The array driving layer 120 may include multiple thin-film transistors (TFTs). These TFTs may be etch-block type, back-channel etch type, or classified according to the position of the gate and active layer as bottom-gate TFTs, top-gate TFTs, etc., or according to their performance as N-type TFTs, P-type TFTs; among them, Figure 3 The thin-film transistor in the text does not represent Figure 2 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of this application.

[0046] Please see Figure 3 The array driving layer 120 may include a light-shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light-shielding layer 121, an active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, an inter-insulating layer 128 disposed on the second gate layer 127, a first source-drain layer 129 disposed on the inter-insulating layer 128, a first planarization layer 130 disposed on the first source-drain layer 129, a second source-drain layer 131 disposed on the first planarization layer 130, a second planarization layer 132 disposed on the second source-drain layer 131, a light-emitting device layer and a pixel definition layer (PDL) disposed on the second planarization layer 132, and a packaging layer (TFE) disposed on the pixel definition layer (PDL).

[0047] Please see Figure 3The light-shielding layer 121 is disposed on the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material.

[0048] Please see Figure 3 A buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0049] In this embodiment, the light-shielding layer 121 can also be embedded within the buffer layer 122.

[0050] Please see Figure 3 The active layer 123 can be made of silicon semiconductor, for example, in this application the active layer 123 can be made of low-temperature polycrystalline silicon.

[0051] Please see Figure 3 The first gate insulating layer 124, the second gate insulating layer 126, and the interlayer insulating layer 128 are respectively disposed on the corresponding metal layer or semiconductor layer, and are disposed separately with different metal layers or semiconductor layers; and the materials of the first gate insulating layer 124, the second gate insulating layer 126, and the interlayer insulating layer 128 can be inorganic materials composed of at least two elements in silicon oxynitride or organic materials with planarity, or can be stacked single or multiple film layers, such as silicon oxide, silicon nitride, aluminum oxide and other stacked structures.

[0052] Please see Figure 3 The first gate layer 125 and the second gate layer 127 are respectively disposed on the corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 127 can be metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals. For example, the materials can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0053] Please see Figure 3The materials of the first source-drain layer 129 and the second source-drain layer 131 can be metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals. For example, the materials can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0054] Please see Figure 3 The first planarization layer 130 and the second planarization layer 132 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 130 and the second planarization layer 132 can be inorganic materials composed of silicon oxynitride, or organic materials with flatness, such as flexible materials such as polytetrafluoroethylene.

[0055] Please see Figure 3 The light-emitting device layer may include multiple light-emitting devices EL, each of which has an anode AN, a light-emitting unit, and a cathode CA connected to the pixel circuit.

[0056] Please see Figure 4 and Figure 5 The gate driving circuit 300 is disposed in the non-display area NA, and the gate driving circuit 300 can be disposed on both sides of the display area AA; the gate driving circuit 300 can include a plurality of gate driving units 300a, the plurality of gate driving units 300a can be arranged along the first direction X, a portion of the plurality of gate driving units 300a is disposed on the first side of the display area AA along the second direction Y, and another portion of the plurality of gate driving units 300a is disposed on the second side of the display area AA along the second direction Y.

[0057] For example, in Figure 4 and Figure 5 In the structure, the multiple gate driving units 300a may each include multiple first gate circuits 310 arranged and cascaded along the first direction X, multiple third gate circuits 330 arranged and cascaded along the first direction X, multiple second gate circuits 320 arranged and cascaded along the first direction X, multiple fourth gate circuits 340 arranged and cascaded along the first direction X, and multiple fifth gate circuits 350 arranged and cascaded along the first direction X. That is, the gate driving units 300a located on both sides of the display area AA can be symmetrically arranged.

[0058] Please see Figure 4 and Figure 5 The first gate circuit 310 is located on one side of the display area AA. The first gate circuit 310 is used to transmit the compensation control signal Scan1 to the sub-pixel PL of a row. That is, the driving mode of the first gate circuit 310 is single-row dual-drive.

[0059] Please see Figure 4 and Figure 5 The second gate circuit 320 is located between the display area AA and the first gate circuit 310. The second gate circuit 320 is used to transmit the first reset control signal Scan2 to a row of sub-pixels PL. That is, the driving mode of the second gate circuit 320 is single-row dual-drive.

[0060] Please see Figure 4 and Figure 5 The fifth gate circuit 350 is located on the side of the first gate circuit 310 away from the display area AA. The fifth gate circuit 350 is used to transmit the switch control signal Scan3 to the sub-pixel PL of a row. That is, the driving mode of the fifth gate circuit 350 is single-row dual-drive.

[0061] Please see Figure 4 and Figure 5 The third gate circuit 330 is located on the side of the fifth gate circuit 350 away from the display area AA. The third gate circuit 330 is used to transmit the light emission control signal EM to the two rows of sub-pixels PL. That is, the driving mode of the third gate circuit 330 is dual-row dual-drive.

[0062] Please see Figure 4 and Figure 5 The fourth gate circuit 340 is located between the fifth gate circuit 350 and the third gate circuit 330. The fourth gate circuit 340 is used to transmit the second reset control signal Scan4 to the two rows of sub-pixels PL. That is, the driving mode of the fourth gate circuit 340 is dual-row dual-drive.

[0063] This is equivalent to the first gate circuit 310 being connected to the compensation transistor T3A, the second gate circuit 320 being connected to the first reset transistor T4A, the third gate circuit 330 being connected to the first light-emitting control transistor T5A and the second light-emitting control transistor T6A, the fourth gate circuit 340 being connected to the second reset transistor T7A and the third reset transistor T8A, and the fifth gate circuit 350 being connected to the switching transistor T2A.

[0064] It should be noted that since the first reset signal Vi1, the second reset signal Vi2 and the third reset signal Vi3 are all constant voltages, they do not require the corresponding gate drive circuit 300 to control them, and can be directly connected to the corresponding constant voltage source.

[0065] In this embodiment, the first gate circuit 310, the second gate circuit 320, the third gate circuit 330, the fourth gate circuit 340, and the fifth gate circuit 350 of this application can be gate circuits of mTnC, where m and n are both positive integers, and this application does not impose specific limitations.

[0066] Please see Figure 5 and Figure 6The power signal line 200 includes a first power line 210, a second power line 220 and a third power line 230 connected to each other. The first power line 210 is located on the side of the gate driving circuit 300 away from the display area AA. The second power line 220 is located between two adjacent gate driving units 300a. The third power line 230 is located within the display area AA.

[0067] In the prior art, only the first power line 210 is usually provided, that is, the power signal line 200 for transmitting the low-level source VSS is provided on both sides of the display panel 100. However, due to the influence of the resistance and capacitance in the wire, there is a difference between the low-level source VSS signal output from the signal source and the low-level source VSS signal received by the pixel driving circuit PC, resulting in abnormal display of the display panel 100. In this application, by providing a larger number of third power lines 230 in the display area AA, and by electrically connecting the first power line 210 and the third power line 230 through the second power line 220, the transmission path of the power signal is increased, the error of the power signal received by the pixel driving circuit PC is reduced, and the display effect of the display panel 100 is improved.

[0068] Please see Figure 6 The third power line 230 includes multiple first sub-lines 231 and multiple second sub-lines 232 that are electrically connected. The first sub-lines 231 extend along the first direction X, and the second sub-lines 232 extend along the second direction Y. The multiple first sub-lines 231 and the multiple second sub-lines 232 form a mesh structure.

[0069] In this embodiment, multiple first sub-lines 231 and multiple second sub-lines 232 are arranged in a cross configuration, which is equivalent to multiple first sub-lines 231 and multiple second sub-lines 232 being connected in parallel, thereby reducing the impedance of the third power line 230. At the same time, within the display area AA, the cathode used to receive the power signal from the low-level source VSS can pass through a via and be electrically connected to the third power line 230 to reduce the error of the power signal from the low-level source VSS.

[0070] In this embodiment, since the pixel driving circuit PC is composed of multiple transistors, and the multiple transistors require the material preparation of the active layer 123, the first gate layer 125, the second gate layer 127, the first source-drain layer 129, and the second source-drain layer 131, in order to avoid the third power line 230 from being short-circuited with the lines in the pixel driving circuit PC, the light-shielding layer 121 of this application may include the third power line 230, that is, the third power line 230 of this application may be prepared by the light-shielding layer 121.

[0071] In this embodiment, since the transistors in the pixel driving circuit PC are all silicon semiconductor transistors, and the device performance of silicon semiconductor transistors is greatly affected by light, the multiple first sub-lines 231 and multiple second sub-lines 232 of this application can be used to block at least some of the transistors in the pixel driving circuit PC. For example, the active part of the compensation transistor can overlap with the first sub-line 231 or the second sub-line 232, and the active part of the first reset transistor can overlap with the first sub-line 231 or the second sub-line 232.

[0072] Please see Figure 5 and Figure 6 The light-shielding layer 121 further includes a light-shielding bus 240 extending along the first direction X. The light-shielding bus 240 is disposed between the second power line 220 and the third power line, and the end of the second power line 220 near the third power line 230 is electrically connected to the light-shielding bus 240, and the end of the third power line 230 near the second power line 220 is electrically connected to the light-shielding bus 240.

[0073] In this embodiment, the light-shielding bus 240 extends along the first direction X, and multiple second sub-lines 232 located within the display area AA are electrically connected to the light-shielding bus 240. Simultaneously, multiple second power lines 220 are also electrically connected to the light-shielding bus 240. Since the second sub-lines 232 and the second power lines 220 are not on the same straight line, the light-shielding bus 240 can be positioned between the second power lines 220 and the third power lines 230. This allows multiple second power lines 220 to transmit power signals to the third power lines 230 via the light-shielding bus 240. Furthermore, the light-shielding bus 240 can also function as a first sub-line 231, allowing multiple second sub-lines 232 to be connected in parallel, thereby reducing the impedance of the third power line 230.

[0074] In this embodiment, the width of the light-shielding bus 240 is greater than the width of the third power line 230 and the second power line 220. Since the area where the light-shielding bus 240 is located is the non-display area NA, in order to reduce the impedance of the light-shielding bus 240, this application can increase the width of the light-shielding bus 240. The third power line 230 only needs to block the active part of the transistor, and the space between two adjacent gate driving units 300a is limited. Therefore, this application can make the width of the light-shielding bus 240 greater than the width of the third power line 230 and the second power line 220.

[0075] In this embodiment, the width of the third power line 230 can be in the range of 1.0 micrometer to 1.2 micrometer.

[0076] In this embodiment, the width of the light-shielding bus 240 is 15 micrometers to 20 micrometers.

[0077] It should be noted that, since the space between two adjacent gate driving units 300a is limited, but the space in this area is still larger than the wiring space in the display area AA, this application can make the width of the second power line 220 greater than or equal to the width of the third power line 230, that is, increase the line width of the second power line 220 as much as possible to reduce the impedance of the second power line 220.

[0078] In this embodiment, the width of the first power line 210 is greater than the width of the light-shielding bus 240. Since the first power line 210 is directly connected to the signal source of the output low-level source VSS, the width of the first power line 210 can be increased to reduce the voltage drop of the low-level source VSS in the first power line 210. At the same time, since the first power line 210 is located on the side of the gate driving circuit 300 away from the display area AA, the first power line 210 of this application can be wide enough while meeting the design requirements of the bezel width.

[0079] Please see Figure 6 The second power line 220 includes multiple third sub-lines 221 electrically connected to each other, and the multiple third sub-lines 221 extend along the second direction Y. At least one of the light-shielding layer 121, the first gate layer 125, the second gate layer 127 and the first source-drain layer 129 includes the third sub-lines 221.

[0080] For example, in Figure 6 In the structure, one second power line 220 may include four laterally extending third sub-lines 221. The four third sub-lines 221 may all be formed in the process of the light-shielding layer 121, or the four third sub-lines 221 may all be formed in the process of the first gate layer 125, or the four third sub-lines 221 may all be formed in the process of the second gate layer 127, or the four third sub-lines 221 may all be formed in the process of the first source-drain layer 129, or the four third sub-lines 221 may be formed in the process of two, three, or four of the light-shielding layer 121, the first gate layer 125, the second gate layer 127, and the first source-drain layer 129.

[0081] In this embodiment, due to the technical problem that electrostatic accumulation is prone to occur when adjacent low-level source VSS signals are transmitted in the same layer of conductors, this application can make the two adjacent third sub-lines 221 set in different layers; for example, in the direction from the first power line 210 to the light-shielding bus 240, the first third sub-line 221 and the third sub-line 221 can be formed in the process of the second gate layer 127, and the second third sub-line 221 and the fourth sub-line 221 can be formed in the process of the first source-drain layer 129.

[0082] It should be noted that this application also proposes a display device, which includes the aforementioned display panel, and the display device of this application can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0083] This application provides a display panel and a display device. The display panel includes a gate driving circuit, a pixel driving circuit, and power signal lines. The power signal lines include a first power line, a second power line, and a third power line. The first and second power lines are located in a non-display area, and the third power line is located in the display area. One end of the second power line is connected to the first power line, and the other end of the second power line is electrically connected to the third power line. The other end of the third power line is electrically connected to the pixel driving circuit, and the second power line is located between two adjacent gate driving units. By setting a second power line between two adjacent gate driving units, this application transmits the power signal transmitted by the first power line to the third power line electrically connected to the pixel driving circuit, increasing the transmission path of the power signal, reducing the error of the power signal received by the pixel driving circuit, and improving the display effect of the display panel.

[0084] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0086] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0087] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area located on one side of the display area. A gate driving circuit is located in the non-display area, and the gate driving circuit includes a plurality of gate driving units arranged along a first direction. The pixel driving circuit is located within the display area; The power signal line includes a first power line, a second power line, and a third power line, wherein the first power line and the second power line are located in the non-display area, and the third power line is located in the display area; Wherein, one end of the second power line is connected to the first power line, the other end of the second power line is electrically connected to the third power line, the other end of the third power line is electrically connected to the pixel driving circuit, and the second power line is located between two adjacent gate driving units.

2. The display panel according to claim 1, characterized in that, The display panel includes a substrate, a light-shielding layer disposed on the substrate, and an array driving layer disposed on the side of the light-shielding layer away from the substrate. The array driving layer includes the gate driving circuit and the pixel driving circuit. The light-shielding layer includes the third power line.

3. The display panel according to claim 2, characterized in that, The third power line includes multiple first sub-lines and multiple second sub-lines that are electrically connected. The first sub-lines extend along the first direction, and the second sub-lines extend along the second direction. The multiple first sub-lines and the multiple second sub-lines form a mesh structure.

4. The display panel according to claim 2, characterized in that, The light-shielding layer further includes a light-shielding bus extending along the first direction. The light-shielding bus is disposed between the second power line and the third power line, and the end of the second power line near the third power line is electrically connected to the light-shielding bus, and the end of the third power line near the second power line is electrically connected to the light-shielding bus.

5. The display panel according to claim 4, characterized in that, The width of each of the light-shielding bus lines is greater than the width of the third power line and the second power line.

6. The display panel according to claim 5, characterized in that, The width of the third power line ranges from 1.0 micrometer to 1.2 micrometers, and the width of the light-shielding bus ranges from 15 micrometers to 20 micrometers.

7. The display panel according to claim 4, characterized in that, The width of the first power line is greater than the width of the light-shielding bus.

8. The display panel according to any one of claims 2 to 7, characterized in that, The array driving layer includes a first gate layer, a second gate layer disposed on the side of the first gate layer away from the substrate, a first source-drain layer disposed on the side of the second gate layer away from the substrate, and a second source-drain layer disposed on the side of the first source-drain layer away from the substrate. The second power line includes multiple third sub-lines that are electrically connected, and all of the multiple third sub-lines extend along a second direction. At least one of the light-shielding layer, the first gate layer, the second gate layer, and the first source-drain layer includes the third sub-lines.

9. The display panel according to claim 8, characterized in that, The two adjacent third sub-lines are arranged in different layers.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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