Charge pump circuits, chips and electronic devices

Abstract

This disclosure provides a charge pump circuit, chip, and electronic device. The charge pump circuit includes: a first charge pump branch, a second charge pump branch, a first energy release circuit, a second energy release circuit, and a charge transfer control branch; the first energy release circuit is configured to form a first charge transfer path with the charge transfer control branch during a first sub-period of the dead time; the second energy release circuit is configured to form a second charge transfer path with the charge transfer control branch during a second sub-period of the dead time; the charge transfer control branch is configured to cross-switch between the first charge transfer path and the second charge transfer path during the dead time to transfer the charge stored in the parasitic capacitance of a first target switch to the parasitic capacitance of the second target switch. This reduces the switching losses of the charge pump circuit, which is beneficial for reducing the temperature and improving the charging efficiency of the charge pump circuit.

Description

Technical Field

[0001] This disclosure relates to the field of charging technology, and more particularly to a charge pump circuit, chip, and electronic device. Background Technology

[0002] In related technologies, electronic devices incorporate charge pump circuits to charge batteries. These charge pump circuits can be implemented using cross-type or symmetrical topologies. During the alternating charging process of the charge pump circuit, a dead-time phase exists, which allows for zero-voltage switching (ZVS) of the MOSFETs within the charge pump circuit, reducing switching losses.

[0003] However, in some scenarios, some switching devices in the charge pump circuit cannot complete the discharge during the dead zone, resulting in significant switching losses, which leads to overheating of electronic devices and reduces the user experience. Utility Model Content

[0004] This disclosure provides a charge pump circuit, chip, and electronic device to solve the above-mentioned technical problems.

[0005] According to a first aspect of this disclosure, a charge pump circuit is provided, comprising: a first charge pump branch, a second charge pump branch, a first energy release circuit, a second energy release circuit, and a charge transfer control branch; the first charge pump branch is provided with a first charge transfer connection point and a first branch connection point; the second charge pump branch is provided with a second charge transfer connection point and a second branch connection point; the first energy release circuit is connected in series between the first charge transfer connection point and the first branch connection point; the second energy release circuit is connected in series between the second charge transfer connection point and the second branch connection point; the charge transfer control branch is connected in series between the first charge transfer connection point and the second charge transfer connection point; the second charge pump branch is electrically connected to the first charge pump branch through the first branch connection point; the first charge pump branch is electrically connected to the second charge pump branch through the second branch connection point; The first charge pump branch and the second charge pump branch are configured to alternately output electrical energy in two adjacent control cycles; The first energy release circuit is configured to form a first charge transfer path with the charge transfer control branch during a first sub-period of the dead zone; The second energy release circuit is configured to form a second charge transfer path with the charge transfer control branch during the second sub-period of the dead zone; The charge transfer control branch is configured to alternately switch between the first charge transfer path and the second charge transfer path during the dead zone period to transfer the charge stored in the parasitic capacitance of the first target switch to the parasitic capacitance of the second target switch. The dead zone period refers to the period between two adjacent control cycles, during which the switching devices in both the first charge pump branch and the second charge pump branch are in the off state; the first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.

[0006] In one embodiment, the first charge pump branch includes a first sub-branch, a second sub-branch, and a first flyby capacitor; the second charge pump branch includes a third sub-branch, a fourth sub-branch, and a second flyby capacitor that are electrically connected; the second sub-branch and the third sub-branch are electrically connected to the second branch connection point; the first sub-branch and the fourth sub-branch are electrically connected to the first branch connection point; the first flyby capacitor is electrically connected to the second sub-branch and the first sub-branch respectively; the second flyby capacitor is electrically connected to the fourth sub-branch and the third sub-branch respectively.

[0007] In one embodiment, the first sub-branch includes a first switching device and a second switching device; the first terminal of the first switching device is electrically connected to the first branch connection point, and the second terminal of the first switching device is electrically connected to the first terminal of the second switching device, the second terminal of the first flying capacitor, and the first charge transfer connection point, respectively; the second terminal of the second switching device is grounded; and the first energy release circuit is connected in parallel with the first switching device.

[0008] In one embodiment, the first energy release circuit includes a first energy release capacitor, a first end of which is electrically connected to the first branch connection point, and a second end of which is electrically connected to the first charge transfer connection point.

[0009] In one embodiment, the first sub-branch further includes a first capacitor, a third switching device, a fourth switching device, a fifth switching device, and a sixth switching device; The first end of the third switching device is electrically connected to the first branch connection point, and the second end of the third switching device is electrically connected to the first end of the fourth switching device; the first end of the fifth switching device is electrically connected to the second end of the fourth switching device, and the second end of the fifth switching device is grounded; the first end of the sixth switching device is electrically connected to the first end of the fifth switching device, and the second end of the sixth switching device is electrically connected to the output end. The first terminal of the first capacitor is electrically connected to the first branch connection point, and the second terminal of the first capacitor is electrically connected to the first terminal of the fifth switching device.

[0010] In one embodiment, the second sub-branch includes a seventh switching device, an eighth switching device, and a ninth switching device; the first terminal of the seventh switching device is electrically connected to a power supply, the second terminal of the seventh switching device is electrically connected to the first terminal of the eighth switching device and the first terminal of the first flying capacitor, the second terminal of the eighth switching device is electrically connected to the first terminal of the ninth switching device, and the second terminal of the ninth switching device is electrically connected to the connection point of the second branch.

[0011] In one embodiment, the third sub-branch includes a tenth switching device and an eleventh switching device; the first terminal of the tenth switching device is electrically connected to the second branch connection point, and the second terminal of the tenth switching device is electrically connected to the first terminal of the eleventh switching device, the second terminal of the second flying capacitor, and the second charge transfer connection point, respectively; the second terminal of the eleventh switching device is grounded; and the second energy release circuit is connected in parallel with the tenth switching device.

[0012] In one embodiment, the second energy release circuit includes a second energy release capacitor, a first terminal of which is electrically connected to the second branch connection point, and a second terminal of which is electrically connected to the second charge transfer connection point.

[0013] In one embodiment, the third sub-branch further includes a second capacitor, a twelfth switching device, a thirteenth switching device, a fourteenth switching device, and a fifteenth switching device; The first terminal of the twelfth switching device is electrically connected to the second branch connection point, and the second terminal of the twelfth switching device is electrically connected to the first terminal of the thirteenth switching device; the first terminal of the fourteenth switching device is electrically connected to the second terminal of the thirteenth switching device, and the second terminal of the fourteenth switching device is grounded; the first terminal of the fifteenth switching device is electrically connected to the first terminal of the fourteenth switching device, and the second terminal of the fifteenth switching device is electrically connected to the output terminal; the first terminal of the second capacitor is electrically connected to the second branch connection point, and the second terminal of the second capacitor is electrically connected to the first terminal of the fourteenth switching device.

[0014] In one embodiment, the fourth sub-branch includes a sixteenth switching device, a seventeenth switching device, and an eighteenth switching device; the first terminal of the sixteenth switching device is electrically connected to a power supply, the second terminal of the sixteenth switching device is electrically connected to the first terminal of the seventeenth switching device and the first terminal of the second flying capacitor, the second terminal of the seventeenth switching device is electrically connected to the first terminal of the eighteenth switching device, and the second terminal of the eighteenth switching device is electrically connected to the first branch connection point.

[0015] In one embodiment, the charge transfer control branch includes a first charge transfer switching device, a second charge transfer switching device, a third charge transfer switching device, a fourth charge transfer switching device, and a charge transfer inductor; The first terminal of the first charge transfer switching device is electrically connected to the first charge transfer connection point, and the second terminal of the first charge transfer switching device is electrically connected to the first terminal of the charge transfer inductor and the first terminal of the fourth charge transfer switching device, respectively. The first terminal of the third charge transfer switch is electrically connected to the second terminal of the charge transfer inductor and the first terminal of the second charge transfer switch, respectively; the second terminal of the third charge transfer switch is electrically connected to the second charge transfer connection point. The second terminal of the second charge transfer switch is connected to the ground plane, and the second terminal of the fourth charge transfer switch is also connected to the ground plane.

[0016] According to a second aspect of this disclosure, a chip is provided, including the charge pump circuit as described above.

[0017] According to a third aspect of this disclosure, an electronic device is provided, comprising: a processor, a battery, a charging interface, and a charge pump circuit as described in any of the first aspects; the charge pump circuit is electrically connected to the battery and the charging interface respectively; the processor is electrically connected to the charge pump circuit; The processor is configured to control the first target switch of the first charge pump branch and the second charge pump branch to switch to the on state and the second target switch to the off state within a control cycle. The processor is configured to control all switching devices of the first charge pump branch and the second charge pump branch to switch to the off state during the dead period; The processor is also configured to output a valid control signal to the charge transfer control branch of the charge pump circuit during the dead time period; The charge transfer control branch is configured to transfer a portion of the charge stored in the parasitic capacitance of the second target switch in the previous control cycle to the parasitic capacitance of the first target switch when a valid control signal is received during the dead zone.

[0018] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor, a battery, a charging interface, and a chip as described in the second aspect; the chip is electrically connected to the battery, the charging interface, and the processor, respectively. The processor is configured to send valid control signals to the first charge pump branch and the second charge pump branch of the charge pump circuit in the chip in each control cycle to switch the second target switch and the first target switch. The processor is also configured to output a valid control signal to the charge transfer control branch of the charge pump circuit during a dead zone period after each control cycle to achieve charge transfer between the second target switch and the first target switch.

[0019] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: The charge pump circuit provided in this embodiment forms a first charge transfer path by setting a first energy release circuit and a charge transfer control branch, and forms a second charge transfer path by setting a second energy release circuit and a charge transfer control branch. It can transfer the charge stored in the parasitic capacitance of the switching device between the first charge transfer connection point and the first branch connection point to the parasitic capacitance of the switching device between the second charge transfer connection point and the second branch connection point, or transfer the charge stored in the parasitic capacitance of the switching device between the second charge transfer connection point and the second branch connection point to the parasitic capacitance of the switching device between the first charge transfer connection point and the first branch connection point. This achieves the effect of zero-voltage switching for some switching devices in the first charge pump branch and the second charge pump branch, reduces the switching loss of the charge pump circuit, and helps to reduce the temperature of the charge pump circuit and improve the charging efficiency of the charge pump circuit.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0022] Figure 2 This is a circuit diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0023] Figure 3 This is a circuit diagram of a charge pump circuit according to an embodiment of the present disclosure.

[0024] Figure 4 This is a schematic diagram of an AC equivalent model of charge transfer during the dead zone after adding a first energy release circuit and a second energy release circuit according to an embodiment of this disclosure.

[0025] Figure 5This is a schematic diagram of an AC equivalent model of charge transfer during the dead zone without adding a first energy release circuit and a second energy release circuit, according to an embodiment of this disclosure.

[0026] Figure 6 This is a schematic diagram comparing the efficiency curves before and after adding a first energy release circuit and a second energy release circuit, according to an embodiment of this disclosure.

[0027] Figure 7 This is a block diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0029] This disclosure provides a charge pump circuit, a chip, and an electronic device. Figure 1 This is a schematic diagram of the structure of an electronic device according to an embodiment of this disclosure. See also... Figure 1 An electronic device 10 includes a processor 11, a charging interface 12, a charge pump circuit 13, and a battery 14. The charge pump circuit 13 is electrically connected to both the battery 14 and the charging interface 12; the processor 11 is electrically connected to the charge pump circuit 13.

[0030] In one example, the charging interface 12 may include, but is not limited to, a USB Type-C interface, a MicroUSB interface, etc. If it can support charging by the charge pump circuit 13, the corresponding charging interface falls within the protection scope of this disclosure.

[0031] In one example, battery 14 may include, but is not limited to, a lithium-ion battery (Li-Ion) or a lithium polymer battery (Li-Polymer), and the corresponding battery falls within the protection scope of this disclosure if it is capable of providing electrical power to various loads within the electronic device.

[0032] See one example. Figure 2 The charge pump circuit 13 includes a first charge pump branch 21, a second charge pump branch 22, and a charge transfer control branch 23.

[0033] In this example, the first charge pump branch 21 and the second charge pump branch 22 constitute a symmetrical charge pump architecture. The symmetrical charge pump architecture includes at least one of the following: a Dixon architecture, a series-parallel charging architecture, and a cross-charging architecture. For ease of description, in this example, the symmetrical structure is implemented using a cross-charging architecture to facilitate the description of subsequent embodiments, but this does not constitute a limitation.

[0034] In one example, the first charge pump branch 21 is provided with a first charge transfer connection point C1N and a first branch connection point C2P. The second charge pump branch 22 is provided with a second charge transfer connection point C1N' and a second branch connection point C2P'. These connection points are physical connection points, physical connection lines, or physical pads at the same potential that allow electrical connections between modules. The attached diagram only shows a virtual point to represent the electrical connection relationship between modules.

[0035] In one example, the charge pump circuit further includes a first energy release circuit 24 and a second energy release circuit 25. The first energy release circuit 24 is disposed between the first charge transfer connection point C1N and the first branch connection point C2P, and the second energy release circuit 25 is disposed between the second charge transfer connection point C1N' and the first branch connection point C2P'. The first energy release circuit 24 and the second energy release circuit 25 are respectively used in conjunction with the aforementioned charge transfer control branch 23. For example, the first energy release circuit 24 is configured to form a first charge transfer path with the charge transfer control branch 23 during a first sub-period of the dead zone, and the second energy release circuit 25 is configured to form a second charge transfer path with the charge transfer control branch 23 during a second sub-period of the dead zone. The coordination process is described in subsequent embodiments.

[0036] In one example, the first charge pump branch 21 includes a first sub-branch 211, a second sub-branch 212, and a first flyby capacitor Cf1, all electrically connected. The second charge pump branch 22 includes a third sub-branch 221, a fourth sub-branch 222, and a second flyby capacitor Cf1, all electrically connected. The second sub-branch 212 and the third sub-branch 221 are electrically connected to the second branch connection point C2P'; the first sub-branch 211 and the fourth sub-branch 222 are electrically connected to the first branch connection point C2P; the first flyby capacitor Cf1 is electrically connected to both the second sub-branch 212 and the first sub-branch 211; and the second flyby capacitor Cf2 is electrically connected to both the fourth sub-branch 222 and the third sub-branch 221. Thus, the first charge pump branch 21 and the second charge pump branch 22 constitute a cross-charging architecture; the first charge pump branch 21 and the second charge pump branch 22 form a cross-charging architecture with respect to the first line where the power supply BAT is located.

[0037] In one example, see [link to example]. Figure 2The first sub-branch 211 includes a first switching device Q1 and a second switching device Q2; the first terminal of the first switching device Q1 is electrically connected to the first branch connection point C2P, and the second terminal of the first switching device Q1 is electrically connected to the first terminal of the second switching device Q2, the second terminal of the first flying capacitor Cf1, and the first charge transfer connection point C1N; the second terminal of the second switching device Q2 is grounded to ground plane GND; the first energy release circuit 24 is connected in parallel with the first switching device Q1.

[0038] In one example, the first energy release circuit 24 includes a first energy release capacitor C1. A first terminal of the first energy release capacitor C1 is electrically connected to a first branch connection point C2P, and a second terminal of the first energy release capacitor C1 is electrically connected to a first charge transfer connection point C1N. Thus, the first energy release capacitor C1 can form a charge transfer channel between the first branch connection point C2P and the first charge transfer connection point C1N during the dead time.

[0039] In one example, see [link to example]. Figure 2 The first sub-branch 211 also includes a first capacitor C2, a third switching device Q3, a fourth switching device Q4, a fifth switching device Q5, and a sixth switching device Q6. The first terminal of the third switching device Q3 is electrically connected to the first branch connection point C2P, and the second terminal of the third switching device Q3 is electrically connected to the first terminal of the fourth switching device Q4; the first terminal of the fifth switching device Q5 is electrically connected to the second terminal of the fourth switching device Q4, and the second terminal of the fifth switching device Q5 is grounded to ground GND; the first terminal of the sixth switching device Q6 is electrically connected to the first terminal of the fifth switching device Q5, and the second terminal of the sixth switching device Q6 is electrically connected to the output terminal VO2; the first terminal of the first capacitor C2 is electrically connected to the first branch connection point C2P, and the second terminal of the first capacitor C2 is electrically connected to the first terminal of the fifth switching device Q5.

[0040] Understandably, the second terminal of the third switching device Q3 can be electrically connected to the output capacitor Cout2 to form the first output terminal VOUT; while the second terminal of the sixth switching device Q6 can be electrically connected to the output capacitor Cout3 to form the second output terminal VO2, and the output voltage of the second output terminal VO2 is equal to the output voltage of the first output terminal VOUT. For example, when the power supply VIN voltage is 20V, the output voltages of both the second output terminal VO2 and the first output terminal VOUT are 5V. In one example, see [link to example]. Figure 2The second sub-branch 212 includes a seventh switching device Q7, an eighth switching device Q8, and a ninth switching device Q9. The first terminal of the seventh switching device Q7 is electrically connected to the power supply VIN. The second terminal of the seventh switching device Q7 is electrically connected to the first terminal of the eighth switching device Q8 and the first terminal of the first flying capacitor Cf1. The second terminal of the eighth switching device Q8 is electrically connected to the first terminal of the ninth switching device Q9. The second terminal of the ninth switching device Q9 is electrically connected to the second branch connection point C2P'. In this example, the second terminal of the eighth switching device Q8 can form a third output terminal VO1 with the output capacitor Cout1. The third output terminal VO1 has twice the output voltage of the first output terminal VOUT. For example, if the power supply VIN voltage is 20V, the third output terminal VO1 outputs 10V, and the first output terminal VOUT outputs 5V.

[0041] In one example, see [link to example]. Figure 2 The third sub-branch 221 includes a tenth switching device Q10 and an eleventh switching device Q11; the first terminal of the tenth switching device Q10 is electrically connected to the second branch connection point C2P', and the second terminal of the tenth switching device Q10 is electrically connected to the first terminal of the eleventh switching device Q11, the second terminal of the second flying capacitor Cf2, and the second charge transfer connection point C1N', respectively; the second terminal of the eleventh switching device Q11 is grounded to ground GND; the second energy release circuit 25 is connected in parallel with the tenth switching device Q10. The second energy release circuit 25 can form a charge transfer channel between the first branch connection point C2P and the first charge transfer connection point C1N during the dead time.

[0042] In one example, see [link to example]. Figure 2 The second energy release circuit 25 includes a second energy release capacitor C3. The first terminal of the second energy release capacitor C3 is electrically connected to the second branch connection point C2P', and the second terminal of the second energy release capacitor C3 is electrically connected to the second charge transfer connection point C1N'. Thus, the second energy release capacitor C3 can create a charge transfer channel between the second branch connection point C2P' and the second charge transfer connection point C1N' during the dead time period.

[0043] In one example, see [link to example]. Figure 2The third sub-branch 221 also includes a second capacitor C4, a twelfth switching device Q12, a thirteenth switching device Q13, a fourteenth switching device Q14, and a fifteenth switching device Q15; the first terminal of the twelfth switching device Q12 is electrically connected to the second branch connection point C2P', and the second terminal of the twelfth switching device Q12 is electrically connected to the first terminal of the thirteenth switching device Q13; the first terminal of the fourteenth switching device Q14 is electrically connected to the second terminal of the thirteenth switching device Q13, and the second terminal of the fourteenth switching device Q14 is grounded to ground GND; the first terminal of the fifteenth switching device Q15 is electrically connected to the first terminal of the fourteenth switching device Q14, and the second terminal of the fifteenth switching device Q15 is electrically connected to the second output terminal VO2; the first terminal of the second capacitor C4 is electrically connected to the second branch connection point C2P', and the second terminal of the second capacitor C4 is electrically connected to the first terminal of the fourteenth switching device Q14.

[0044] Understandably, the second terminal of the twelfth switching device Q12 can be electrically connected to the output capacitor Cout2 to form the first output terminal VOUT; while the second terminal of the fifteenth switching device Q15 can be electrically connected to the output capacitor Cout3 to form the second output terminal VO2, and the second output terminal VO2 is equal to the output voltage of the first output terminal VOUT.

[0045] In one example, see [link to example]. Figure 2 The fourth sub-branch 222 includes a sixteenth switching device Q16, a seventeenth switching device Q17, and an eighteenth switching device Q18; the first terminal of the sixteenth switching device Q16 is electrically connected to the power supply, the second terminal of the sixteenth switching device Q16 is electrically connected to the first terminal of the seventeenth switching device Q17 and the first terminal of the second flying capacitor Cf2, the second terminal of the seventeenth switching device Q17 is electrically connected to the first terminal of the eighteenth switching device Q18; the second terminal of the eighteenth switching device Q18 is electrically connected to the first branch connection point C2P.

[0046] In one example, see [link to example]. Figure 2The charge transfer control branch 23 includes a first charge transfer switch Q19, a second charge transfer switch Q20, a third charge transfer switch Q21, a fourth charge transfer switch Q22, and a charge transfer inductor L1. The first terminal of the first charge transfer switch Q19 is electrically connected to the first charge transfer connection point C1N, and the second terminal of the first charge transfer switch Q19 is electrically connected to the first terminal of the charge transfer inductor L1 and the first terminal of the fourth charge transfer switch Q22, respectively. The first terminal of the third charge transfer switch Q21 is electrically connected to the second terminal of the charge transfer inductor L1 and the first terminal of the second charge transfer switch Q20, respectively, and the second terminal of the third charge transfer switch Q21 is electrically connected to the second charge transfer connection point C1N'. The second terminal of the second charge transfer switch Q20 is grounded to ground GND, and the second terminal of the fourth charge transfer switch Q22 is grounded to ground GND.

[0047] In one example, Figure 2 The working principle of the example charge pump circuit includes: In the first control cycle, see Figure 3 In the first charge pump branch 21, the first switching device Q1, the fourth switching device Q4, the fifth switching device Q5, and the seventh switching device Q7 are switched to the on state, while the other switching devices are switched to the off state. In the second charge pump branch 22, the eleventh switching device Q11, the twelfth switching device Q12, and the fourteenth switching device Q14 are switched to the on state, while the other switching devices are switched to the off state. All switching devices in the charge transfer control branch 23 are switched to the off state. Or, in other words, Figure 3 The switches marked in red are switched to the ON state, while the switches marked in blue and black are switched to the OFF state.

[0048] In the first control cycle, the charge pump circuit includes four current paths; The first current path: The current starts from the power supply VIN, passes through the seventh switching device Q7, the first flying capacitor Cf1, the first charge transfer connection point C1N, the first switching device Q1, the first branch connection point C2P, the first capacitor C2, and the fourth switching device Q4 in sequence, and finally passes through the first output terminal VOUT to output to the load.

[0049] The second current path: The current starts from the power supply VIN, passes through the seventh switching device Q7, the first flying capacitor Cf1, the first charge transfer connection point C1N, the first switching device Q1, the first branch connection point C2P and the eighteenth switching device Q18 in sequence, and finally passes through the third output terminal VO1 to output to the load.

[0050] The third current path: The current starts from the power supply VIN, passes sequentially through the seventh switching device Q7, the first flying capacitor Cf1, the first charge transfer connection point C1N, the first switching device Q1, the first branch connection point C2P, the eighteenth switching device Q18, the second flying capacitor Cf2, and the eleventh switching device Q11, and finally flows into the ground GND, which is the negative terminal of the power supply.

[0051] The fourth current path: the fourteenth switching device Q14, the second capacitor C4, the twelfth switching device Q12, and finally output to the load through the first output terminal VOUT.

[0052] In the second control cycle, see [link / reference]. Figure 3 , Figure 3 The switches marked in red and black are switched to the off state, while the switches marked in blue are switched to the on state. In the second control cycle, the charge pump circuit includes four current paths; The first current path: The current starts from the positive terminal of the power supply VIN, passes sequentially through the sixteenth switching device Q16, the second flying capacitor Cf2, the second charge transfer connection point C1N', the tenth switching device Q10, the second branch connection point C2P', the second capacitor C4, and the thirteenth switching device Q13, and finally passes through the first output terminal VOUT to output to the load.

[0053] The second current path: The current starts from the positive terminal of the power supply VIN, passes sequentially through the sixteenth switching device Q16, the second flying capacitor Cf2, the second charge transfer connection point C1N', the tenth switching device Q10, the second branch connection point C2P', the second capacitor C4, and the fifteenth switching device Q15, and finally is output to the load through the second output terminal VO2.

[0054] The third current path: The current starts from the positive terminal of the power supply VIN, passes sequentially through the sixteenth switching device Q16, the second flying capacitor Cf2, the second charge transfer connection point C1N', the tenth switching device Q10, the second branch connection point C2P', and the ninth switching device Q9, and finally is output to the load through the third output terminal VO3.

[0055] The fourth current path: the fifth switching device Q5, the first capacitor C2, the third switching device Q3, and finally the output to the load through the first output terminal VOUT.

[0056] Understandably, the charge pump circuit switches between the two control cycles mentioned above to achieve the effect of outputting electrical energy from the first charge pump branch 21 or the second charge pump branch 22.

[0057] The period between the first and second control cycles is a dead zone during which all switching devices in the first charge pump branch 21 and the second charge pump branch 22 are in the off state. However, some switches in the first target switch within the first charge pump branch 21 and the second charge pump branch 22 may have parasitic charges, meaning that the parasitic capacitances (such as source-drain parasitic capacitances Cds) of these switching devices will store charge. The first target switch refers to the switching device that was in the on state during the previous control cycle. Correspondingly, the switching device that was in the off state during the previous control cycle is called the second target switch to distinguish the two types of switching devices.

[0058] In one example, the dead time is divided into two sub-cycles: the first sub-cycle of the dead time and the second sub-cycle of the dead time. Understandably, the operating sequence of the charge pump circuit can be: first control cycle, first sub-cycle of the dead time, second sub-cycle of the dead time, second control cycle, first sub-cycle of the dead time, and second sub-cycle of the dead time, repeating the above sequence to achieve the power conversion function. It should be noted that the first control cycle, the first sub-cycle of the dead time, the second sub-cycle of the dead time, and the second control cycle are independent of each other, with no overlapping time regions, thus ensuring reliable operation of the charge pump circuit.

[0059] In one example, during the dead time, the first charge pump branch 21 and the second charge pump branch 22 are inactive, while the charge transfer control branch 23, the first energy release circuit 24, and the second energy release circuit 25 are active. For example, the charge transfer control branch 23 and the first energy release circuit 24 form a first charge transfer path during a first sub-period of the dead time, and the charge transfer control branch 23 and the second energy release circuit 25 form a second charge transfer path during a second sub-period of the dead time. When both the first energy release circuit 24 and the second energy release circuit 25 are implemented using capacitors, the charge transfer control branch 23 can alternately switch between the first charge transfer path and the second charge transfer path during the dead time to transfer the charge stored in the parasitic capacitance of the first target switch to the parasitic capacitance of the second target switch.

[0060] Given that the charge pump circuit in this disclosure is implemented with a symmetrical structure, the scheme for switching the charge transfer control branch 23 to either the first charge transfer path or the second charge transfer path is the same, differing only in the switching devices of the required transfer circuit. The following description will use the switching of the charge transfer control branch 23 to the first charge transfer path as an example.

[0061] In one example, with the red-marked switch as the first target switch and the blue-marked switch as the second target switch, and the power supply VIN voltage as 20V, the operating principle of the charge pump circuit during the dead time includes: Taking the first sub-period of the dead zone as an example, the nineteenth switch device Q19 and the twentieth switch device Q20 are in the on state, while the twenty-first switch device Q21 and the twenty-second switch device Q22 are in the off state. Under these circumstances, the first charge transfer path can be formed.

[0062] See Figure 4 The node voltage between the first charge transfer connection point C1N and the first branch connection point C2P is 10V. The voltage of the parasitic capacitance Cds-Q3 of the third switching device Q3 is 5V. The voltage of the parasitic capacitance Cds-Q4 of the fourth switching device Q4 is 0V. The voltage of the parasitic capacitance Cds-Q5 of the fifth switching device Q5 is 5V. The voltage of the parasitic capacitance Cds-Q1 of the first switching device Q1 is 0V. The voltage of the parasitic capacitance Cds-Q2 of the second switching device Q2 is 10V.

[0063] During the first sub-period, i.e., just entering the dead zone, the nineteenth switch Q19 and the twentieth switch Q20 are in the on state. The voltage at the first charge transfer junction C1N is pulled down to 0V, and the parasitic capacitance Cds-Q2 of the second switch Q2 discharges from 10V to 0V. At this time, the parasitic capacitances of the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are connected in parallel, and the parasitic capacitance Cds-Q1 of the first switch Q1 is connected in parallel with the first capacitor C2. The two sets of parallel capacitors are then connected in series, resulting in the following... Figure 4 The equivalent model of communication shown.

[0064] See Figure 4 In the AC equivalent model, the first capacitor C2 and the output capacitor Cout2 at the first output terminal are equivalent to a short circuit. The capacitance of the first energy release capacitor C1 is greater than the equivalent capacitance of the parasitic capacitances of the third switch Q3, the fourth switch Q4, and the fifth switch Q5 connected in parallel. Furthermore, the capacitance of the first energy release capacitor C1 is relatively large (e.g., C1 is greater than or equal to 100nF, and similarly, C is also greater than or equal to 100nF, and C1 = C3). Therefore, there is a path to ground in the parasitic capacitances. In this case, the parasitic capacitances Cds-Q3 of the third switch Q3 and Cds-Q5 of the fifth switch Q5 release energy, i.e., transfer charge, thus achieving zero-voltage switching (ZVS) for the switching devices. Additionally, the parasitic capacitance Cds-Q1 of the first switch Q1 is connected in parallel with the first energy release capacitor C1, and their terminal voltages are the same, thus compensating for the energy of the parasitic capacitance Cds-Q1 of the first switch Q1. Ultimately, the voltage of the parasitic capacitance Cds-Q3 of the third switching device Q3 and the parasitic capacitance Cds-Q5 of the fifth switching device Q5 is 0V, and the voltage of the parasitic capacitance Cds-Q1 of the first switching device Q1 is 5V.

[0065] In one example, assuming that the first energy release capacitor C1 and the second energy release capacitor C3 are not provided, the node voltage between the first charge transfer connection point C1N and the first branch connection point C2P is 10V, the voltage of the parasitic capacitance Cds-Q3 of the third switching device Q3 is 5V, the voltage of the parasitic capacitance Cds-Q4 of the fourth switching device Q4 is 0V, the voltage of the parasitic capacitance Cds-Q5 of the fifth switching device Q5 is 5V, the voltage of the parasitic capacitance Cds-Q1 of the first switching device Q1 is 0V, and the voltage of the parasitic capacitance Cds-Q2 of the second switching device Q2 is 10V.

[0066] During the first sub-period, i.e., just entering the dead zone, the nineteenth switch Q19 and the twentieth switch Q20 are in the on state, while the twenty-first switch Q21 and the twenty-second switch Q22 are in the off state. The voltage at the first charge transfer junction C1N is pulled down to 0V, and the parasitic capacitance Cds-Q2 of the second switch Q2 discharges from 10V to 0V. At this time, the parasitic capacitances of the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are connected in parallel, and then connected in series with the parasitic capacitance Cds-Q1 of the first switch Q1, resulting in the following... Figure 5 The equivalent model of communication shown.

[0067] See Figure 5 In the AC equivalent model, the first capacitor C2 and the output capacitor of the first output terminal VOUT are equivalent to a short circuit. Furthermore, the parasitic capacitance Cds-Q1 of the first switching device Q1 is less than the capacitance of the parasitic capacitances of the third switching device Q3, the fourth switching device Q4, and the fifth switching device Q5 connected in parallel. When the voltage of the parasitic capacitance Cds-Q1 of the first switching device Q1 is 0V, the parasitic capacitances of the third switching device Q3, the fourth switching device Q4, and the fifth switching device Q5 have no energy release path, thus making it impossible to complete zero-voltage switching (ZVS) (i.e., during the dead time, the voltage of the parasitic capacitance Cds of the switching device that needs to be turned on in the next stage drops to 0V, and the parasitic capacitance Cds of the switching device that needs to be turned off in the next stage compensates for a certain voltage).

[0068] Simulations were conducted on a scheme with added first energy release capacitor C1 and second energy release capacitor C3, compared to a scheme without these additions, and the results were obtained. Figure 6 The efficiency curve shown in the example. See also Figure 6 The P4 curve, or orange curve, represents the mapping relationship between current and efficiency before adding C1 and C3. The P4 optimized ZVS curve, or gray curve, represents the mapping relationship between current and efficiency after adding C1 and C3. Comparative analysis shows that the efficiency of the charge pump circuit has been significantly improved after adding C1 and C3.

[0069] Thus, in this embodiment, the first and second energy release circuits can provide charge transfer channels for some switching devices during the dead time, realizing the transfer of charge stored in the parasitic capacitance of these switching devices. This reduces the switching losses of the charge pump circuit, improves charging efficiency, and reduces temperature rise, thereby enhancing the user experience. For example, in scenarios where electronic devices are used while charging, such as playing games while charging, the load on the electronic device is relatively large, and the temperature rise caused by charging is also high. The solution disclosed in this invention can improve charging efficiency, i.e., shorten charging time; and can reduce switching losses and thus reduce temperature rise, avoiding excessive temperature rise that would affect the user experience.

[0070] In some possible embodiments, a chip is also provided, comprising the above-described... Figures 1-4 The example charge pump circuit.

[0071] Figure 7 This is a block diagram illustrating an electronic device according to an exemplary embodiment. For example, the electronic device 700 may be a smartphone, computer, digital broadcasting terminal, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0072] Reference Figure 7 The electronic device 700 may also include one or more of the following components: processing component 702, memory 704, power supply component 706, multimedia component 708, audio component 710, input / output (I / O) interface 712, sensor component 714, communication component 716, and image acquisition component 718.

[0073] Processing component 702 typically controls the overall operation of electronic device 700, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 702 may include one or more processors 11 to execute computer programs. Furthermore, processing component 702 may include one or more modules to facilitate interaction between processing component 702 and other components. For example, processing component 702 may include a multimedia module to facilitate interaction between multimedia component 708 and processing component 702. In one example, processor 11 may control a charge pump circuit to charge a battery.

[0074] Memory 704 is configured to store various types of data to support the operation of electronic device 700. Examples of such data include computer programs for any application or method operating on electronic device 700, contact data, phone book data, messages, pictures, videos, etc. Memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0075] Power supply component 706 provides power to various components of electronic device 700. Power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 700. Power supply component 706 may include a power chip, which a controller can communicate with to control the power chip to turn a first switching device on or off, thereby enabling or disabling battery power to the motherboard circuitry. In one example, the power supply component 706 includes a charge pump circuit and / or chip as described above.

[0076] The multimedia component 708 includes a screen that provides an output interface between the electronic device 700 and the target object.

[0077] In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touchscreen to receive input information from a target object. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation.

[0078] Audio component 710 is configured to output and / or input audio file information. For example, audio component 710 includes a microphone (MIC) configured to receive external audio file information when electronic device 700 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio file information may be further stored in memory 704 or transmitted via communication component 716. In some embodiments, audio component 710 also includes a speaker for outputting audio file information.

[0079] I / O interface 712 provides an interface between processing component 702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc.

[0080] Sensor assembly 714 includes one or more sensors for providing state assessments of various aspects of electronic device 700. For example, sensor assembly 714 can detect the on / off state of electronic device 700, the relative positioning of components (e.g., the display screen and keypad of electronic device 700), changes in position of electronic device 700 or a component, the presence or absence of contact between a target object and electronic device 700, the orientation or acceleration / deceleration of electronic device 700, and temperature changes of electronic device 700. In this example, sensor assembly 714 may include magnetic sensors, gyroscopes, and magnetic field sensors, and may also include inertial sensors, image sensors, etc., wherein the magnetic field sensor includes at least one of the following: a Hall sensor, a thin-film magnetoresistive sensor, and a magnetic fluid accelerometer.

[0081] Communication component 716 is configured to facilitate wired or wireless communication between electronic device 700 and other devices. Electronic device 700 can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G, 5G, or combinations thereof. In one exemplary embodiment, communication component 716 receives broadcast information or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 716 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0082] In an exemplary embodiment, the electronic device 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital information processors (DSPs), digital information processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microprocessors, or other electronic components.

[0083] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0084] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A charge pump circuit, characterized by, The charge pump circuit includes: a first charge pump branch, a second charge pump branch, a first energy release circuit, a second energy release circuit, and a charge transfer control branch; the first charge pump branch is provided with a first charge transfer connection point and a first branch connection point; the second charge pump branch is provided with a second charge transfer connection point and a second branch connection point; the first energy release circuit is connected in series between the first charge transfer connection point and the first branch connection point; the second energy release circuit is connected in series between the second charge transfer connection point and the second branch connection point; the charge transfer control branch is connected in series between the first charge transfer connection point and the second charge transfer connection point; the second charge pump branch is electrically connected to the first charge pump branch through the first branch connection point; the first charge pump branch is electrically connected to the second charge pump branch through the second branch connection point; The first charge pump branch and the second charge pump branch are configured to alternately output electrical energy in two adjacent control cycles; The first energy release circuit is configured to form a first charge transfer path with the charge transfer control branch during a first sub-period of the dead zone; The second energy release circuit is configured to form a second charge transfer path with the charge transfer control branch during the second sub-period of the dead zone; The charge transfer control branch is configured to alternately switch between the first charge transfer path and the second charge transfer path during the dead zone period to transfer the charge stored in the parasitic capacitance of the first target switch to the parasitic capacitance of the second target switch. The dead zone period refers to the period between two adjacent control cycles, during which the switching devices in both the first charge pump branch and the second charge pump branch are in the off state; the first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.

2. The charge pump circuit of claim 1, wherein, The first charge pump branch includes a first sub-branch, a second sub-branch, and a first flyby capacitor; the second charge pump branch includes a third sub-branch, a fourth sub-branch, and a second flyby capacitor that are electrically connected; the second sub-branch and the third sub-branch are electrically connected to the second branch connection point; the first sub-branch and the fourth sub-branch are electrically connected to the first branch connection point; the first flyby capacitor is electrically connected to the second sub-branch and the first sub-branch respectively; the second flyby capacitor is electrically connected to the fourth sub-branch and the third sub-branch respectively.

3. The charge pump circuit of claim 2, wherein, The first sub-branch includes a first switching device and a second switching device; the first end of the first switching device is electrically connected to the first branch connection point, and the second end of the first switching device is electrically connected to the first end of the second switching device, the second end of the first flying capacitor, and the first charge transfer connection point, respectively; the second end of the second switching device is grounded; and the first energy release circuit is connected in parallel with the first switching device.

4. The charge pump circuit according to any one of claims 1 to 3, characterized in that, The first energy release circuit includes a first energy release capacitor, a first end of which is electrically connected to the first branch connection point, and a second end of which is electrically connected to the first charge transfer connection point.

5. The charge pump circuit of claim 3, wherein, The first sub-branch also includes a first capacitor, a third switching device, a fourth switching device, a fifth switching device, and a sixth switching device; The first end of the third switching device is electrically connected to the first branch connection point, and the second end of the third switching device is electrically connected to the first end of the fourth switching device; the first end of the fifth switching device is electrically connected to the second end of the fourth switching device, and the second end of the fifth switching device is grounded; the first end of the sixth switching device is electrically connected to the first end of the fifth switching device, and the second end of the sixth switching device is electrically connected to the output end. The first terminal of the first capacitor is electrically connected to the first branch connection point, and the second terminal of the first capacitor is electrically connected to the first terminal of the fifth switching device.

6. The charge pump circuit of claim 2, wherein, The second sub-branch includes a seventh switching device, an eighth switching device, and a ninth switching device; the first end of the seventh switching device is electrically connected to the power supply, the second end of the seventh switching device is electrically connected to the first end of the eighth switching device and the first end of the first flying capacitor, the second end of the eighth switching device is electrically connected to the first end of the ninth switching device, and the second end of the ninth switching device is electrically connected to the connection point of the second branch.

7. The charge pump circuit of claim 2, wherein, The third sub-branch includes a tenth switching device and an eleventh switching device; the first terminal of the tenth switching device is electrically connected to the connection point of the second branch, and the second terminal of the tenth switching device is electrically connected to the first terminal of the eleventh switching device, the second terminal of the second flying capacitor, and the second charge transfer connection point, respectively; the second terminal of the eleventh switching device is grounded; the second energy release circuit is connected in parallel with the tenth switching device.

8. The charge pump circuit of claim 1 or 7, wherein, The second energy release circuit includes a second energy release capacitor, the first end of which is electrically connected to the second branch connection point, and the second end of which is electrically connected to the second charge transfer connection point.

9. The charge pump circuit of claim 7, wherein, The third sub-branch also includes a second capacitor, a twelfth switching device, a thirteenth switching device, a fourteenth switching device, and a fifteenth switching device; The first terminal of the twelfth switching device is electrically connected to the second branch connection point, and the second terminal of the twelfth switching device is electrically connected to the first terminal of the thirteenth switching device; the first terminal of the fourteenth switching device is electrically connected to the second terminal of the thirteenth switching device, and the second terminal of the fourteenth switching device is grounded; the first terminal of the fifteenth switching device is electrically connected to the first terminal of the fourteenth switching device, and the second terminal of the fifteenth switching device is electrically connected to the output terminal; the first terminal of the second capacitor is electrically connected to the second branch connection point, and the second terminal of the second capacitor is electrically connected to the first terminal of the fourteenth switching device.

10. The charge pump circuit of claim 2, wherein, The fourth sub-branch includes a sixteenth switching device, a seventeenth switching device, and an eighteenth switching device; the first terminal of the sixteenth switching device is electrically connected to the power supply, the second terminal of the sixteenth switching device is electrically connected to the first terminal of the seventeenth switching device and the first terminal of the second flying capacitor, the second terminal of the seventeenth switching device is electrically connected to the first terminal of the eighteenth switching device, and the second terminal of the eighteenth switching device is electrically connected to the first branch connection point.

11. The charge pump circuit of claim 1, wherein, The charge transfer control branch includes a first charge transfer switching device, a second charge transfer switching device, a third charge transfer switching device, a fourth charge transfer switching device, and a charge transfer inductor; The first terminal of the first charge transfer switching device is electrically connected to the first charge transfer connection point, and the second terminal of the first charge transfer switching device is electrically connected to the first terminal of the charge transfer inductor and the first terminal of the fourth charge transfer switching device, respectively. The first terminal of the third charge transfer switch is electrically connected to the second terminal of the charge transfer inductor and the first terminal of the second charge transfer switch, respectively; the second terminal of the third charge transfer switch is electrically connected to the second charge transfer connection point. The second terminal of the second charge transfer switch is connected to the ground plane, and the second terminal of the fourth charge transfer switch is also connected to the ground plane.

12. A chip, characterized in that, Includes the charge pump circuit as described in any one of claims 1 to 11.

13. An electronic device, characterized in that, include: The processor, battery, charging interface, and charge pump circuit as described in any one of claims 1 to 11; The charge pump circuit is electrically connected to the battery and the charging interface, respectively. The processor is electrically connected to the charge pump circuit; The processor is configured to control the first target switch of the first charge pump branch and the second charge pump branch to switch to the on state and the second target switch to the off state within a control cycle; The processor is configured to control all switching devices of the first charge pump branch and the second charge pump branch to switch to the off state during the dead period; The processor is also configured to output a valid control signal to the charge transfer control branch of the charge pump circuit during the dead time period; The charge transfer control branch is configured to transfer a portion of the charge stored in the parasitic capacitance of the second target switch in the previous control cycle to the parasitic capacitance of the first target switch when a valid control signal is received during the dead zone.

14. An electronic device, characterized in that, include: Processor, battery, charging interface, and chip as described in claim 12; The chip is electrically connected to the battery, the charging interface, and the processor, respectively. The processor is configured to send valid control signals to the first charge pump branch and the second charge pump branch of the charge pump circuit in the chip in each control cycle to switch the second target switch and the first target switch. The processor is also configured to output a valid control signal to the charge transfer control branch of the charge pump circuit during a dead zone period after each control cycle to achieve charge transfer between the second target switch and the first target switch.

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