A drive circuit for suppressing accidental turn-on of power semiconductor devices
By designing a circuit to suppress false turn-on and an active clamping circuit in the drive circuit, and using a combination of transistors and clamping transistors, the problem of false turn-on during IGBT fast turn-on is solved, thereby achieving the stability and reliability of IGBT and avoiding turn-on losses and short-circuit risks.
Patent Information
- Application Number
- CN202522538876.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-11-06
- Estimated Expiration
- 2035-11-28
AI Technical Summary
During rapid IGBT turn-on, parasitic capacitance can cause false turn-on, leading to unnecessary turn-on losses or potentially short circuits due to prolonged false turn-on. Existing technologies struggle to effectively prevent this.
A drive circuit was designed, including a driver, a circuit to suppress false turn-on, and an active clamping circuit. By combining a transistor and a clamping transistor, a low-impedance path is provided to shunt displacement current to prevent false turn-on and to mitigate the risk of overvoltage during turn-off.
It effectively suppresses the false turn-on of IGBTs, reduces turn-on losses, avoids short-circuit risks, and ensures the stability and reliability of the drive circuit.
Smart Images
Figure CN224947542U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power module testing technology, and in particular to a drive circuit for suppressing the accidental turn-on of power semiconductor devices. Background Technology
[0002] For most power semiconductor IGBTs, the IGBT is turned on when the voltage between the gate (G) and emitter (E) is higher than the threshold voltage VGE(th), and turned off when the voltage is lower than VGE(th). Because of the parasitic capacitance Cgc between the collector (C) and gate of the IGBT, a coupling current flows through the gate resistor and drive during rapid turn-on, ultimately creating a voltage rise between the G and E terminals. When this voltage exceeds Vth, it leads to false turn-on. Short-term false turn-on of the IGBT results in unnecessary turn-on losses, while prolonged false turn-on can cause short circuits and device failure. Therefore, this phenomenon must be avoided in practical applications. Utility Model Content
[0003] To address the problems existing in the prior art, this utility model provides a driving circuit for suppressing the accidental turn-on of power semiconductor devices, which is connected to the main power circuit. The main power circuit includes a power semiconductor device and a power supply capacitor, and the collector and emitter of the power semiconductor device are respectively connected to the two ends of the power supply capacitor.
[0004] The driving circuit includes:
[0005] A driver, the output of which is connected to the gate of the power semiconductor device via a gate resistor;
[0006] A circuit to suppress accidental turn-on is connected to the gate of the power semiconductor device, the output terminal of the driver, and the ground terminal of the driver.
[0007] Preferably, the power semiconductor device includes a first IGBT and a second IGBT, wherein the collector of the first IGBT is connected to the positive terminal of the power supply capacitor, the emitter of the first IGBT is connected to the collector of the second IGBT, and the emitter of the second IGBT is connected to the negative terminal of the power supply capacitor;
[0008] The driving circuit includes two lines, corresponding to the first IGBT and the second IGBT respectively.
[0009] Preferably, it also includes an active clamping circuit connected between the gate and collector of the power semiconductor device.
[0010] Preferably, the active clamping circuit includes:
[0011] At least one clamping transistor, wherein each clamping transistor is connected in series between the collector of the power semiconductor device and the gate of the power semiconductor.
[0012] Preferably, the circuit for suppressing false turn-on includes:
[0013] The transistor has its emitter connected to the gate of the power semiconductor device, its base connected to the output of the driver, and its collector connected to the emitter of the power semiconductor and the ground of the driver.
[0014] Preferably, the transistor is a PNP type transistor.
[0015] Preferably, the clamping transistor is a bidirectional Zener diode.
[0016] The above technical solution has the following advantages or beneficial effects:
[0017] The circuit suppressing false turn-on directly addresses the voltage rise caused by displacement current. When displacement current flows through the gate resistor PG, a voltage drop is generated across PG. This voltage drop triggers the circuit suppressing false turn-on to conduct, providing a low-impedance path to shunt the displacement current to the driver's ground terminal, thereby short-circuiting the false turn-on loop and preventing the gate-emitter voltage from exceeding the threshold. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of a drive circuit for suppressing accidental turn-on of power semiconductor devices, which is a preferred embodiment of the present invention. Detailed Implementation
[0019] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment; other embodiments that conform to the spirit of the present invention may also fall within its scope.
[0020] In a preferred embodiment of this utility model, based on the above-mentioned problems existing in the prior art, a driving circuit for suppressing the erroneous turn-on of power semiconductor devices is provided. The circuit is connected to the main power circuit, which includes a power semiconductor device and a power supply capacitor. The collector and emitter of the power semiconductor device are respectively connected to the two ends of the power supply capacitor.
[0021] like Figure 1 As shown, the driving circuit 1 includes:
[0022] The driver Drive, the output of which is connected to the gate of the power semiconductor device IGBT through the gate resistor PG;
[0023] Circuit 3, which suppresses accidental turn-on, connects the gate of the power semiconductor device IGBT, the output terminal of the driver Drive, and the ground terminal of the driver Drive.
[0024] Specifically, when a power semiconductor device, an IGBT, is turned on rapidly, the collector-emitter voltage change rate (du / dt) is high, generating a displacement current through the parasitic capacitance Cgc. This current flows through the gate resistor PG and the driver Drive, creating a voltage rise between the gate and emitter. If the voltage exceeds the threshold VGE(th), it can cause the IGBT to turn on falsely, leading to unnecessary losses or short-circuit risks. In this embodiment, the false turn-on suppression circuit 3 directly suppresses the voltage rise caused by the displacement current. When the displacement current flows through the gate resistor PG, a voltage drop is generated across the gate resistor PG. This voltage drop triggers the false turn-on suppression circuit 3 (such as a PNP transistor) to conduct, providing a low-impedance path to divert the displacement current to the ground terminal of the driver Drive, thereby short-circuiting the false turn-on loop and preventing the gate-emitter voltage from exceeding the threshold.
[0025] The driver Drive and gate resistor PG provide normal drive signal control and work together with the circuit 3 to suppress false turn-on to ensure that the switching performance of the IGBT is not affected during normal operation.
[0026] In a preferred embodiment of the present invention, the power semiconductor device includes a first IGBT and a second IGBT. The collector of the first IGBT is connected to the positive terminal of the power supply capacitor, the emitter of the first IGBT is connected to the collector of the second IGBT, and the emitter of the second IGBT is connected to the negative terminal of the power supply capacitor.
[0027] The drive circuit consists of two lines, corresponding to the first IGBT and the second IGBT respectively.
[0028] In a preferred embodiment of this utility model, such as Figure 1 As shown, the circuit 3 for suppressing accidental turn-on includes:
[0029] A transistor's emitter is connected to the gate of a power semiconductor device, its base is connected to the output of a driver, and its collector is connected to the emitter of the power semiconductor device and the ground of the driver.
[0030] In a preferred embodiment of this invention, the transistor is a PNP type transistor.
[0031] In a preferred embodiment of this utility model, such as Figure 1 As shown, it also includes an active clamping circuit 2, which is connected between the gate and collector of the power semiconductor device IGBT.
[0032] The source clamping circuit 2 includes at least one clamping transistor, which is connected in series between the collector of the power semiconductor device and the gate of the power semiconductor.
[0033] In a preferred embodiment of this invention, the clamping transistor is a bidirectional Zener diode.
[0034] Specifically, such as Figure 1 As shown, the main power circuit consists of power semiconductor devices IGBT1 and IGBT2 connected in series with the power supply capacitor C. The collector (C) of IGBT1 is connected to VCC of the main power circuit, and IGBT1 is called the "upper transistor". The emitter (E) of IGBT2 is connected to the negative terminal of the power supply capacitor C, and IGBT2 is called the "lower transistor". The driving circuit for the upper transistor consists of driver Drive1, gate resistor RG1, clamping transistors TVS1 and TVS2, and PNP transistor T1. The output of driver Drive1 is connected in series with the gate (G) of IGBT1 through RG1. An active clamping circuit is connected in series between the gate (G) and collector (C) of IGBT1. The base of PNP transistor T1 is connected to the output of driver Drive1, the emitter of PNP transistor T1 is connected to the gate (G) of IGBT1, and the collector of PNP transistor T1 is connected to the ground terminal SGND of driver Drive1. The driving circuit connection structure for the lower transistor is similar to that of the upper transistor, except that the serial numbers of identical components are increased accordingly, which will not be repeated here.
[0035] Specifically, in this embodiment, for either the first IGBT1 or the second IGBT2 and its driving circuit, when the IGBT is turned on quickly, the voltage between the collector and emitter of the IGBT will increase rapidly, i.e., there will be a large du / dt. The unit of this parameter is usually V / ns. According to the formula I = C*(du / dt), this will generate a displacement current I that flows through the parasitic capacitance Cgc, the gate resistor RG, and the internal circuit of the driver Drive, eventually reaching the ground terminal SGND of the driver Drive. A voltage rise will be generated at both ends of this circuit, and this voltage will just act on the GE of the IGBT. Once this voltage exceeds the threshold voltage VGE(th) of the IGBT, the IGBT will be turned on. In this invention, there is a PNP transistor as a circuit to suppress false turn-on. When the displacement current is generated, the voltage generated at both ends of RG just turns on the transistor. After the transistor is turned on, the impedance is almost zero, which short-circuits the original false turn-on circuit, thus avoiding the false turn-on of the IGBT.
[0036] Specifically, in this embodiment, the active clamping circuit 2 mainly addresses the overvoltage problem during turn-off, while indirectly supporting false turn-on suppression. When the power semiconductor device IGBT is turned off, the false turn-on suppression circuit may accelerate the turn-off speed, leading to collector-emitter voltage overvoltage. The active clamping circuit 2 (such as a TVS clamping transistor) will break down when the voltage is too high, generating current flowing through the gate-emitter junction, slowing down the turn-off speed, avoiding the risks caused by turn-off overvoltage, and thus ensuring the stability of the drive circuit. The active clamping circuit includes:
[0037] Specifically, in this embodiment, for either the first IGBT or the second IGBT and its driving circuit, when the IGBT is normally turned off, the driving current flows from the emitter (E) of the IGBT to the gate (G), the gate resistor (RG), the driver (Drive), and finally to the ground terminal (SGND) of the driver (Drive). This also creates a voltage across the gate resistor (RG), turning on the PNP transistor. The driving current then flows from the PNP transistor loop to the ground terminal (SGND) of the driver (Drive). Because the loop impedance is very low, the IGBT's turn-off speed is extremely fast, which may lead to a high CE overvoltage. Therefore, this novel experimental design introduces a TVS clamping transistor between the gate (G) and collector (C) of the IGBT. When the IGBT's turn-off voltage (VCE) is higher than the TVS clamping transistor's operating voltage, the TVS clamping transistor will break down, generating a current flowing through the gate (G) and emitter (E) of the IGBT, thus turning on the IGBT again and slowing down its turn-off speed, avoiding the overvoltage risk caused by the PNP transistor.
[0038] The clamping transistors are bidirectional Zener diodes (TVS). The number of TVS transistors depends on the breakdown voltage of a single TVS transistor and the actual voltage value that needs to be protected. The breakdown voltage of a single clamping transistor multiplied by the number of clamping transistors is the voltage value that triggers the protection. This value should not exceed the actual protection voltage value that needs to be protected.
[0039] This embodiment Figure 1 The GND in the circuit includes the driver's ground terminal 0SGND and the ground terminal GND in the main power circuit. These two ground terminals are isolated and are not simply shorted together.
[0040] The above are merely preferred embodiments of the present utility model and are not intended to limit the implementation methods and protection scope of the present utility model. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present utility model.
Claims
1. A driving circuit for suppressing erroneous turn-on of power semiconductor devices, characterized in that, The driving circuit is connected to the main power circuit, which includes a power semiconductor device and a power supply capacitor. The collector and emitter of the power semiconductor device are respectively connected to the two ends of the power supply capacitor. The driving circuit includes: A driver, the output of which is connected to the gate of the power semiconductor device via a gate resistor; A circuit to suppress accidental turn-on is connected to the gate of the power semiconductor device, the output terminal of the driver, and the ground terminal of the driver.
2. The driving circuit according to claim 1, characterized in that, The power semiconductor device includes a first IGBT and a second IGBT. The collector of the first IGBT is connected to the positive terminal of the power supply capacitor, the emitter of the first IGBT is connected to the collector of the second IGBT, and the emitter of the second IGBT is connected to the negative terminal of the power supply capacitor. The driving circuit includes two lines, corresponding to the first IGBT and the second IGBT respectively.
3. The driving circuit according to claim 1, characterized in that, It also includes an active clamping circuit connected between the gate and collector of the power semiconductor device.
4. The driving circuit according to claim 3, characterized in that, The active clamping circuit includes: At least one clamping transistor, wherein each clamping transistor is connected in series between the collector of the power semiconductor device and the gate of the power semiconductor.
5. The driving circuit according to claim 1, characterized in that, The circuit for suppressing accidental turn-on includes: The transistor has its emitter connected to the gate of the power semiconductor device, its base connected to the output of the driver, and its collector connected to the emitter of the power semiconductor and the ground of the driver.
6. The driving circuit according to claim 5, characterized in that, The transistor is a PNP type transistor.
7. The driving circuit according to claim 4, characterized in that, The clamping transistor is a bidirectional Zener diode.