A level conversion circuit and chip

Abstract

This disclosure provides a level conversion circuit and chip, comprising: a first transistor pair connected in a cross-coupled transistor pair structure; a second transistor pair respectively connecting the other end of a first transistor to a second level terminal; the second transistors being in opposite switching states, with the first and second transistors in different branches having the same switching state; a level output node being led out from the connection point of the first and second transistors in the output branch of the branch; an inverting unit coupled to the level output node and the level output terminal; and a pull-down switch connected between the level output node and ground, receiving a switching signal to turn on the pull-down switch in response to power loss. The pull-down switch can pull down the level of the level output node when there is no power supply to the third level terminal, avoiding the risk of the inverting unit failing and conducting due to the parasitic capacitance of the transistors between the first and second level terminals affecting the level of the level output node, thus improving reliability.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and in particular to a level conversion circuit and chip. Background Technology

[0002] A level shifting circuit is an electronic circuit used to convert signals between different voltage levels. It is mainly used in digital circuits or communication systems. When two devices or modules that need to communicate with each other use different logic levels, a level shifting circuit is needed to ensure the correct signal transmission between them and avoid damage to devices or communication errors caused by voltage mismatch.

[0003] The main technologies for level shifting circuits fall into several broad categories: high speed, low power consumption, and temperature compensation design. Among these technologies, some solutions propose high-speed level shifting circuits by introducing resistors to improve the switching speed. Others propose low-power level shifting circuits by designing appropriate circuits to reduce dynamic power consumption during level shifting. Still others propose temperature-compensated level shifting circuits, addressing the problem of excessive leakage current at high temperatures by introducing a temperature compensation module.

[0004] However, the above technologies mainly improve the performance of level conversion circuits in various aspects, and rarely propose reliability design to avoid chip failure caused by various operating conditions. Summary of the Invention

[0005] In view of the shortcomings of the above-mentioned related technologies, the purpose of this disclosure is to provide a level conversion circuit and chip to solve the reliability problem of level conversion circuits in the related technologies.

[0006] The first aspect of this disclosure provides a level shifting circuit, comprising: a first transistor pair, including: a pair of first transistors connected in a cross-coupled transistor pair structure; the pair of first transistors having one connected end led out to a first level terminal; a second transistor pair, including: a pair of second transistors, each connecting the other end of one of the first transistors to a second level terminal to form a pair of branches between the first level terminal and the second level terminal; one of the first level terminal and the second level terminal and the other are respectively connected to a first power supply and a ground terminal; wherein the second transistor pair is set to a switching state by a set of input switching signals, such that the second transistors are in opposite switching states. The first and second transistors in different branches are configured to have the same switching state; a level output node is led out from the connection point of the first and second transistors in the output branch of the pair of branches; an inverting unit is coupled between the level output node and the level output terminal, and coupled to the first power supply and ground; a pull-down switch is connected between the level output node and ground, and has a switch control terminal for setting the switching state; the switch control terminal is coupled to a third level terminal, which is connected to a second power supply; the switch control terminal receives a switching signal to turn on the pull-down switch when the third level terminal loses power.

[0007] In an embodiment of the first aspect, a pair of second transistors are driven by a first switch signal and a second switch signal with opposite levels to be set to different switching states; the second switch signal is obtained by inverting the first switch signal once.

[0008] In an embodiment of the first aspect, the first switch signal and the second switch signal are generated based on the power supply of the second power source.

[0009] In an embodiment of the first aspect, the first transistor is a PMOS; the second transistor is an NMOS; and the first voltage level terminal and the second voltage level terminal are respectively connected to a first power supply and a ground terminal.

[0010] In an embodiment of the first aspect, the inverting unit includes: a pair of NMOS and PMOS, connected together by a common gate and connected to the level output node, and connected together by a common drain and connected to the level output terminal.

[0011] In an embodiment of the first aspect, the pull-down switch is implemented as an NMOS, with its switch control terminal connected to the output terminal of an input inverter, the input terminal of which is connected to the third level terminal.

[0012] In an embodiment of the first aspect, the level shifting circuit includes at least one third transistor pair, comprising: a pair of third transistors connected in parallel with a first transistor; a third transistor and a third transistor; the third transistor being configured to a switching state opposite to that of the connected second transistor.

[0013] In an embodiment of the first aspect, a pair of second transistors are driven by a first switch signal and a second switch signal with opposite levels to be set to different switch states; a pair of third transistors are set to different switch states by a second switch signal and a third switch signal with opposite levels; wherein the first switch signal and the second switch signal are respectively obtained by inverting the third switch signal once and twice.

[0014] In an embodiment of the first aspect, the first switch signal, the second switch signal, and the third switch signal are generated based on the power supply of the second power source.

[0015] A second aspect of this disclosure provides a chip including a level conversion circuit as described in any one aspect of the first aspect.

[0016] As described above, this disclosure provides a level conversion circuit and chip, comprising: a first transistor pair connected in a cross-coupled transistor pair structure; a second transistor pair respectively connecting the other end of a first transistor to a second level terminal; wherein the second transistor pair is set to a switching state by a set of input switching signals, such that the second transistors are in opposite switching states, so that the first transistors and second transistors in different branches have the same switching state; a level output node is led out from the connection point of the first transistor and the second transistor in the output branch of the pair; an inverting unit coupled to the level output node and the level output terminal; and a pull-down switch connected between the level output node and ground, its switching control terminal coupled to a third level terminal, receiving a switching signal to turn on the pull-down switch in response to the loss of power supply. By using the pull-down switch to immediately pull down the level of the level output node when there is no power supply to the third level terminal, the risk of the inverting unit failing and generating a large current due to the influence of the parasitic capacitance of the transistors between the first and second level terminals on the level of the level output node is avoided, thus improving reliability. Attached Figure Description

[0017] Figure 1 A schematic diagram of a level conversion circuit according to an embodiment of the present disclosure is shown.

[0018] Figure 2 exhibit Figure 1 A schematic diagram illustrating the relationship between the first switch signal and the second switch signal in the embodiment.

[0019] Figure 3 A schematic diagram of the structure of the parasitic capacitance equivalent model in the embodiments of this disclosure is shown.

[0020] Figure 4 A schematic diagram of the level conversion circuit in yet another embodiment of this disclosure is shown.

[0021] Figure 5 exhibit Figure 4A schematic diagram illustrating the relationship between the third switch signal, the first switch signal, and the second switch signal in the embodiment. Detailed Implementation

[0022] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the information disclosed herein. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this disclosure can be modified or changed according to different viewpoints and application modules without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.

[0023] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement it. This disclosure may be embodied in many different forms and is not limited to the embodiments described herein.

[0024] In this disclosure, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic represented in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in any one or a group of embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples represented in this disclosure, as well as the features of those different embodiments or examples.

[0025] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this disclosure, "a set" means two or more, unless otherwise explicitly specified.

[0026] For the purpose of clarity, devices unrelated to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0027] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0028] While the terms first, second, etc., are used in some examples herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, module, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, modules, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0029] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this disclosure. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0030] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the message of the present disclosure, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0031] A level shifting circuit is an electronic circuit used to convert signals between different voltage levels. It is mainly used in digital circuits or communication systems. When two devices or modules that need to communicate with each other use different logic levels, a level shifting circuit is needed to ensure the correct signal transmission between them and avoid damage to devices or communication errors caused by voltage mismatch.

[0032] However, level conversion circuits in related technologies are mostly aimed at improving various performance aspects of level conversion circuits, with few mentioning reliability design to avoid chip failures caused by various operating conditions.

[0033] Therefore, this disclosure provides a level conversion circuit and chip that can effectively avoid the failure of the inverting unit connected to the output terminal and effectively improve the reliability of signal output.

[0034] like Figure 1 The diagram shown illustrates the structure of a level conversion circuit in one embodiment of this disclosure.

[0035] In this embodiment, the level conversion circuit 100 includes a first transistor pair 110, a second transistor pair 120, an inverting unit 130, and a pull-down switch M9, etc.

[0036] The first transistor pair 110 includes: a pair of first transistors connected in a cross-coupled transistor pair structure. As an example, Figure 1 The pair of first transistors 110 are implemented as MOS transistors of the same type, exemplarily selected as PMOS. The pair of first transistors are respectively a first PMOS and a second PMOS, represented by M1 and M2. The cross-coupled transistor pair refers to two transistors connected at one end (e.g., common-source connection) to a first voltage level, with their respective drains connected to each other's gates. As an example, M1 and M2 are connected to a first power supply via their common source to obtain a first voltage VCC, which is considered a high level.

[0037] The second transistor pair 120 includes a pair of second transistors, each connecting the other end of a first transistor to a second level terminal to form a pair of branches between the first level terminal and the second level terminal. As an example, the pair of second transistors can be implemented as a MOS of a different type from the first transistor; that is, the second transistor can be an NMOS. In this case, the pair of second transistors is a first NMOS and a second NMOS, represented by M5 and M6 respectively. The drains of M5 and M6 are connected to the drains of M1 and M2 respectively, and the sources of M5 and M6 are connected to the second level terminal. Exemplarily, corresponding to the first level terminal being connected to a first power supply (i.e., obtaining a high level), the second level terminal is connected to ground (GND) (i.e., obtaining a low level), thereby forming two branches between the first power supply and ground: a first branch containing M1 and M5, and a second branch containing M2 and M6. The second branch serves as an output branch, and the connection point between M2 and M6 forms a level output node, coupled to the input terminal of the inverting unit 130.

[0038] The inverting unit 130 is coupled between the level output node and the level output terminal, and is also coupled to the first power supply and ground terminal. It is used to invert the level signal obtained from the level output node to obtain an inverted signal output at the level output terminal, thus completing level conversion. The inverting unit 130 receives high and low level supplies from the first power supply and ground terminal, respectively, for generating the inverted signal. Exemplarily, the inverting unit 130 includes a pair of PMOS and NMOS, namely a third PMOS (labeled M7) and a third NMOS (labeled M8), connected via a common gate and connected to the level output node, and connected via a common drain and connected to the level output terminal VOUT. The source of M7 is connected to the first level terminal. Figure 1 The example obtains a high VCC level. The source of M8 is connected to the second level terminal. Figure 1 In the example, grounding provides a low-level signal.

[0039] The pull-down switch 140, connected between the level output node and ground, has a switch control terminal for setting the switch state. The switch control terminal is coupled to a third level terminal, which is supplied with a second power supply voltage VDD. When the third level terminal loses power, the switch control terminal receives a switch signal that turns on the pull-down switch 140. That is, when there is no VDD power supply to the third level terminal, the pull-down switch 140 turns on, pulling the level of the level output node low to ground.

[0040] As an example, the pull-down switch 140 can be implemented as a transistor, specifically a MOS transistor, with its gate serving as the switch control terminal, and one of its source and drain connected to VDD while the other is connected to GND. For example, in Figure 1 The fourth NMOS in this embodiment, designated M9, has its drain connected to the level output node and its source grounded. Based on NMOS, V... gs Due to the conduction characteristics of Vth, M9 needs to be turned on when the gate is high. To achieve the goal of "the pull-down switch 140 is turned on when there is no VDD power supply at the third level terminal", the third level terminal can be connected to the gate of M9 via an input inverter 140, so that when the VDD power supply is lost and the voltage is low, the inverter unit 130 outputs a high level to turn on M9. The input inverter 140 can be connected to the first power supply terminal and the ground terminal to obtain power. Optionally, the input inverter 140 can be a Schmitt trigger inverter, which has higher stability against noise interference and prevents false triggering of the M9 switching state due to VDD fluctuations.

[0041] Detailed Explanation Figure 1 The circuit principle and the function of the pull-down switch 140.

[0042] M5 and M6 are controlled to switch on and off by a pair of opposite first switch signals CLK1 and second switch signals CLK2. In some embodiments, combined with Figure 2 As shown, the first switch signal CLK1 can be converted into a second switch signal CLK2 by a first inverter Inv1 to ensure that the two signals are strictly opposite in level. In some embodiments, one of CLK1 and CLK2 is an external clock signal. The second power supply corresponding to VDD can be an external power supply that powers the external clock, and the external clock signal is generated by the second power supply. When the second power supply is connected to the third level terminal, the third level terminal receives VDD, i.e., a high level, and one of CLK1 and CLK2 is the external clock signal, while the other is its inverted signal. When the second power supply is not connected to the third level terminal, the third level terminal is a low level, and both CLK1 and CLK2 are low levels.

[0043] Therefore, it can be deduced that when VCC and VDD are powered normally, the gate of M9 is at a low level and not conducting, and it does not pull down the voltage of the output node connected to its drain. If CLK1 and CLK2 are at high and low levels respectively, then M5 is turned on and M6 is turned off. The drain level of M5 is pulled low, causing M2 to conduct. The drain of M2 receives the VCC power supply, pulling up the gate voltage of M1 connected to it, triggering the turn-off state of M1. The high level of the drain of M2 is output to the inverting unit 130, that is, the common gate connection point of M7 and M8. M7 is a PMOS and is therefore turned off, while M8 is an NMOS and is therefore turned on, connecting the ground terminal and VOUT, pulling VOUT low to achieve the inverted output.

[0044] When VCC and VDD are powered normally, the gate of M9 is at a low level and not conducting, so it does not pull down the voltage of the output node connected to its drain. If CLK1 and CLK2 are at low and high levels respectively, then M6 is turned on and M5 is turned off. The drain level of M6 is pulled low, causing M1 to conduct. The drain of M1 receives VCC power and pulls up the gate voltage of M2 connected to it, triggering the turn-off state of M2. The low level of the drain of M6 is output to the inverting unit 130, which is the common gate connection point of M7 and M8. M8 is an NMOS and is therefore turned off. M7 is a PMOS and is therefore turned on, conducting VCC to VOUT, pulling VOUT high, and achieving the inverted output.

[0045] The above describes the normal operating conditions. However, when a certain condition occurs that causes VCC to be powered normally while the external power supply fails and VDD changes to a low level, both CLK1 and CLK2 will be low. At this time, M5, M6, M1, and M2 will all be turned off.

[0046] It's worth noting that parasitic effects may exist between M1, M2, M5, M6, M7, and M8, forming parasitic capacitance between VCC and GND. For example, assuming we ignore the output inverter transistors M7 and M8, the parasitic capacitance from VCC to GND is determined by the following: first, the capacitance from VCC to the drain of M6 is Cgs of M1 and Cds of M2; second, the capacitance from the drain of M6 to GND is Cdg of M6. For transistors of the same size, Cgs may be much larger than Cds and Cdg, and Cds is very small. Similarly, if M7 and M8 are included, the final parasitic effect is determined by the combined capacitance of M1, M2, M6, M7, and M8.

[0047] Therefore, the entire level conversion circuit can be formed as follows: Figure 3 The parasitic capacitance equivalent model shown is that VCC is connected to ground through parasitic capacitances C1 and C2 on both sides of the level output node, and C1 and C2 form a parasitic capacitance voltage divider circuit. When the capacitance ratio of C1 and C2 reaches a preset threshold, an intermediate level between high and low levels will be generated at the level output node between C1 and C2 due to the voltage division. If there is no pull-down switch M9, this intermediate level may turn on M7 and M8 simultaneously, causing the inverting unit to fail and trigger a large current.

[0048] However, in Figure 1 and Figure 2 In the middle, by pulling down switch M9, it can be turned on when the third level is low, which pulls down the drain level of M2, eliminates the intermediate level, and prevents M7 and M8 from being turned on at the same time, avoiding the occurrence of large current and effectively improving reliability.

[0049] When operating normally, with both VDD and VCC at high levels, the gate level of M9 is low and will not conduct, thus affecting timing functionality. Since adding only a few components, such as M9 (or alternatively, an input inverter 140, or changing the MOS type of M9), will not waste much chip area when applied to integrated circuit chips, achieving high reliability with fewer components.

[0050] Figure 1 This application only illustrates the circuit structure in one embodiment. In other embodiments, M1, M2, M5, and M6 can be varied as the cross-coupled main circuit, and are not intended to be the sole embodiment. Figure 1 Limited to.

[0051] like Figure 4 The diagram shows a schematic representation of a level conversion circuit in yet another embodiment of this disclosure.

[0052] In this embodiment, the level conversion circuit 100 includes at least one third transistor pair 150. The third transistor pair 150 includes a pair of third transistors, each connected in parallel with a first transistor. Figure 4 The diagram shows that the third transistor is implemented as an NMOS, namely the fifth NMOS and the sixth NMOS, labeled M3 and M4, respectively. Alternatively, in other embodiments, the third transistor may also be implemented as a PMOS.

[0053] The drain of M3 is connected to the source of M1 and VCC. The source of M3 is connected to the drain of M1 and the drain of M5. The drain of M4 is connected to the source of M2 and VCC. The source of M4 is connected to the drain of M2 and the drain of M6.

[0054] A pair of third transistors are configured to switch in the opposite state to the connected second transistors; that is, M3 and M5 are configured to switch in opposite states, and M4 and M6 are configured to switch in opposite states. Since M5 and M6 are in opposite states during normal operation, M3 and M4 are also in opposite states. Because M1 is in the opposite state to M5, M3 is configured to switch in the same state as M1. Similarly, M4 is configured to switch in the opposite state to M6 and in the same state as M2.

[0055] When M3 and M4 are the same NMOS transistor, opposite switching signals are applied to their gates. As an example, a first switching signal CLK1 is applied to the gate of M4, and a third switching signal CLK3, which is opposite to the first switching signal CLK1, is applied to the gate of M3. In this embodiment, refer to... Figure 5 As shown, the third switching signal CLK3 can be an external clock signal. The first switching signal CLK1 applied to the gates of M5 and M4, and the second switching signal CLK2 applied to the gate of M6, can be obtained by inverting CLK3 once and twice, respectively. The corresponding inverters are the first inverter Inv1 and the second inverter Inv2, to ensure that the three signals are strictly opposite / same level. Therefore, CLK1, CLK2, and CLK3 are generated based on the second power supply VDD. When VDD changes to a low level, CLK1, CLK2, and CLK3 are all low.

[0056] Combination Figure 4 When VCC and VDD are powered normally, the gate of M9 is at a low level and not conducting, so it does not pull down the voltage of the level output node connected to the drain.

[0057] When VCC and VDD are powered normally, the gate of M9 is at a low level and not conducting, so it does not pull down the voltage of the output node connected to its drain. If CLK3, CLK1, and CLK2 are low, high, and low respectively, then M3 is off, M4 is on, M5 is on, and M6 is off. The high level of the source of M4 transmits to the gate of M1, directly triggering the off state of M1. The conduction of M5 pulls down its drain level, making M2 conduct; the drain of M2 is also at a high level, keeping M1 off. The high level of the drain of M2 is output to the inverting unit 130, that is, the common gate connection point of M7 and M8. M7 is a PMOS so it is off, and M8 is an NMOS so it is on, connecting the ground terminal and VOUT, pulling VOUT low to achieve the inverted output.

[0058] When VCC and VDD are powered normally, the gate of M9 is at a low level and not conducting, so it does not pull down the voltage of the output node connected to its drain. If CLK3, CLK1, and CLK2 are high, low, and high respectively, then M3 is on, M4 is off, M6 is on, and M5 is off. The high level of the source of M3 is transmitted to the gate of M2, directly triggering the off state of M2. The drain level of M6 is pulled low. The high level of the source of M3 is transmitted to the gate of M2, directly triggering the off state of M2. M6 conducts, pulling its drain level low, making M1 conduct; the drain of M1 is also at a high level, keeping M2 off. The low level of the drain of M6 is output to the inverting unit 130, that is, the common gate connection point of M7 and M8. M7 is a PMOS, so it is on; M8 is an NMOS, so it is off. This turns on VCC and VOUT, pulling VOUT high to achieve the inverted output.

[0059] As can be seen, in this embodiment, since the conduction of M4 / M3 minimizes the voltage difference between the source and drain of the parallel-connected and also conducted M2 / M1, the current between the two electrodes can be effectively reduced. Moreover, compared to... Figure 1 In this embodiment, by changing the drain voltage of M6 / M5 to a level sufficient to turn on M1 / M2, and then by changing the drain voltage of M1 / M2 to a level sufficient to trigger the turn-off state of M2 / M1, the fast and stable turn-off of M2 / M1 can be more reliably guaranteed, and the level switching speed can be improved.

[0060] The above describes the normal operating conditions. However, when a certain condition occurs that causes VCC to be powered normally while the external power supply fails, resulting in VDD changing to a low level, CLK3, CLK1, and CLK2 will all be at a low level. At this time, M1, M2, M3, M4, and M6 will all be turned off. The parasitic effects of M1 to M8 will also cause... Figure 3 The parasitic capacitance equivalent model shown is shown, except that C1 and C2 may be determined by M1, M2, M4 (considering Cgs of M4), and M6 (M7 and M8 are optional).

[0061] By using the pull-down switch M9, the circuit can be turned on when the third level terminal is low, thus pulling the level of the output node low and eliminating the intermediate level. This prevents M7 and M8 from being turned on simultaneously, avoiding the occurrence of large current and effectively improving reliability.

[0062] When operating normally, with both VDD and VCC at high levels, the gate level of M9 is low and will not conduct, thus affecting timing functionality. Since adding only a few components, such as M9 (or alternatively, an input inverter 140, or changing the MOS type of M9), will not waste much chip area when applied to integrated circuit chips, achieving high reliability with fewer components.

[0063] In another embodiment of this disclosure, a chip may be provided, including the level conversion circuit 100 of any of the above embodiments. The chip may include chips of the type such as memory (e.g., SRAM), flip-flops, latches, storage cells or registers in MCUs / SoCs / FPGAs, oscillators, clock generation circuits, bandgap references, LDOs, control loops in power management chips, or analog comparators.

[0064] In summary, this disclosure provides a level conversion circuit and chip, comprising: a first transistor pair connected in a cross-coupled transistor pair structure; a second transistor pair respectively connecting the other end of a first transistor to a second level terminal; wherein the second transistor pair is set to a switching state by a set of input switching signals, such that the second transistors are in opposite switching states, so that the first transistors and second transistors in different branches have the same switching state; a level output node is led out from the connection point of the first transistor and second transistor in the output branch of the pair; an inverting unit coupled to the level output node and the level output terminal; and a pull-down switch connected between the level output node and ground, its switching control terminal coupled to a third level terminal, receiving a switching signal to turn on the pull-down switch in response to the loss of power supply. By using the pull-down switch to immediately pull down the level of the level output node when there is no power supply to the third level terminal, the risk of the inverting unit failing and generating a large current due to the influence of the parasitic capacitance of the transistors between the first and second level terminals on the level of the level output node is avoided.

[0065] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the protection scope of this disclosure.

Claims

1. A level conversion circuit, characterized in that, include: The first transistor pair includes: a pair of first transistors connected to form a cross-coupled transistor pair structure; the pair of first transistors are led out to a first voltage level at one of their connected ends; The second transistor pair includes: a pair of second transistors, each connecting the other end of a first transistor to a second level terminal to form a pair of branches between the first level terminal and the second level terminal; one of the first level terminal and the other of the second level terminal are respectively connected to a first power supply and a ground terminal; wherein, the second transistor pair is set to a switching state by a set of input switching signals, so that the second transistors are in opposite switching states, so that the first transistors and second transistors in different branches have the same switching state; the connection point of the first transistor and the second transistor of the output branch in the pair of branches leads to a level output node; An inverting unit is coupled between the level output node and the level output terminal, and is also coupled to the first power supply and ground terminal; A pull-down switch, connected between the level output node and ground, has a switch control terminal for setting the switch state; the switch control terminal is coupled to a third level terminal, which is supplied with a second power supply; the switch control terminal receives a switch signal to turn on the pull-down switch when the third level terminal loses power.

2. The level conversion circuit according to claim 1, characterized in that, A pair of second transistors are driven by a first switch signal and a second switch signal with opposite levels to be set to different switching states; the second switch signal is obtained by inverting the first switch signal once.

3. A level conversion circuit according to claim 2, characterized in that, The first switch signal and the second switch signal are generated based on the power supply of the second power source.

4. The level conversion circuit according to claim 1, characterized in that, The first transistor is a PMOS; the second transistor is an NMOS; the first voltage level terminal and the second voltage level terminal are respectively connected to the first power supply and the ground terminal.

5. A level conversion circuit according to claim 1, characterized in that, The inverting unit includes a pair of NMOS and PMOS, which are connected to the common gate and connected to the level output node, and connected to the common drain and connected to the level output terminal.

6. A level conversion circuit according to claim 1, characterized in that, The pull-down switch is implemented as an NMOS, with its switch control terminal connected to the output terminal of an input inverter, and the input terminal of the input inverter connected to the third level terminal.

7. A level conversion circuit according to any one of claims 1-6, characterized in that, Also includes: At least one third transistor pair includes: a pair of third transistors connected in parallel with a first transistor; a third transistor and a third transistor; the third transistor being configured to be in a switching state opposite to that of the connected second transistor.

8. A level conversion circuit according to claim 7, characterized in that, A pair of second transistors are driven by a first switch signal and a second switch signal with opposite levels to be set to different switching states; a pair of third transistors are set to different switching states by a second switch signal and a third switch signal with opposite levels; wherein the first switch signal and the second switch signal are respectively obtained by inverting the third switch signal once and twice.

9. A level conversion circuit according to claim 8, characterized in that, The first switch signal, the second switch signal, and the third switch signal are generated based on the power supply of the second power source.

10. A chip, characterized in that, Includes the level conversion circuit as described in any one of claims 1 to 9.

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