A circuit that can fully utilize the I / O resources of programmable devices

Abstract

This invention discloses a circuit that can fully utilize the I / O resources of a programmable device, comprising: a programmable logic device, a multi-channel buffer, a first switching switch, a second switching switch, and a third switching switch. The multi-channel buffer includes a first channel group, a second channel group, a first enable terminal for controlling the first channel group, and a second enable terminal for controlling the second channel group. This invention employs a JTAG pin multiplexing circuit, configuring JTAG pins as general-purpose I / O or other functional pins in non-debugging mode, thereby achieving efficient utilization of pin resources. The circuit has a simple structure and clear logic control, and can significantly improve the I / O utilization of programmable devices while ensuring the integrity of debugging functions, thus possessing broad application prospects and practical value.

Description

Technical Field

[0001] This utility model relates to the field of programmable device technology, and in particular to a circuit that can make full use of the I / O resources of programmable devices. Background Technology

[0002] I / O resources are extremely valuable for programmable devices, and maximizing their utilization is a crucial consideration during the product definition phase. Programmable devices with varying I / O counts differ significantly in price; a few I / O ports may be the difference in a single solution. Upgrading a programmable device mid-project can lead to a substantial increase in cost. Currently, programmable devices like FPGAs or CPLDs typically include four JTAG pins, primarily used for logic programming and in-circuit debugging. These four pins are generally used exclusively for JTAG and not reused for other functions. However, in designs with limited I / O resources, these four dedicated JTAG pins often result in a waste of valuable I / O.

[0003] Therefore, existing technologies have shortcomings and need to be improved. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a circuit that can fully utilize the I / O resources of programmable devices, applicable to various fields such as network communication, industrial control, and medical applications. It maximizes the utilization rate of I / O resources in programmable devices such as FPGAs or CPLD chips when resources are limited.

[0005] The technical solution of this utility model is as follows: This utility model provides a circuit that can fully utilize the I / O resources of a programmable device, including: a programmable logic device, a multi-channel buffer, a first switching switch, a second switching switch, and a third switching switch. The multi-channel buffer includes a first channel group, a second channel group, a first enable terminal for controlling the first channel group, and a second enable terminal for controlling the second channel group. The first channel group and the second channel group each include four channels. The first enable terminal is electrically connected to the first switching switch, and the second enable terminal is electrically connected to the second switching switch. The programmable logic device includes a JTAG enable terminal, which is electrically connected to the third switching switch. The four data pins of the JTAG of the programmable logic device are electrically connected to one end of the four channels of the corresponding first channel group, and the other end of the four channels of the first channel group is electrically connected to the corresponding JTAG physical interface terminal. The four data pins of the JTAG of the programmable logic device are also electrically connected to one end of the four channels of the corresponding second channel group, and the other end of the four channels of the second channel group is electrically connected to the corresponding I / O terminal.

[0006] Furthermore, the first switch, the second switch, and the third switch are all jumper caps.

[0007] By adopting the above solution, this utility model employs a JTAG pin multiplexing circuit. By configuring the JTAG pins as general-purpose I / O or other functional pins in non-debugging mode, it achieves efficient utilization of pin resources. This circuit has a simple structure and clear logic control, and can significantly improve the I / O utilization of programmable devices while ensuring the integrity of the debugging function. It has broad application prospects and practical value. Attached Figure Description

[0008] Figure 1 This is a structural schematic diagram of an embodiment of the present utility model. Detailed Implementation

[0009] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0010] Please accept this. Figure 1 In this embodiment, the present invention provides a circuit that can fully utilize the I / O resources of a programmable device, including: a programmable logic device U3, a multi-channel buffer U2, a first switching switch CN16, a second switching switch CN17, and a third switching switch CN18. The multi-channel buffer U2 includes a first channel group 1A-1Y, a second channel group 2A-2Y, a first enable terminal 1OE for controlling the first channel group, and a second enable terminal 2OE for controlling the second channel group. Both the first and second channel groups include four channels. The first enable terminal 1OE is electrically connected to the first switching switch CN16, and the second enable terminal 2OE is electrically connected to the second switching switch CN17. The programmable logic device U3 includes a JATG enable pin (pin 41), which is electrically connected to the third switching switch CN18. The four data pins of the JTAG interface of the programmable logic device U3 (pins 45, 44, 47, and 48) are electrically connected to one end of the four channels of the corresponding first channel group. The other ends of the four channels of the first channel group are electrically connected to the corresponding JTAG physical interface CON1. ​​The four data pins of the JTAG interface of the programmable logic device U3 are also electrically connected to one end of the four channels of the corresponding second channel group. The other ends of the four channels of the second channel group are electrically connected to the corresponding IO terminals. It is worth noting that in this embodiment, the multi-channel buffer U2 is model 74LVC2244A, which is an eight-channel buffer with three outputs, enabling unidirectional transmission. In different embodiments, if bidirectional communication is required, a multi-channel buffer with bidirectional communication functionality can also be selected.

[0011] Furthermore, in this embodiment, the first switching switch CN16, the second switching switch CN17, and the third switching switch CN18 are all jumper caps.

[0012] Please continue to refer to the following: Figure 1 In this solution, during operation: the first enable pin 1OE and the second enable pin 2OE of the multi-channel buffer U2 (or driver) are connected in series in the circuit, and jumper caps (switching switches) are designed on the corresponding enable pins to facilitate different jumper connections for different application scenarios. In normal operating mode, the second switching switch CN17 is switched to pins 1-2 (2OE pull-down), and the first switching switch CN16 is switched to pins 2-3 (1OE pull-up). At this time, the buffer 2A-2Y channels are open, and the 1A-1Y output is high impedance. The programmable device can use these JTAG IO pins for IO sampling, including temperature, speed, status indication, etc. At the same time, the third switching switch CN18 needs to be switched to pins 1-2 (JTAG_EN pull-down) to disable the JTAG function of the programmable device. In programming mode, which is when the programmable device needs to be debugged or its logic updated online, the JTAG function needs to be activated. Similarly, the third switch CN18 needs to be switched to pins 2-3 to enable JTAG, while the second switch CN17 is switched to pins 2-3 with a 2OE pull-up, and the first switch CN16 is switched to pins 1-2 with a 1OE pull-down. The buffer 2A-2Y channels are set to high impedance, and the 1A-1Y channels are enabled. The programmable device can then use the 1A-1Y channel to achieve JTAG communication and connect normally with the host computer to enter JTAG programming mode.

[0013] As can be seen, this solution effectively integrates the utilization efficiency of existing I / O ports, ensuring maximum resource utilization without sacrificing functional integrity. This solution is particularly suitable for project scenarios with high requirements for cost control and hardware integration, providing a brand-new technical approach for product design.

[0014] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A circuit that can fully utilize the I / O resources of a programmable device, characterized in that, include: The system includes a programmable logic device (PLD), a multi-channel buffer, a first switching switch, a second switching switch, and a third switching switch. The multi-channel buffer includes a first channel group, a second channel group, a first enable terminal for controlling the first channel group, and a second enable terminal for controlling the second channel group. Each of the first and second channel groups includes four channels. The first enable terminal is electrically connected to the first switching switch, and the second enable terminal is electrically connected to the second switching switch. The PLD includes a JTAG enable terminal, which is electrically connected to the third switching switch. The four data pins of the PLD's JTAG are electrically connected to one end of the four channels of the corresponding first channel group, and the other ends of the four channels of the first channel group are electrically connected to the corresponding JTAG physical interface terminals. The four data pins of the PLD's JTAG are also electrically connected to one end of the four channels of the corresponding second channel group, and the other ends of the four channels of the second channel group are electrically connected to the corresponding I / O terminals.

2. The circuit according to claim 1 that can fully utilize the I / O resources of a programmable device, characterized in that, The first, second, and third switching switches are all jumper caps.

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