A link structure of a fixed frequency band synthesis method

Abstract

This utility model discloses a link structure for a fixed frequency band synthesis method, including a first loop, a second loop, and a controller. The first loop includes a reference loop phase detector, a reference loop filter, a reference loop VCO, a reference loop power divider, a frequency divider, and a low-pass filter. When the input frequency is processed sequentially by the reference loop phase detector, reference loop filter, reference loop VCO, reference loop power divider, frequency divider, and low-pass filter, reference signals F1 to Fn are generated and used as the input signals of the second loop. The second loop includes a main loop phase detector, main loop filter, main loop VCO, and main loop power divider. When the reference signals F1 to Fn are processed sequentially by the main loop phase detector, main loop filter, main loop VCO, and main loop power divider, a step signal is finally output. This application achieves a small step size and low spurious wideband output synthesized signal.

Description

Technical Field

[0001] This utility model belongs to the field of radio frequency and microwave technology, and relates to a link structure of a fixed frequency band synthesis method, specifically a link structure of a broadband universal 10-20G frequency synthesis method. Background Technology

[0002] In recent years, with the rapid development of various electronic device technologies, the demand for the generalization of frequency synthesizers has become increasingly urgent. The 2-18G ultra-wideband frequency converter requires a wideband frequency hopping local oscillator signal.

[0003] Typical specifications for broadband frequency-hopping local oscillator signals are as follows: spurious emissions below 65dBc, frequency hopping step of 1MHz, frequency output range of 10-20GHz, and phase noise better than -90dBc / Hz @1KHz.

[0004] Faced with such performance indicators, using a single-loop approach to achieve broadband frequency synthesis would have drawbacks such as spurious errors at integer boundaries and a large workload for debugging registers, thus failing to meet the requirements. Utility Model Content

[0005] The purpose of this invention is to propose a link structure for a fixed frequency band synthesis method, which not only has a universal, small-step, and broadband frequency synthesis local oscillator source, but also has a compact structure and small size, and can be used on multiple platforms.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows: A link structure for a fixed frequency band synthesis method is characterized by comprising a first loop, a second loop, and a controller, wherein the first loop and the second loop are respectively connected to the controller, and the controller supplies control signals to the first loop and the second loop; The first loop is a reference loop, including a reference loop phase detector, a reference loop loop filter, a reference loop VCO, a reference loop power divider, a frequency divider, and a low-pass filter. The reference loop phase detector is connected to the reference loop loop filter, the reference loop loop filter is connected to the reference loop VCO, the reference loop VCO is connected to the reference loop power divider, the reference loop power divider is connected to the frequency divider and the reference loop phase detector, and the frequency divider is connected to the low-pass filter. When the input frequency is processed sequentially by the reference loop phase detector, the reference loop loop filter, the reference loop VCO, the reference loop power divider, the frequency divider, and the low-pass filter, a reference signal F1 to Fn with frequency hopping low harmonics is generated, which is used as the input signal of the second loop. The second loop is the main loop, which includes a main loop phase detector, a main loop filter, a main loop VCO, and a main loop power divider. The main loop phase detector is connected to the main loop filter, the main loop filter is connected to the main loop VCO, the main loop VCO is connected to the main loop power divider, and the main loop power divider is connected to the main loop phase detector. When the frequency-hopping low harmonic reference signals F1 to Fn are processed sequentially by the main loop phase detector, the main loop filter, the main loop VCO, and the main loop power divider, a step signal is output.

[0007] As a preferred technical solution of the present invention: the reference ring phase detector is used to perform phase detection on the input and output frequency signals, and convert the detected phase difference signal into a voltage signal output; The reference loop filter is used to filter the input voltage signal; The reference ring VCO is used to generate jumpable signals; The reference loop power divider is used to divide the input jumpable signal; The frequency divider and low-pass filter are used to switch the frequency of the input hopping signal and filter out the high-frequency components in the hopping signal while retaining the low-frequency components, thereby generating a reference signal F1 to Fn for hopping frequency low harmonics.

[0008] As a preferred technical solution of the present invention: the main ring phase detector is used to perform phase detection on the input and output reference signals, and convert the detected phase difference signal into a voltage signal for output; The main loop filter is used to filter the input voltage signal; The main loop VCO is used to generate jumpable signals; The main loop power divider is used to divide the input jumpable signal.

[0009] As a preferred embodiment of the present invention, the typical phase noise of the stepping signal is <-90dBc@1KHz; Strays: <-65dBc; Frequency hopping step: ≤1MHz; Synthesis range: 10-20GHz.

[0010] As a preferred technical solution of the present invention: it also includes a register, which is connected to the controller. When the reference loop performs frequency hopping to a certain reference signal Fm (m=1,2,3,…,n), and the integer boundary spurious signals generated by the main loop are outside the preset range, then the Fm (m=1,2,3,…,n) at this time is selected as the output of the reference loop, and Fm (m=1,2,3,…,n) is used as the reference signal of the main loop. The controller distributes relevant registers to the reference loop and the main loop respectively.

[0011] As a preferred embodiment of the present invention, the controller is a PLC.

[0012] Compared with the prior art, the beneficial effects of this utility model are as follows: The link structure proposed in this invention, through its designed dual-ring structure, effectively avoids the large integer boundary spuriousness that occurs in the single-ring structure, and achieves a wideband output synthesized signal with small step size and low spuriousness. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the principle framework of this utility model; Figure 2 This is a flowchart illustrating the principle of this utility model.

[0014] List of reference numerals in the attached diagram: 1. Reference ring phase detector; 2. Reference ring loop filter; 3. Reference ring VCO; 4. Reference ring power divider; 5. Frequency divider; 6. Low-pass filter; 7. Main ring phase detector; 8. Main ring loop filter; 9. Main ring VCO; 10. Main ring power divider; 11. Controller. Detailed Implementation

[0015] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments: like Figure 1 As shown, this utility model proposes a link structure for a fixed frequency band synthesis method, including a first loop, a second loop, and a controller 11. The first loop and the second loop are respectively connected to the controller 11, and the controller 11 supplies control signals to the first loop and the second loop. The first loop is a reference loop, including a reference loop phase detector 1, a reference loop filter 2, a reference loop VCO 3, a reference loop power divider 4, a frequency divider 5, and a low-pass filter 6. The reference loop phase detector 1 is connected to the reference loop filter 2, the reference loop filter 2 is connected to the reference loop VCO 3, the reference loop VCO 3 is connected to the reference loop power divider 4, the reference loop power divider 4 is connected to the frequency divider 5 and the reference loop phase detector 1, and the frequency divider 5 is connected to the low-pass filter 6. When the input frequency is processed sequentially by the reference loop phase detector 1, the reference loop filter 2, the reference loop VCO 3, the reference loop power divider 4, the frequency divider 5, and the low-pass filter 6, a reference signal F1 to Fn with frequency hopping low harmonics is generated, which is used as the input signal of the second loop. The second loop is the main loop, including a main loop phase detector 7, a main loop filter 8, a main loop VCO 9, and a main loop power divider 10. The main loop phase detector 7 is connected to the main loop filter 8, the main loop filter 8 is connected to the main loop VCO 9, the main loop VCO 9 is connected to the main loop power divider 10, and the main loop power divider 10 is connected to the main loop phase detector 7. When the frequency-hopping low harmonic reference signals F1 to Fn are processed sequentially by the main loop phase detector 7, the main loop filter 8, the main loop VCO 9, and the main loop power divider 10, a step signal is output.

[0016] In the reference loop: The reference ring phase detector 1 is used to perform phase detection on the input and output frequency signals and convert the detected phase difference signal into a voltage signal for output. The reference loop filter 2 is used to filter the input voltage signal; The reference ring VCO3 is used to generate a jumpable signal; The reference loop power divider 4 is used to divide the input jumpable signal; The frequency divider 5 and the low-pass filter 6 are used to switch the frequency of the input hopping signal and filter out the high-frequency components in the hopping signal while retaining the low-frequency components, thereby generating a reference signal F1 to Fn for hopping frequency low harmonics.

[0017] On the main ring road: The main ring phase detector 7 is used to perform phase detection on the input and output reference signals and convert the detected phase difference signal into a voltage signal for output. The main loop filter 8 is used to filter the input voltage signal; The main ring VCO9 is used to generate jumpable signals; The main loop power divider 10 is used to divide the input jumpable signal.

[0018] It also includes registers connected to controller 11. When the reference loop hops to a certain reference signal Fm (m=1,2,3,…,n), and the integer boundary spurious signals generated by the main loop are outside a preset range, then Fm (m=1,2,3,…,n) at this time is selected as the output of the reference loop, and Fm (m=1,2,3,…,n) is used as the reference signal of the main loop. Controller 11 distributes relevant registers to the reference loop and the main loop respectively. Controller 11 is a PLC.

[0019] like Figure 2As shown, the control flow of this utility model is as follows: The reference loop first generates a first reference F1 as the reference signal of the main loop. It calculates whether the integer boundary spurious signals generated by the main loop are within 5MHz of the final output signal. If so, the reference loop hops to the second reference F2. It calculates whether the integer boundary spurious signals generated by the main loop are within 5MHz of the final output signal. If so, the reference loop hops to the third reference F3. It calculates whether the integer boundary spurious signals generated by the main loop are within 5MHz of the final output signal. The above operation is repeated in sequence until the reference loop hops to a certain reference signal Fm (m=1,2,3,…,n). It is calculated that the integer boundary spurious signals generated by the main loop are outside the 5MHz range of the final output signal. The selected Fm (m=1,2,3,…,n) is used as the output of the reference loop, and Fm (m=1,2,3,…,n) is used as the reference signal of the main loop. The controller 11 distributes the relevant registers to the reference loop and the main loop respectively.

[0020] The final phase-locked loop synthesizes a step signal of 10-20 GHz. The typical phase noise of this frequency source is: <-90dBc@1KHz; spurious noise: <-65dBc; frequency hopping step: ≤1MHz; synthesis range: 10-20GHz.

[0021] Based on the above technical solution, the link structure proposed in this utility model, through the designed double-ring structure, effectively avoids the large integer boundary spurious characteristics that occur in the single-ring structure, and realizes a broadband output synthesized signal with small step size and low spuriousness.

[0022] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any other way. Any modifications or equivalent changes made based on the technical essence of the present utility model shall still fall within the scope of protection claimed by the present utility model.

Claims

1. A link structure for a fixed frequency band synthesis method, characterized in that, It includes a first loop, a second loop, and a controller (11), wherein the first loop and the second loop are respectively connected to the controller (11), and the controller (11) delivers control signals to the first loop and the second loop; The first loop is a reference loop, including a reference loop phase detector (1), a reference loop loop filter (2), a reference loop VCO (3), a reference loop power divider (4), a frequency divider (5), and a low-pass filter (6). The reference loop phase detector (1) is connected to the reference loop loop filter (2), the reference loop loop filter (2) is connected to the reference loop VCO (3), the reference loop VCO (3) is connected to the reference loop power divider (4), the reference loop power divider (4) is connected to the frequency divider (5) and the reference loop phase detector (1), and the frequency divider (5) is connected to the low-pass filter (6). When the input frequency is processed sequentially by the reference loop phase detector (1), the reference loop loop filter (2), the reference loop VCO (3), the reference loop power divider (4), the frequency divider (5), and the low-pass filter (6), a reference signal F1 to Fn with frequency hopping low harmonics is generated and used as the input signal of the second loop. The second loop is the main loop, including a main loop phase detector (7), a main loop filter (8), a main loop VCO (9), and a main loop power divider (10). The main loop phase detector (7) is connected to the main loop filter (8), the main loop filter (8) is connected to the main loop VCO (9), the main loop VCO (9) is connected to the main loop power divider (10), and the main loop power divider (10) is connected to the main loop phase detector (7). When the frequency-hopping low harmonic reference signals F1 to Fn are processed sequentially by the main loop phase detector (7), the main loop filter (8), the main loop VCO (9), and the main loop power divider (10), a step signal is output.

2. The link structure of the fixed frequency band synthesis method according to claim 1, characterized in that, The reference ring phase detector (1) is used to perform phase detection on the input and output frequency signals and convert the detected phase difference signal into a voltage signal output. The reference loop filter (2) is used to filter the input voltage signal; The reference ring VCO(3) is used to generate jumpable signals; The reference loop power divider (4) is used to distribute the power of the input jumpable signal; The frequency divider (5) and low-pass filter (6) are used to switch the frequency of the input hopping signal and filter out the high-frequency components in the hopping signal while retaining the low-frequency components, thereby generating a reference signal F1 to Fn for hopping frequency low harmonics.

3. The link structure of the fixed frequency band synthesis method according to claim 1, characterized in that, The main ring phase detector (7) is used to perform phase detection on the input and output reference signals and convert the detected phase difference signal into a voltage signal for output. The main loop filter (8) is used to filter the input voltage signal; The main loop VCO(9) is used to generate jumpable signals; The main loop power divider (10) is used to distribute the power of the input jumpable signal.

4. The link structure of the fixed frequency band synthesis method according to claim 1, characterized in that, Typical phase noise of the step signal: <-90dBc@1KHz; Strays: <-65dBc; Frequency hopping step: ≤1MHz; Synthesis range: 10-20GHz.

5. The link structure of the fixed frequency band synthesis method according to claim 1, characterized in that, It also includes registers, which are connected to the controller (11). When the reference loop hops to a certain reference signal Fm (m=1,2,3,…,n), the integer boundary spurious signals generated by the main loop are outside the preset range. Then, Fm (m=1,2,3,…,n) is selected as the output of the reference loop, and Fm (m=1,2,3,…,n) is used as the reference signal of the main loop. The controller (11) distributes relevant registers to the reference loop and the main loop respectively.

6. The link structure of the fixed frequency band synthesis method according to claim 5, characterized in that, The controller (11) is a PLC.

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