An airborne audio and video processing board based on Hi3559AV100

Abstract

This utility model discloses an airborne audio and video processing board based on the Hi3559AV100, including a SOC chip, and connected to the SOC chip are a FLASH chip, DDR memory, a watchdog circuit, an Ethernet PHY circuit, an RS232 transceiver circuit, an audio processing circuit, an eMMC memory, a voltage detection circuit, a temperature monitoring circuit, an LVDS video transceiver circuit, an HDMI video transmission circuit, a BT.1120 video transmission circuit, a power conversion circuit, and a connector. This utility model can effectively improve airborne audio and video processing capabilities and achieve controllability of the technical solution.

Description

Technical Field

[0001] This utility model relates to the field of airborne audio and video processing, and specifically provides an airborne audio and video processing board based on Hi3559AV100. Background Technology

[0002] Airborne audio and video processing equipment is a crucial component of airborne avionics systems. With advancements in electronic technology, the hardware and software performance of airborne audio and video processing equipment has continuously improved. This equipment has evolved from its traditional single recording and playback function to include the transmission and reception of high-definition audio and video data. Therefore, the application of airborne audio and video processing equipment with abundant computing resources, high-performance signal processing capabilities, low power consumption, and high reliability in airborne avionics systems is a current development trend. Utility Model Content

[0003] The purpose of this invention is to provide an airborne audio and video processing board based on Hi3559AV100, which can effectively improve airborne audio and video processing capabilities and achieve controllability of the technical solution.

[0004] The objective of this invention is achieved through the following technical solution:

[0005] An airborne audio and video processing board based on Hi3559AV100 includes a SOC chip, an audio processing circuit, an LVDS video transceiver circuit, an HDMI video transmission circuit, and a BT.1120 video transmission circuit.

[0006] The SOC chip in question is model number Hi3559AV100;

[0007] The audio port of the SOC chip is connected to the audio processing circuit via an audio input / output interface, which is used to interface with the on-chip or off-chip audio codec to complete the input and output of audio data;

[0008] The sensor serial input video interface of the SOC chip is configured as an LVDS video transceiver port. The LVDS video transceiver circuit is electrically connected to the MIPI Rx raw video data input port and MIPIDSI video data output port of the SOC chip to process LVDS interface video signals.

[0009] Some of the output video interfaces of the SOC chip are configured as HDMI video transmission ports. The HDMI video transmission circuit is electrically connected to the HDMI video transmission port configuration of the SOC chip to transmit HDMI interface video signals.

[0010] Part of the output video interface of the SOC chip is configured as a BT.1120 video transmission port. The BT.1120 video transmission circuit is electrically connected to the BT.1120 video transmission port of the SOC chip to transmit BT.1120 interface video signals.

[0011] Preferably, the audio processing circuit includes an instrumentation amplifier circuit, a first-order low-pass filter, and a first-order RC high-pass filter for input and output processing of analog differential audio signals.

[0012] Preferably, the audio processing circuit is model SX33178MF; the LVDS video transceiver circuit is model Hi3559AV100; the HDMI video transmission circuit is model Hi3559AV100; and the BT.1120 video transmission circuit is model Hi3559AV100.

[0013] Preferably, the airborne audio and video processing board based on Hi3559AV100 also includes an Ethernet PHY circuit and an RS232 transceiver circuit.

[0014] The Ethernet port of the SOC chip is connected to the gigabit network transformer via RGMII, and electrically connected to the external connector via the Ethernet PHY circuit to realize the physical layer connection of Ethernet.

[0015] Some serial ports of the SOC chip are configured as UART ports, and the RS232 transceiver circuit is electrically connected to the UART port of the SOC chip to realize the transmission of RS232 data.

[0016] Some high-speed serial ports of the SOC chip are configured as PCIe ports, including one set of PCIe x2 channels, to realize PCIe data stream communication;

[0017] Some serial ports of the SOC chip are configured as I2C ports, and some I2C ports are used to connect to external I2C communication interfaces.

[0018] Some serial ports of the SOC chip are configured as SPI ports, and some SPI ports are used to connect to external SPI communication interfaces.

[0019] Some serial ports of the SOC chip are configured as USB ports to connect to external USB communication interfaces;

[0020] Some GPIO ports of the SOC chip are configured as discrete signal ports to connect to external discrete signals.

[0021] Preferably, the Ethernet PHY circuit is model SJ16T245LJFC-1 and B88E1111MB; the RS232 transceiver circuit is model CSTXS0108 and SJ3232S.

[0022] Preferably, the airborne audio and video processing board based on Hi3559AV100 also includes a FLASH chip, DDR memory, watchdog circuit, eMMC memory, connector, power conversion circuit, voltage detection circuit and temperature monitoring circuit.

[0023] Some serial ports of the SOC chip are configured as I2C ports. The voltage detection circuit is electrically connected to some I2C ports of the SOC chip to detect the operating voltage inside the board. The temperature monitoring circuit is electrically connected to some I2C ports of the SOC chip to monitor the temperature of the board.

[0024] Some serial ports of the SOC chip are configured as SPI ports, and the FLASH chip is electrically connected to the SPI port of the SOC chip in the SPI mode to reserve storage system programs;

[0025] The eMMC memory is electrically connected to the eMMC port of the SOC chip to store system programs and record board self-test data and abnormal error data;

[0026] The connector is electrically connected to the JTAG port and external port of the SOC chip for burning system files, online debugging, and external communication.

[0027] The DDR memory consists of four chips. Two chips are electrically connected to the DDR0 port of the SOC chip using a FLY-BY topology to form a 32-bit DDR for system cache. The other two chips are electrically connected to the DDR1 port of the SOC chip using a FLY-BY topology to serve as a data cache for high-speed signals.

[0028] The watchdog circuit is electrically connected to the reset port of the SOC chip's GPIO for system reset.

[0029] The power conversion circuit is electrically connected to each power port and external connector of the SOC chip, and converts the input DC power into various operating voltages required by the SOC chip before supplying them to the SOC chip.

[0030] Preferably, the FLASH chip is model SG35M2GMB; the DDR memory is model HSMD4-512M16-PBGM; the watchdog circuit is model AiP74LVC1G08 and SJ706TAHV; the eMMC memory is model KWYY32GJDEA; the voltage detection circuit is model JAD7998; the temperature monitoring circuit is model HWD1668MAE; the power conversion circuit is model HCE4644AMB and HCE8025MB; and the connector is a JTAG connector, model LMD-107-02-GD.

[0031] Preferably, the SOC chip also includes a minimum system for system initialization, system status monitoring, and communication and port control.

[0032] The beneficial effects of this utility model are as follows:

[0033] This utility model's airborne audio and video processing board uses Huawei HiSilicon Hi3559AV100 as its core processing unit, integrating dual-core A73 and dual-core A53, a big.LITTLE architecture, and a dual operating system, achieving a balance between power consumption and startup time; its high-performance input signal processing capabilities enable high-speed audio and video compression processing and storage; and it adopts advanced 12nm low-power process and miniaturized packaging to support product miniaturization design.

[0034] The airborne audio and video processing board of this utility model utilizes the audio and video port of the SOC to implement multi-protocol audio and video encoding and decoding through software, supports H.264 / H.265 / MJPEG / JPEG encoding formats, supports multiple bitrate control modes, and has a maximum output bitrate of up to 200Mbps;

[0035] This utility model's airborne audio and video processing board integrates audio and video input and output interfaces, supports multiple video input and output interfaces, supports external audio codecs, supports dual-channel microphone differential input, and reduces background noise.

[0036] This utility model's airborne audio and video processing board supports multiple communication methods such as PCIe, Ethernet, and UART for data transmission, enabling high-speed data flow access between boards. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of an airborne audio and video processing board based on Hi3559AV100. Detailed Implementation

[0038] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0039] An airborne audio and video processing board based on Hi3559AV100, such as Figure 1 As shown, it includes SOC chip 1, audio processing circuit 7, LVDS video transceiver circuit 11, HDMI video transmission circuit 12, BT.1120 video transmission circuit 13, Ethernet PHY circuit 5, RS232 transceiver circuit 6, FLASH chip 2, DDR memory 3, watchdog circuit 4, eMMC memory 8, power conversion circuit 14, external connector 15, voltage detection circuit 9, temperature monitoring circuit 10, and external connector 16, etc.

[0040] The audio port of SOC chip 1 is connected to audio processing circuit 7 via an AIAO (AI Audio Input / Output Interface) to interface with on-chip or off-chip audio codecs, enabling audio data input and output for functions such as recording, intercom, and playback. Audio processing circuit 7 should also include an instrumentation amplifier circuit, a first-order low-pass filter, and a first-order RC high-pass filter for processing the input and output of analog differential audio signals.

[0041] The Sensor serial input video interface of SOC chip 1 is configured as an LVDS video transceiver port. The LVDS video transceiver circuit 11 is electrically connected to the MIPI Rx raw video data input port and MIPIDSI video data output port of the SOC chip to process LVDS interface video signals and supports multiple working modes.

[0042] The SOC chip 1 has a portion of its output video interface configured as an HDMI video transmission port, supporting up to 4K@60fps output. The HDMI video transmission circuit 12 is electrically connected to the HDMI video transmission port of the SOC chip to transmit HDMI interface video signals.

[0043] Part of the output video interface of SOC chip 1 is configured as a BT.1120 video transmission port. The BT.1120 video transmission circuit 13 is electrically connected to the BT.1120 video transmission port of the SOC chip to transmit BT.1120 interface video signals.

[0044] The Ethernet port of SOC chip 1 is connected to the gigabit network transformer via RGMII, and electrically connected to the external connector via Ethernet PHY circuit 5 to realize the physical layer connection of the board's Ethernet, enabling the board to be debugged and upgraded online.

[0045] Some serial ports of SOC chip 1 are configured as UART ports with a baud rate of 115200. The RS232 transceiver circuit 6 is electrically connected to the UART port of the SOC chip to realize RS232 data transmission, enabling the burning of system files and online debugging.

[0046] Some of the high-speed serial ports of SOC chip 1 are configured as PCIe ports, including one set of PCIe x2 channels, to realize PCIe data stream communication.

[0047] Some serial ports of SOC chip 1 are configured as I2C ports, and some I2C ports are used to connect to external I2C communication interfaces. The voltage detection circuit 9 is electrically connected to some I2C ports of the SOC chip to detect the operating voltages such as 5V, 3.3V, and 2.5V within the board; the temperature monitoring circuit 10 is electrically connected to some I2C ports of the SOC chip to monitor the temperature of the board.

[0048] Some serial ports of SOC chip 1 are configured as SPI ports, and some SPI ports are used to connect to an external SPI communication interface. The FLASH chip 2 is electrically connected to the SPI port of the SOC chip via SPI to reserve space for storing system programs.

[0049] Some serial ports of SOC chip 1 are configured as USB ports to connect to external USB communication interfaces.

[0050] Some GPIO ports of SOC chip 1 are configured as discrete signal ports to connect to external discrete signals.

[0051] The eMMC memory 8 is electrically connected to the eMMC port of the SOC chip to store system programs and record board self-test data, abnormal error data, etc.

[0052] The connector 15 is electrically connected to the JTAG port and the external port of the SOC chip 1 for burning system files, online debugging, and external communication.

[0053] The DDR memory 3 consists of four chips. Two chips are electrically connected to the DDR0 port of the SOC chip 1 using a FLY-BY topology to form a 32-bit DDR for system cache. The other two chips are also electrically connected to the DDR1 port of the SOC chip using a FLY-BY topology for high-speed signal data cache.

[0054] The watchdog circuit 4 is electrically connected to the reset port of the GPIO of the SOC chip 1 for system reset.

[0055] The power conversion circuit 14 is electrically connected to each power port and external connector of the SOC chip 1, and converts the input +12V DC power supply into various operating voltages required by the SOC chip, such as -12V, 5.0V, 3.3V, 2.5V, 1.8V, 1.5V, and 1.0V, and then supplies them to the SOC chip.

[0056] The SOC chip 1 should also include a minimum system for system initialization, system status monitoring, and communication and port control.

[0057] The SOC chip 1 is model Hi3559AV100; the FLASH chip 2 is model SG35M2GMB; the DDR memory 3 is model HSMD4-512M16-PBGM; the watchdog circuit 4 is model AiP74LVC1G08(SOT353) and SJ706TAHV; the Ethernet PHY circuit 5 is model SJ16T245LJFC-1 and B88E1111MB; the RS232 transceiver circuit 6 is model CSTXS0108 and SJ3232S; the audio processing circuit 7 is model SX33178MF; and the eMMC memory 8 is model KWYY32. GJDEA; the voltage detection circuit 9 is model JAD7998; the temperature monitoring circuit 10 is model HWD1668MAE; the LVDS video transceiver circuit 11 is model Hi3559AV100; the HDMI video transmission circuit 12 is model Hi3559AV100; the BT.1120 video transmission circuit 13 is model Hi3559AV100; the power conversion circuit 14 is model HCE4644AMB and HCE8025MB; the JTAG connector 15 is model LMD-107-02-GD, and the external connector 16 is model XMC-0619-10T.

[0058] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. An airborne audio and video processing board based on Hi3559AV100, comprising a SOC chip, an audio processing circuit, an LVDS video transceiver circuit, an HDMI video transmission circuit, and a BT.1120 video transmission circuit, characterized in that: The SOC chip in question is model number Hi3559AV100; The audio port of the SOC chip is connected to the audio processing circuit via an audio input / output interface, which is used to interface with the on-chip or off-chip audio codec to complete the input and output of audio data; The sensor serial input video interface of the SOC chip is configured as an LVDS video transceiver port. The LVDS video transceiver circuit is electrically connected to the MIPI Rx raw video data input port and MIPIDSI video data output port of the SOC chip to process LVDS interface video signals. Some of the output video interfaces of the SOC chip are configured as HDMI video transmission ports. The HDMI video transmission circuit is electrically connected to the HDMI video transmission port configuration of the SOC chip to transmit HDMI interface video signals. Part of the output video interface of the SOC chip is configured as a BT.1120 video transmission port. The BT.1120 video transmission circuit is electrically connected to the BT.1120 video transmission port of the SOC chip to transmit BT.1120 interface video signals.

2. The on-board audio and video processing board based on the Hi3559AV100 according to claim 1, characterized in that The audio processing circuit includes an instrumentation amplifier circuit, a first-order low-pass filter, and a first-order RC high-pass filter, used for input and output processing of analog differential audio signals.

3. The on-board audio and video processing board based on the Hi3559AV100 according to claim 1, characterized in that The audio processing circuit is model SX33178MF; the LVDS video transceiver circuit is model Hi3559AV100; the HDMI video transmission circuit is model Hi3559AV100; and the BT.1120 video transmission circuit is model Hi3559AV100.

4. The on-board audio and video processing board based on the Hi3559AV100 according to claim 1, characterized in that It also includes an Ethernet PHY circuit and an RS232 transceiver circuit; The Ethernet port of the SOC chip is connected to the gigabit network transformer via RGMII, and electrically connected to the external connector via the Ethernet PHY circuit to realize the physical layer connection of Ethernet. Some serial ports of the SOC chip are configured as UART ports, and the RS232 transceiver circuit is electrically connected to the UART port of the SOC chip to realize the transmission of RS232 data. Some high-speed serial ports of the SOC chip are configured as PCIe ports, including one set of PCIe x2 channels, to realize PCIe data stream communication; Some serial ports of the SOC chip are configured as I2C ports, and some I2C ports are used to connect to external I2C communication interfaces. Some serial ports of the SOC chip are configured as SPI ports, and some SPI ports are used to connect to external SPI communication interfaces. Some serial ports of the SOC chip are configured as USB ports to connect to external USB communication interfaces; Some GPIO ports of the SOC chip are configured as discrete signal ports to connect to external discrete signals.

5. An airborne audio and video processing board based on Hi3559AV100 according to claim 4, characterized in that... The Ethernet PHY circuits are model SJ16T245LJFC-1 and B88E1111MB; the RS232 transceiver circuits are model CSTXS0108 and SJ3232S.

6. The airborne audio and video processing board based on Hi3559AV100 according to claim 1, characterized in that... It also includes FLASH chips, DDR memory, watchdog circuit, eMMC memory, connectors, power conversion circuit, voltage detection circuit and temperature monitoring circuit; Some serial ports of the SOC chip are configured as I2C ports. The voltage detection circuit is electrically connected to some I2C ports of the SOC chip to detect the operating voltage inside the board. The temperature monitoring circuit is electrically connected to some I2C ports of the SOC chip to monitor the temperature of the board. Some serial ports of the SOC chip are configured as SPI ports, and the FLASH chip is electrically connected to the SPI port of the SOC chip in the SPI mode to reserve storage system programs; The eMMC memory is electrically connected to the eMMC port of the SOC chip to store system programs and record board self-test data and abnormal error data; The connector is electrically connected to the JTAG port and external port of the SOC chip for burning system files, online debugging, and external communication. The DDR memory consists of four chips. Two chips are electrically connected to the DDR0 port of the SOC chip using a FLY-BY topology to form a 32-bit DDR for system cache. The other two chips are electrically connected to the DDR1 port of the SOC chip using a FLY-BY topology to serve as a data cache for high-speed signals. The watchdog circuit is electrically connected to the reset port of the SOC chip's GPIO for system reset. The power conversion circuit is electrically connected to each power port and external connector of the SOC chip, and converts the input DC power into various operating voltages required by the SOC chip before supplying them to the SOC chip.

7. An airborne audio and video processing board based on Hi3559AV100 according to claim 6, characterized in that... The FLASH chip is model SG35M2GMB; the DDR memory is model HSMD4-512M16-PBGM; the watchdog circuit is model AiP74LVC1G08 and SJ706TAHV; the eMMC memory is model KWYY32GJDEA; the voltage detection circuit is model JAD7998; the temperature monitoring circuit is model HWD1668MAE; the power conversion circuit is model HCE4644AMB and HCE8025MB; the connector is a JTAG connector, model LMD-107-02-GD.

8. The airborne audio and video processing board based on Hi3559AV100 according to claim 1, characterized in that... The SOC chip also includes a minimum system for system initialization, system status monitoring, and communication and port control.

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