Digital noise cancellation circuit for over-ear headphones

Abstract

This utility model discloses a digital noise cancellation circuit for over-ear headphones, including a sound recognition and printed circuit (PDM) processor, a power module, a button circuit, an LED indicator circuit, and a speaker circuit. The power module, button circuit, LED indicator circuit, and speaker circuit are all electrically connected to the PDM processor. It also includes a front-facing microphone driver circuit, a feedback microphone driver circuit, and a call microphone driver circuit. The front-facing microphone driver circuit and the call microphone driver circuit are directly electrically connected to the PDM processor. The feedback microphone driver circuit is first connected to a buffer before being connected to the PDM processor. The added buffer chip improves the integrity of the PDM signal, thereby providing driving force for the PDM signal. This ensures that the rising / falling edge times of the transmitted signal waveform are close to the rising / falling edge times of the feedback microphone output, guaranteeing signal integrity and allowing users to enter a noise-free environment at any time when noise cancellation is activated.

Description

Technical Field

[0001] This utility model relates to the field of headphones, and in particular to a digital noise reduction circuit for headphones. Background Technology

[0002] Noise-canceling headphones use feedback microphones for sound pickup. In the PDM signal, the CLK signal is easily interfered with by other signals during transmission through the headband cable, causing waveform distortion and loss of signal integrity. This results in the receiving terminal recognizing new sounds (what is known as phase error noise in the noise-canceling headphone industry), which seriously affects the user experience. Utility Model Content

[0003] In view of this, the present invention addresses the deficiencies of the existing technology, and its main objective is to provide a digital noise reduction circuit for headphones that improves the driving force of the feedback microphone signal to enhance signal integrity, thereby overcoming the shortcomings of the existing technology.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: A digital noise reduction circuit for over-ear headphones includes a sound recognition and printed circuit processor, a power module, a button circuit, an LED indicator circuit, and a speaker circuit. The power module, button circuit, LED indicator circuit, and speaker circuit are all electrically connected to the sound recognition and printed circuit processor. The system includes a front-facing microphone driver circuit, a feedback microphone driver circuit, and a call microphone driver circuit. The front-facing microphone driver circuit and the call microphone driver circuit are directly electrically connected to the sound recognition and printing processor, while the feedback microphone driver circuit is first connected to a buffer and then connected to the sound recognition and printing processor.

[0005] As a preferred embodiment, the voice recognition and printing processor is model AB1571AM.

[0006] As a preferred embodiment, the buffer includes a power decoupling section and a buffer drive section; wherein the power decoupling section includes inductor L12 and capacitor C45, inductor L13 and capacitor C46, ​​and inductor L14 and capacitor C47 connected in parallel; the buffer drive section includes a digital buffer U2, which is a 74LV1T125, and amplifies the weak digital audio microphone signal from the sound recognition and printed circuit processor into a low-jitter waveform that can drive the feedback microphone drive circuit.

[0007] As a preferred embodiment, the front microphone driver circuit includes capacitors C5, C15, C21, C53, and C26; resistors R26, R8, R27, and R29; inductors L3 and L15; and TVS diodes E15 and E19. The inductors L3 and capacitors C5 and C53, and inductors L15, C15, and C21 on the two electronic circuits connected to the sound recognition and printed circuit processor form a filter circuit to short-circuit the 2.4 GHz Wi-Fi / BLE energy to ground, preventing self-oscillation. Resistor R26 is connected in series with the front microphone to dampen and suppress high-frequency spikes.

[0008] As a preferred embodiment, the call microphone driver circuit includes capacitors C24, C25, C22, C23, and C27; resistors R16, R31, R17, and R37; inductors L16 and L17; and TVS diodes E14 and E16. Inductors L16 and capacitors C24 and C23, and inductors L17, C25, and C27 on the two electronic circuits connected to the voice recognition and printed circuit processor form a filter circuit to short-circuit the 2.4 GHz Wi-Fi / BLE energy to ground, preventing self-oscillation. Resistor R16 is connected in series with the front microphone to dampen and suppress high-frequency spikes.

[0009] As a preferred embodiment, the feedback microphone driving circuit includes two sets of feedback microphone interfaces for the left and right ears. Each set of feedback microphone interfaces is connected to four signal lines, namely the power supply, clock, data line and ground signal line; resistors R54, R55, R58 and R59 are connected in series with the clock and data lines to dampen and suppress high-frequency spikes.

[0010] As a preferred embodiment, the power module has a charging interface circuit that can be connected to a reversible plug for charging, a charging management circuit that can provide a compatible power supply, and a rechargeable battery. The charging interface circuit, the charging management circuit, and the battery are electrically connected in sequence, and the voice recognition and printed circuit processor are electrically connected to the charging management circuit.

[0011] As a preferred embodiment, the charging interface circuit is a Type-C interface with a lithium battery charging chip U4, model WPi107; the charging management circuit includes a linear lithium battery charging chip U3, model CE3221A420ES.

[0012] As a preferred embodiment, the button circuit includes volume up, volume down, and ANC buttons, with each button line having a 1k current-limiting resistor and TVS diode surge protection added to ground.

[0013] As a preferred embodiment, the LED indicator circuit includes two LEDs, LED1, LED2, and LED3, for displaying battery level and status. It uses sound recognition and the three control ports of the printed circuit board processor and a transistor constant current source to display four statuses: charging, discharging, low battery, and pairing.

[0014] Compared with the prior art, this utility model has obvious advantages and beneficial effects. Specifically, as can be seen from the above technical solution, This innovative design incorporates a hardware circuit to enhance the driving force of the feedback microphone (PDM) in over-ear noise-canceling headphones. To improve the integrity of the PDM signal, a buffer chip is added, thereby providing driving force for the PDM signal. This ensures that the rising / falling edge time of the transmitted signal waveform is close to the rising / falling edge time of the feedback microphone output, guaranteeing signal integrity and allowing users to enter a noise-free environment at any time when noise cancellation is activated.

[0015] To more clearly illustrate the structural features and effects of this utility model, the following detailed description of this utility model is provided in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0016] Figure 1 This is a block diagram of a digital noise reduction circuit system for headphones, according to an embodiment of this utility model.

[0017] Figure 2 This is a circuit diagram of a sound recognition and printed processor according to an embodiment of the present invention.

[0018] Figure 3 This is a circuit diagram of a buffer according to an embodiment of the present invention.

[0019] Figure 4 This is a diagram of the front microphone driver circuit, the feedback microphone driver circuit, and the call microphone driver circuit according to an embodiment of this utility model.

[0020] Figure 5 This is a circuit diagram of the power supply module according to an embodiment of the present invention.

[0021] Figure 6 This is a circuit diagram of the button circuit and LED indicator circuit according to an embodiment of the present invention.

[0022] Figure 7 This is a speaker circuit diagram of an embodiment of the present invention.

[0023] Explanation of reference numerals in the attached diagram: 10. Voice recognition and printed circuit processor; 20. Power module 30. Button circuit; 40. LED indicator circuit 50. Speaker circuit; 60. Front microphone driver circuit 70. Feedback microphone driver circuit; 80. Talk microphone driver circuit 90. Buffer. Detailed Implementation

[0024] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0025] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0026] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0028] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments.

[0029] Please refer to Figures 1 to 7As shown, it illustrates the specific structure of a preferred embodiment of the present invention, which is a digital noise reduction circuit for headphones. It includes a sound recognition and printing processor 10, a power module 20, a button circuit 30, an LED indicator circuit 40, and a speaker circuit 50. The power module 20, button circuit 30, LED indicator circuit 40, and speaker circuit 50 are all electrically connected to the sound recognition and printing processor 10. It also includes a front-facing microphone driver circuit 60, a feedback microphone driver circuit 70, and a call microphone driver circuit 80. The front-facing microphone driver circuit 60 and the call microphone driver circuit 80 are directly electrically connected to the sound recognition and printing processor 10. The feedback microphone driver circuit 70 is first connected to a buffer 90 and then connected to the sound recognition and printing processor 10.

[0030] When the user triggers the button circuit 30, the power management circuit supplies power to the sound recognition and printing processor 10 and other circuits and devices. The external ambient sound is collected through the front microphone driver circuit 60, and the sound inside the headphones is collected through the feedback microphone driver circuit 70. The sound collected by the feedback microphone and the sound collected by the front microphone are canceled out by the sound recognition and printing processor 10, so that the headphones can be used to enjoy quiet noise reduction.

[0031] like Figure 2 As shown, the sound recognition and printed processor 10 is model AB1571AM. The AB1571AM chip integrates a Cortex-M4F + M0 dual-core processor, Bluetooth 5.3 LE Audio, 96 kHz audio codec, Buck power management, and a programmable DSP into a single chip: the Sensor Hub runs a keyword model at 10 µA, recognizes the keyword, wakes up the main core, and sends high-fidelity audio to the headphones via LE Audio. At the same time, it uses a 128-tap FIR for real-time ANC, realizing a headphone main control solution that combines "ultra-low power consumption, high sound quality, and intelligent wake-up". The hardware architecture of the AB1571AM chip includes a computing core, Bluetooth RF, audio subsystem, and power management. The audio subsystem features a 96 kHz / 24-bit stereo DAC with an SNR of 110 dB, two 16-bit Σ-Δ ADCs for ANC feedforward / feedback microphones, and also includes a built-in 5-band equalizer, 3D audio effects, and wind noise suppression module.

[0032] like Figure 3As shown, the buffer 90 includes a power decoupling section and a buffer drive section. The power decoupling section includes inductors L12 and C45, L13 and C46, ​​and L14 and C47 connected in parallel. The buffer drive section includes a digital buffer U2, model 74LV1T125, which amplifies the weak digital audio microphone signal from the sound recognition and printed circuit processor 10 into a low-jitter waveform that can drive the feedback microphone drive circuit 70. In headphones, the 74LV1T125 chip is essentially a "1.8 V → 3.3 V single-channel high-speed clock / data line buffer 90": it tolerates 1.8 V logic input, outputs 8 mA push-pull, and is tri-state controllable, solving both level conversion and providing low-power isolation. Among them, resistor R35 is a 0Ω / 33Ω series resistor placed at the output terminal, which serves as both EMI damping and convenient for debugging; capacitor C35 is 100 nF and is attached to the VCC pin less than 1mm away, ensuring that 2.4 GHz noise will not couple to the clock; the 5 V-VCC input will not damage the chip even if a 5 V transient is generated by USB hot-plugging.

[0033] like Figure 4 As shown, the front microphone driver circuit 60 includes capacitors C5, C15, C21, C53, and C26, resistors R26, R8, R27, and R29, inductors L3 and L15, and TVS diodes E15 and E19. The inductors L3 and capacitors C5 and C53, and the inductors L15 and C15 and C21 on the two electronic circuits connected to the sound recognition and printed processor 10 form a filter circuit to short-circuit the 2.4GHz Wi-Fi / BLE energy to ground to avoid self-oscillation. Resistor R26 is connected in series with the front microphone to dampen and suppress high-frequency spikes.

[0034] like Figure 4 As shown, the call microphone driving circuit 80 includes capacitors C24, C25, C22, C23, C27, resistors R16, R31, R17, R37, inductors L16, L17, and TVS diodes E14, E16. The inductors L16 and capacitors C24 and C23, and inductors L17, C25, and C27 on the two electronic circuits connected to the voice recognition and printed circuit processor 10 form a filter circuit to short-circuit the 2.4 GHz Wi-Fi / BLE energy to ground, preventing self-oscillation. Resistor R16 is connected in series with the front microphone to dampen and suppress high-frequency spikes.

[0035] like Figure 4As shown, the feedback microphone driving circuit 70 includes two sets of feedback microphone interfaces for the left and right ears. Each set of feedback microphone interfaces is connected to four signal lines, namely the power supply, clock, data line and ground signal line; resistors R54, R55, R58 and R59 are connected in series with the clock and data lines to dampen and suppress high frequency spikes.

[0036] like Figure 1 and Figure 5 As shown, the power module 20 has a charging interface circuit that can be connected to a reversible plug for charging, a charging management circuit that can provide a compatible power supply, and a rechargeable battery. The charging interface circuit, the charging management circuit, and the battery are connected in sequence. The voice recognition and printed processor 10 are connected to the charging management circuit.

[0037] like Figure 5 As shown, the charging interface circuit is a Type-C interface with a lithium battery charging chip U4, model WPi107; the charging management circuit includes a linear lithium battery charging chip U3, model CE3221A420ES.

[0038] like Figure 5 As shown, the button circuit 30 includes volume up, volume down and ANC buttons, and each button line is equipped with a 1k current limiting resistor and TVS diode surge protection to ground.

[0039] like Figure 5 As shown, the LED indicator circuit 40 includes two LEDs, LED1, LED2, and LED3, for displaying power and status. It completes the display of four statuses—charging, discharging, low power, and pairing—through sound recognition, the three control ports of the printed circuit processor, and the transistor constant current source.

[0040] Its working principle is as follows: Figures 2 to 3 As shown, the MIC_BIAS0 pin of the main control chip U1 of the sound recognition and printed processor 10 is connected to the front microphone driver circuit 60. The front microphone has two microphones, left and right. One end is connected to the AU_VIN0_LFF_P pin of the main control chip U1 of the sound recognition and printed processor 10 via the electronic circuitry of AU_VIN0_LFF_P and LFF_P. The other end is connected to the AU_VIN0_LFF_N pin of the main control chip U1 of the sound recognition and printed processor 10 via AU_VIN0_LFF_N and LFF_N. Thus, the front microphones collect ambient sound and send it to the main control chip U1 of the sound recognition and printed processor 10 via the two electronic circuits.

[0041] Similarly, the MIC_BIAS1 pin of the voice recognition and printed processor 10 main control chip U1 is connected to the call microphone driver circuit 80, and the two feedback microphones in the left and right ears also collect the sound in the earphone and send it to the voice recognition and printed processor 10 main control chip U1 through two electronic circuits.

[0042] The added feedback microphone is used for feedback (FB) noise reduction. The main control chip U1 of the sound recognition and printed circuit processor 10 provides a second DMIC0_DAT, DDMIC0_CLK_IN, and VIO18, which are connected in series with the buffer 90 chip U2. The outputs are connected in parallel to the two feedback microphones respectively; the DATA signals are independently returned to the main control chip U1 of the sound recognition and printed circuit processor 10. The two buffer 90s are located on the same earcup FPC with symmetrical routing to ensure consistent timing. When the headphone system uses 3.3V I / O, the buffer 90 chip U2 can be selected as AIP74LV1T125-SOT353. Its input is compatible with 1.8V / 3.3V, and its output drives 32mA, meeting the needs of longer distance (1.5m) headphone usage scenarios.

[0043] Actual measurements show that, under conditions of a 1 m 28AWG flexible cable, a 48 kHz sampling rate, and a 3.072 MHz CLK, after adding the buffer 90 of this invention: the CLK rise time decreased from 9.8 ns to 2.1 ns; the jitter (RMS) decreased from 162 ps to 31 ps; the phase error noise decreased by 12 dB (A-weighted), and the perceived background noise disappeared. Overall power consumption increased by <0.3 mW, without affecting headphone battery life; the hardware BOM cost increased by <0.05 USD, making it suitable for mass production.

[0044] This invention effectively solves the signal integrity problem caused by long-distance flexible transmission of headphones by inserting a high-speed buffer 90 in series in the path between the feedback microphone driver circuit 70 and the sound recognition and printed processor 10, and by comprehensively optimizing the wiring, matching and ESD. It also significantly suppresses phase error noise and has the advantages of low cost, easy mass production, good compatibility and low power consumption.

[0045] The above description is merely a preferred embodiment of the present utility model and does not constitute any limitation on the technical scope of the present utility model. Therefore, any minor modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present utility model shall still fall within the scope of the technical solution of the present utility model.

Claims

1. A digital noise reduction circuit for headphones, comprising a sound recognition and printed circuit processor (10), a power module (20), a button circuit (30), an LED indicator circuit (40), and a speaker circuit (50), wherein the power module (20), the button circuit (30), the LED indicator circuit (40), and the speaker circuit (50) are all electrically connected to the sound recognition and printed circuit processor (10), characterized in that: Also includes The front microphone driver circuit (60), the feedback microphone driver circuit (70), and the call microphone driver circuit (80) are directly electrically connected to the sound recognition and printing processor (10). The feedback microphone driver circuit (70) is first connected to the buffer (90) and then connected to the sound recognition and printing processor (10).

2. The digital noise reduction circuit for headphones according to claim 1, characterized in that: The voice recognition and printing processor (10) is model AB1571AM.

3. The digital noise reduction circuit for headphones according to claim 1, characterized in that: The buffer (90) includes a power decoupling section and a buffer drive section; wherein the power decoupling section includes inductor L12 and capacitor C45, inductor L13 and capacitor C46, ​​inductor L14 and capacitor C47 connected in parallel; the buffer drive section includes a digital buffer U2, the model of which is 74LV1T125, which amplifies the weak digital audio microphone signal from the sound recognition and printed processor (10) into a low-jitter waveform that can drive the feedback microphone drive circuit (70).

4. The digital noise reduction circuit for headphones according to claim 1, characterized in that: The front microphone driver circuit (60) includes capacitors C5, C15, C21, C53, C26, resistors R26, R8, R27, R29, inductors L3, L15, and TVS diodes E15, E19. The inductors L3 and capacitors C5 and C53, L15 and C15, and C21 on the two electronic circuits connected to the sound recognition and printed processor (10) form a filter circuit to short-circuit the 2.4 GHz Wi-Fi / BLE energy to ground to avoid self-oscillation. The resistor R26 is connected in series with the front microphone to dampen and suppress high-frequency spikes.

5. The digital noise reduction circuit for headphones according to claim 1, characterized in that: The microphone driver circuit (80) includes capacitors C24, C25, C22, C23, C27, resistors R16, R31, R17, R37, inductors L16, L17, and TVS diodes E14, E16. The inductors L16 and capacitors C24 and C23, and the inductors L17, C25, and C27 on the two electronic circuits connected to the voice recognition and printed processor (10) form a filter circuit to short-circuit the 2.4 GHz Wi-Fi / BLE energy to ground to avoid self-oscillation. The resistor R16 is connected in series with the front microphone to dampen and suppress high-frequency spikes.

6. The digital noise reduction circuit for headphones according to claim 1, characterized in that: The feedback microphone driver circuit (70) includes two sets of feedback microphone interfaces for the left and right ears. Each set of feedback microphone interfaces is connected to four signal lines, namely power supply, clock, data line and ground signal line; resistors R54\R55\R58\R59 are connected in series with the clock and data lines to dampen and suppress high frequency spikes.

7. The digital noise reduction circuit for headphones according to claim 1, characterized in that: The power module (20) has a charging interface circuit that can be connected to a reversible plug for charging, a charging management circuit that can provide a power supply, and a rechargeable battery. The charging interface circuit, the charging management circuit, and the battery are connected in sequence. The voice recognition and printed processor (10) are connected to the charging management circuit.

8. The digital noise reduction circuit for headphones according to claim 7, characterized in that: The charging interface circuit is a Type-C interface and has a lithium battery charging chip U4, model WPi107; the charging management circuit includes a linear lithium battery charging chip U3, model CE3221A420ES.

9. The digital noise reduction circuit for headphones according to claim 1, characterized in that: The button circuit (30) includes volume up, volume down and ANC buttons, and each button line is equipped with a 1k current limiting resistor and TVS diode surge protection to ground.

10. The digital noise reduction circuit for headphones according to claim 1, characterized in that: The LED indicator circuit (40) includes two LEDs, LED1, LED2, and LED3, for displaying power and status. It completes the display of four statuses: charging, discharging, low power, and pairing through sound recognition, the three-way control interface of the printed processor (10), and the transistor constant current source.

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