circuit board

Abstract

This application provides a circuit board including a substrate, a chip array, and a power supply module. The chip array includes multiple power-collecting units connected in sequence, each power-collecting unit including at least one chip. The power supply module includes a first conductive element for connecting to the positive terminal of a power supply and a second conductive element for connecting to the negative terminal of a power supply. The first conductive element is electrically connected to the first power-collecting unit of the chip array, and the second conductive element is electrically connected to the last power-collecting unit of the chip array. The first and second conductive elements are arranged adjacent to each other at a first end in the extension direction of the substrate. The centralized design of the first and second conductive elements allows the electrical connection boards to be synchronously adapted to the centralized arrangement. The housing no longer needs to reserve multiple avoidance areas due to the dispersed arrangement of the electrical connection boards, simplifying the housing processing technology, reducing the damage to the structural integrity of the housing caused by avoidance openings, and helping to improve the overall strength of the housing.

Description

Technical Field

[0001] This application relates to the field of computing device technology, and more particularly to a circuit board. Background Technology

[0002] The positive and negative conductive components on circuit boards are often arranged in a distributed manner. The electrical connection boards that connect these components to the power supply, needing to accommodate this distributed layout, often occupy a significant amount of space, compressing the mounting area for other components in the computing device. This necessitates the creation of additional mounting space for these components, limiting the overall integration of the computing device. Furthermore, the distributed arrangement of the positive and negative conductive components and their corresponding electrical connection boards requires the provision of clearance channels around each connection board, thus restricting the placement of openings in the computing device. Utility Model Content

[0003] This application provides a circuit board to solve or alleviate one or more technical problems in the prior art.

[0004] As one aspect of the embodiments of this application, this application provides a circuit board, including:

[0005] substrate;

[0006] A chip array is disposed on the substrate, the chip array comprising a plurality of power-collecting units connected in sequence, each power-collecting unit comprising at least one chip;

[0007] A power supply module, the power supply module including a first conductive element for connecting to the positive terminal of a power supply and a second conductive element for connecting to the negative terminal of a power supply, the first conductive element being electrically connected to the first power-taking unit of the chip array, and the second conductive element being electrically connected to the last power-taking unit of the chip array;

[0008] The first conductive element and the second conductive element are arranged adjacent to each other and are disposed at the first end of the substrate along the extension direction.

[0009] In one embodiment, the second conductive element is further away from the first side edge of the substrate along the extension direction relative to the first conductive element;

[0010] The first power-collecting unit is disposed near the first side edge of the substrate along the extension direction, and the last power-collecting unit is disposed near the second side edge of the substrate along the extension direction.

[0011] In one embodiment, a notch is formed at the edge of the first end of the substrate along the extension direction, corresponding to the region of the first conductive element.

[0012] In one embodiment, the upper edges of the first conductive element and the second conductive element do not extend beyond the upper edge of the substrate.

[0013] In one embodiment, the power supply module further includes a first electrical connector connected between the second conductive element and the end power extraction unit.

[0014] In one embodiment, the first electrical connector extends along a first direction perpendicular to the extension direction.

[0015] In one embodiment, the first electrical connector includes at least two electrical connection groups that are connected sequentially, with adjacent electrical connection groups spaced apart to define a clearance channel for arranging wiring.

[0016] In one embodiment, the electrical connection group includes at least one conductive sheet connected in sequence, and the number of conductive sheets in each electrical connection group may be different.

[0017] In one embodiment, the power supply module further includes a boost module and a voltage regulator module, which are disposed at the first end of the substrate along the extension direction.

[0018] In one embodiment, the booster module and the voltage regulator module are arranged along a first direction perpendicular to the extension direction, with the booster module being closer to the first conductive element and the second conductive element than the voltage regulator module.

[0019] In one embodiment, a signal connector is further included, which is disposed at a first end of the substrate along the extension direction and adjacent to a second side edge of the substrate along the extension direction; the signal connector is sequentially connected to each chip of the chip array via signal lines.

[0020] In one embodiment, a processing module is further included, which is disposed at the first end in the extension direction of the substrate and configured between the signal connector and the voltage regulator module.

[0021] In one embodiment, the power supply module has multiple voltage monitoring points, and the processing module is connected to the multiple voltage monitoring points through multiple voltage monitoring lines to collect the voltage of the voltage monitoring points.

[0022] In one embodiment, a temperature sensor is provided on the substrate, and the processing module is connected to the temperature sensor through a temperature acquisition line to acquire the temperature detected by the temperature sensor.

[0023] In one embodiment, the number of temperature sensors is at least two, with at least one temperature sensor adjacent to the air inlet side of the substrate and at least one temperature sensor adjacent to the air outlet side of the substrate along the direction of airflow through the circuit board.

[0024] In one embodiment, a voltage monitoring line extends through a clearance passage to connect to a corresponding voltage monitoring point, and / or a temperature acquisition line extends through a clearance passage to connect to a temperature sensor.

[0025] In one embodiment, the number of electrical connection groups is three, and the three electrical connection groups are spaced apart to define two clearance channels.

[0026] Each clearance path is for at least one voltage monitoring line and at least one temperature acquisition line to pass through.

[0027] In one implementation, the signal line passes through a clearance channel adjacent to the signal connector and is connected to the signal of the end power supply unit.

[0028] In one embodiment, the chip array includes a first power supply group, a second power supply group, and at least one third power supply group, wherein the first power supply group, the second power supply group, and the third power supply group include a plurality of power supply units that are connected in series along the extension direction.

[0029] The first power-taking group is adjacent to the first side edge of the substrate along the extension direction, the second power-taking group is adjacent to the second side edge of the substrate along the extension direction, and at least one third power-taking group is located between the first power-taking group and the second power-taking group in a first direction.

[0030] In one implementation, the uppermost power-taking unit in the first power-taking group is the first power-taking unit, and the uppermost power-taking unit in the second power-taking group is the last power-taking unit.

[0031] The circuit board also includes multiple second electrical connections;

[0032] In any one of the first power supply group, the second power supply group, and the third power supply group, the power supply unit at the bottom is connected in series with the power supply unit at the bottom of the adjacent power supply group through the corresponding second electrical connector.

[0033] In at least one third power supply group, the uppermost power supply unit in the same power supply group is connected in series with the uppermost power supply unit in the adjacent power supply group through a corresponding second electrical connector.

[0034] In one embodiment, along the direction of airflow through the circuit board, the second power take-up group is adjacent to the air inlet side of the substrate, and the first power take-up group is adjacent to the air outlet side of the substrate.

[0035] In one embodiment, the signal line passes through the clearance channel of the adjacent signal connector, starting from the chip of the last power-taking unit of the second power-taking group adjacent to the clearance channel, and sequentially connects all the chips in the last power-taking unit in a direction away from the clearance channel, and sequentially connects the chips of the adjacent power-taking units downwards based on the principle of proximity, until it is connected to the chip of the power-taking unit at the bottom of the second power-taking group.

[0036] The signal line starts from the chip of the power-taking unit at the bottom of the second power-taking group, connects to the chip of the power-taking unit at the bottom of the adjacent third power-taking group, and connects to each chip of the third power-taking group and each chip of the first power-taking group in sequence based on the principle of proximity.

[0037] In one embodiment, each power-gathering unit includes a plurality of chips spaced apart along a first direction, the plurality of chips being electrically connected in parallel.

[0038] In one implementation, the uppermost power-taking unit in the first power-taking group is the first power-taking unit, and the uppermost power-taking unit in the second power-taking group is the last power-taking unit.

[0039] The uppermost power-taking unit in the first power-taking group is positioned higher than the uppermost power-taking unit in the second power-taking group in the extension direction.

[0040] In one implementation, the uppermost power-taking unit in the first power-taking group is the first power-taking unit, and the uppermost power-taking unit in the second power-taking group is the last power-taking unit.

[0041] The uppermost power-taking unit in the first power-taking group and the uppermost power-taking unit in the second power-taking group are positioned higher than the uppermost power-taking unit in the third power-taking group in the extension direction.

[0042] In one embodiment, the first power supply group and the second power supply group include a plurality of power supply areas spaced apart along the extension direction.

[0043] There are vacant positions between adjacent power supply areas in the same power supply group. The number of vacant positions in the first power supply group is greater than the number of vacant positions in the second power supply group. The number of vacant positions in the second power supply group is 0, or equal to or greater than 1.

[0044] In one embodiment, the number of vacant positions in the second power supply group is equal to or greater than 1, and the number of power supply units in at least one power supply area in the second power supply group is greater than the number of power supply units in at least one power supply area in the first power supply group.

[0045] In one embodiment, along a first direction, the spacing between adjacent power supply groups in the second power supply group, the third power supply group, and the first power supply group increases sequentially.

[0046] According to the circuit board of this application embodiment, the first conductive element and the second conductive element are disposed adjacent to each other at the end of the substrate along the extension direction. The centralized design of the first conductive element and the second conductive element allows the electrical connection plates to be synchronously adapted and centrally arranged. The housing no longer needs to reserve multiple clearance channels due to the dispersed arrangement of the electrical connection plates. Only one clearance structure is needed to meet the clearance requirements of the two electrical connection plates, which simplifies the housing processing technology, reduces the damage to the structural integrity of the housing by clearance openings, and helps to improve the overall strength of the housing.

[0047] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0048] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0049] Figure 1 A schematic diagram of the circuit board structure according to a first example of an embodiment of this application is shown;

[0050] Figure 2 A schematic diagram of the circuit board structure according to a second example of an embodiment of this application is shown;

[0051] Figure 3 A schematic diagram of the circuit board structure according to a third example of an embodiment of this application is shown;

[0052] Figure 4 A schematic diagram of the circuit board structure according to a fourth example of an embodiment of this application is shown;

[0053] Figure 5 A schematic diagram of the circuit board structure according to a fifth example of an embodiment of this application is shown.

[0054] Explanation of reference numerals in the attached figures:

[0055] Circuit board 81, first conductive component 811, second conductive component 812, signal connector 813, temperature sensor 814, power extraction unit 82, chip 821, first electrical connector 83, electrical connection group 831, conductive sheet 8311, clearance channel 83a, second electrical connector 832.

[0056] Voltage monitoring point 81a, voltage acquisition line 81b, temperature acquisition line 81c, signal line 81d;

[0057] Boost module 84, capacitor 841, voltage regulator module 85, processing module 86;

[0058] First power supply group 87, second power supply group 88, third power supply group 89, power supply area 871, vacancy 872;

[0059] The first direction is L1, and the third direction is L3. Detailed Implementation

[0060] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0061] In related technologies, the positive and negative conductive components of circuit boards are often arranged in a distributed manner. The electrical connection boards that connect these conductive components to the power supply, needing to adapt to this distributed layout, often occupy a significant amount of space, compressing the installation area of ​​other components in the computing device. This necessitates the creation of additional installation space for these components, limiting the integration of the computing device. Furthermore, due to the distributed arrangement of the positive and negative conductive components and their corresponding electrical connection boards, the computing device needs to reserve clearance channels around each electrical connection board, thus restricting the placement of openings within the computing device.

[0062] To address the aforementioned technical problems, the circuit board in this embodiment adopts the following improved design: the positive and negative conductive components are arranged adjacent to each other, specifically at the end of the circuit board substrate along its extension direction, near one edge of the substrate along the extension direction. Through this centralized layout, the electrical connection board connecting the positive and negative conductive components to the external power supply can be synchronously and centrally arranged, eliminating the need to reserve redundant space for a dispersed layout and reducing overall space occupancy. This design also frees up sufficient mounting area for other components such as the control board of the computing device.

[0063] Meanwhile, due to the centralized arrangement of positive and negative conductive components and their corresponding electrical connection boards, the casing of the computing device no longer needs to reserve multiple clearance channels around the dispersed components. A single clearance structure is sufficient to meet the requirements, simplifying the casing manufacturing process and reducing the damage to the structural integrity of the casing caused by clearance openings, which helps to improve the overall strength of the casing. In addition, the centralized layout also provides more flexible layout space for components in other areas of the substrate (such as chip arrays, boost modules, voltage regulator modules, signal connectors, etc.), enhancing the adaptability of the circuit board to different types of computing devices and expanding its application range.

[0064] The following detailed description is provided with reference to specific embodiments and illustrations.

[0065] Figure 1 A schematic diagram of the structure of a circuit board 81 according to a first example of an embodiment of this application is shown.

[0066] like Figure 1As shown, the circuit board 81 in this embodiment includes a substrate, a chip array, and a power supply module. The chip array is disposed on the substrate and includes a plurality of power-collecting units 82 connected in sequence. Each power-collecting unit 82 includes at least one chip 821. The power supply module includes a first conductive element 811 for connecting to the positive terminal of a power supply and a second conductive element 812 for connecting to the negative terminal of a power supply. The first conductive element 811 is electrically connected to the first power-collecting unit 82 of the chip array, and the second conductive element 812 is electrically connected to the last power-collecting unit 82 of the chip array. The first conductive element 811 and the second conductive element 812 are disposed adjacent to each other at a first end in the extension direction of the substrate. The extension direction can be a third direction L3.

[0067] The first conductive element 811 is used to connect to the positive terminal of the power supply, serving as the positive conductive element of the circuit board 81, and the second conductive element 812 is used to connect to the negative terminal of the power supply, serving as the negative conductive element. The first conductive element 811 and the second conductive element 812 can be electrically connected to the two electrical connectors (positive electrical connector and negative electrical connector) of the power supply respectively through an electrical connection plate.

[0068] The computing module of a computing device is generally housed within the device's casing, while the power supply module is located outside the casing. To enable the power supply connection between the power supply module and the circuit board 81 of the computing module, a clearance area is typically required on the casing for the electrical connection board. In this embodiment, the first conductive element 811 and the second conductive element 812 are adjacent to each other at the end of the circuit board 81 substrate along a third direction, near the first side edge of the substrate along a third direction. The centralized design of the first conductive element 811 and the second conductive element 812 allows the electrical connection boards to be synchronously adapted and centrally arranged. The casing no longer needs to reserve multiple clearance channels due to the dispersed arrangement of the electrical connection boards; a single clearance structure can meet the clearance requirements of two electrical connection boards, simplifying the casing manufacturing process and reducing the damage to the structural integrity of the casing caused by clearance openings, thus contributing to improved overall casing strength.

[0069] The centralized design of the first conductive element 811 and the second conductive element 812 eliminates the need for redundant space to be reserved for the dispersed layout of the electrical connection board in the casing of the computing device, reducing the overall space occupation and thus freeing up sufficient installation area for other components such as the control board of the computing device.

[0070] A notch is formed at the edge of the first end of the substrate along the extension direction, corresponding to the area of ​​the first conductive element 811. The first conductive element 811 is connected to the positive terminal electrical connector of the power module through an electrical connection plate. The notch design at the edge of the substrate increases the distance between the electrical connection plate and the edge of the substrate, thereby increasing the safety clearance.

[0071] In other examples, if the distance between the substrate edge and the electrical connection plate already meets the preset safety distance requirements (no need to increase the gap to avoid electrical safety risks), then the substrate edge may not need to have the aforementioned notch, and a complete edge structure can be used.

[0072] The second conductive element 812 is connected to the negative terminal electrical connector of the power module through another electrical connection plate. Since the second conductive element 812 is the negative terminal, which is equivalent to the ground terminal, the edge of the first end of the substrate along the extension direction does not need to be notched in the area corresponding to the second conductive element 812.

[0073] The upper edges of the first conductive element 811 and the second conductive element 812 do not extend beyond the upper edge of the substrate. This design can effectively reduce the overall height of the computing device, making it compatible with standardized shelves.

[0074] The power-collecting units 82 of the chip array can be connected in series. Specifically, the first power-collecting unit 82 of the chip array is electrically connected to the positive terminal of the power supply via a first conductive element 811, and the last power-collecting unit 82 of the chip array is electrically connected to the negative terminal of the power supply via a second conductive element 812. The power-collecting units 82 between the first and last power-collecting units 82 are connected in series between the first and last power-collecting units 82, thus achieving series electrical connection between the power-collecting units 82 of the chip array. Multiple chips 821 of the same power-collecting unit 82 can be connected in parallel.

[0075] The second conductive element 812 is located further away from the first side edge of the substrate along the third direction relative to the first conductive element 811. The first power-taking unit 82 is disposed adjacent to the first side edge of the substrate along the third direction, and the last power-taking unit 82 is disposed adjacent to the second side edge of the substrate along the third direction. That is, the first power-taking unit 82 is disposed adjacent to the first conductive element 811, and the last power-taking unit 82 is located at the two sides of the substrate substantially along the third direction.

[0076] like Figure 1 As shown, the first end of the substrate along a third direction is the upper end of the substrate. The first conductive element 811 is located at the rightmost end of the upper end of the substrate, and the second conductive element 812 is adjacent to the left side of the first conductive element 811. The power-taking unit 82 at the rightmost and topmost end of the substrate is the first power-taking unit 82, and the power-taking unit 82 at the leftmost and topmost end of the substrate is the last power-taking unit 82.

[0077] The second conductive element 812 can be electrically connected to the end power-taking unit 82 via the first electrical connector 83. The electrical connection between the first conductive element 811 and the first power-taking unit 82, as well as the electrical connections between the first power-taking unit 82 and each power-taking unit 82 between the end power-taking unit 82, can be connected via another electrical connector. The electrical connector can be a metal busbar, such as a conductive copper busbar, to reduce voltage drop.

[0078] The first electrical connector 83 can be designed to extend along a first direction L1 perpendicular to the third direction. By optimizing the arrangement of the second conductive member 812 and the end power extraction unit 82, it can be ensured that the first electrical connector 83 between the two can be arranged along the first direction L1, avoiding the increase in substrate space occupied by the inclined arrangement and compressing the occupied area of ​​the first electrical connector 83.

[0079] To prevent the first electrical connector 83 from coming into contact with other lines on the substrate and causing a short circuit, the first electrical connector 83 can be designed as at least two sequentially connected electrical connection groups 831, with adjacent electrical connection groups 831 spaced apart to form a clearance channel 83a for arranging other lines.

[0080] Specifically, two adjacent electrical connection groups 831 are connected by electrical connection lines embedded inside the substrate. Simultaneously, the substrate surface is covered with an insulating layer in the area corresponding to the electrical connection lines, and the surface of the avoidance channel 83a has an insulating protective structure. This design ensures that lines arranged along the avoidance channel 83a will not directly contact the electrical connection groups 831, nor will they contact the electrical connection lines embedded in the substrate, structurally eliminating the risk of short circuits.

[0081] By using the avoidance channel 83a to centrally arrange other lines, not only can the lines on the substrate be organized and the layout chaos caused by the messy lines be reduced, but the centralized arrangement of the components of the circuit board 81 can also be further promoted, forming a synergy with the centralized layout of the aforementioned positive and negative conductive components, and optimizing the space utilization of the substrate.

[0082] The lines arranged along the avoidance channel 83a can be voltage monitoring lines and / or temperature acquisition lines 81c and / or signal lines 81d.

[0083] For example, a signal connector 813, a boost module 84, a voltage regulator module 85, a processing module 86, and a temperature sensor 814 may be disposed on the substrate.

[0084] The signal connector 813 is connected to each chip 821 of the chip array in sequence through the signal line 81d. The signal connector 813 can be electrically connected to the external control board through the cable to realize the transmission of data between the control board and each chip 821.

[0085] Understandably, in order to communicate with external devices at different voltage levels, data transmission between the signal connector 813 and the chip 821 requires independent power. The chip 821 itself requires a lower voltage to operate, while the power supply voltage for data transmission between the signal connector 813 and the chip 821 is higher. The power supply unit 82 exists as a chipset, with each chip 821 connected in parallel. To ensure the stability of data transmission between each chip 821 in each chipset level, the substrate is typically equipped with an auxiliary power supply module corresponding to each chipset level. The auxiliary power supply module should ideally draw power from the corresponding chipset level, but since the output voltage of this chipset level cannot meet the power supply requirements for data transmission, the auxiliary power supply module needs to draw power sequentially across multiple chipsets along the data transmission direction. For the last few chipsets in the data transmission path where power cannot be drawn across levels, a booster module 84 can be added to increase the power supply voltage to meet the power supply requirements for data transmission.

[0086] To ensure a consistently stable voltage input to the chipset, a voltage regulator module 85 can be connected to the voltage output of the boost module 84. The voltage output from the boost module 84 is first regulated by the voltage regulator module 85 before being delivered to the corresponding chipset, effectively avoiding the impact of voltage fluctuations on the stability of data transmission and improving the reliability of the data transmission process.

[0087] The power supply module may have multiple voltage monitoring points 81a, and the processing module 86 may be connected to multiple voltage monitoring points 81a through multiple voltage monitoring lines to collect the voltage of the voltage monitoring points 81a.

[0088] In related technologies, if the circuit board 81 malfunctions, it requires manual inspection of each component and circuit repeatedly, which not only consumes a lot of manpower and time but also has extremely low fault location efficiency, affecting equipment maintenance progress. In this embodiment, the circuit board 81 is equipped with a processing module 86 and voltage monitoring points 81a. The voltage monitoring points 81a are distributed at key locations on the circuit board 81, and the processing module 86 can monitor the voltage status of multiple areas of the circuit board 81 in real time through these monitoring points. When the circuit board 81 malfunctions, the processing module 86 can quickly capture abnormal voltage signals, thereby accurately locating the fault point without requiring manual inspection, significantly improving fault identification efficiency and shortening the equipment maintenance cycle.

[0089] Figure 1 A voltage monitoring point 81a is shown, which is located on the conductive part of the lowest power collection unit 82 that connects the two power collection groups on the right. Figure 2Two voltage monitoring points 81a are shown. One voltage monitoring point 81a is located on the conductive part of the leftmost power supply group that connects the bottommost power supply unit 82 and the adjacent uppermost power supply unit 82. The other voltage monitoring point 81a is located on the conductive part of the bottommost power supply unit 82 and the adjacent uppermost power supply unit 82 of another power supply group adjacent to the rightmost power supply group. Figure 3 , Figure 4 Multiple voltage monitoring points 81a are shown separately, and will not be described in detail here. Figures 1 to 4 The voltage monitoring point 81a shown is merely an example and does not constitute a limitation on this application. The voltage monitoring point 81a may also be provided on the conductive part connecting the first conductive member 811 and the first power taking unit 82, or on the conductive part connecting the first electrical connector 83 and the last power taking unit 82, etc., and is not limited to these.

[0090] The processing module 86 can be connected to the temperature sensor 814 via the temperature acquisition line 81c to acquire the temperature detected by the temperature sensor 814. The number of temperature sensors 814 is at least two, with at least one temperature sensor 814 adjacent to the air inlet side of the substrate and at least one temperature sensor 814 adjacent to the air outlet side of the substrate along the direction of airflow through the circuit board 81.

[0091] In this embodiment, the first side of the substrate along the third direction is the air outlet side, and the second side of the substrate along the third direction is the air inlet side.

[0092] like Figure 1 As shown, two temperature sensors 814 can be disposed on the substrate. One temperature sensor 814 is disposed in the gap area between the two columns of chips on the left, located upstream in the airflow direction, and the other temperature sensor 814 is disposed in the gap area between the two columns of chips on the right, located downstream in the airflow direction. By distributing temperature sensors 814 upstream and downstream of the airflow, real-time temperature data of different areas of the circuit board 81 can be captured simultaneously, providing a more comprehensive reflection of the overall temperature distribution of the circuit board 81. Based on this complete temperature distribution information, the operating parameters of the fan (such as speed) can be adjusted in a targeted manner. This avoids affecting the performance of the circuit board 81 due to local overheating and also prevents energy waste caused by excessive fan operation, further improving the stability and energy efficiency of the circuit board 81.

[0093] For example, the signal connector 813, processing module 86, voltage regulator module 85, and booster module 84 can be disposed at the first end of the substrate along a third direction (i.e., the upper end of the substrate along a third direction), located at the same end of the substrate along a third direction as the first conductive element 811 and the second conductive element 812, forming an integrated layout of functional modules. Specifically, the signal connector 813, processing module 86, voltage regulator module 85, and booster module 84 can be arranged sequentially along the first direction L1 at the upper end of the substrate to optimize the space utilization of the substrate.

[0094] The signal connector 813 is located near the second side edge of the substrate along the third direction (extension direction), and the first conductive element 811 and the second conductive element 812 are located near the first side edge of the substrate along the extension direction. The signal connector 813 can be connected to the signal connection structure of the control board via a signal cable, and the first conductive element 811 and the second conductive element 812 can be connected to the two electrical connection sockets of the power supply via two electrical connection plates. The top of the computing device housing may have a clearance area for avoiding the signal cable and a clearance area for avoiding the two electrical connection plates. By setting the signal connector 813 and the two conductive elements 811 and 812 respectively on the two side edges of the substrate along the extension direction, the two clearance areas opened on the top of the housing can be located near the two ends of the top plate of the housing along the first direction, thereby preserving the solid structure of the middle area of ​​the top plate of the housing and enhancing the support strength and support balance of the top of the housing.

[0095] The signal connector 813 is located on the second side edge of the substrate along a third direction, upstream of the airflow direction. When the signal connector 813 transmits data through the signal line 81d, it can establish a connection from the upstream chip 821. Since the upstream chip 821 is located upstream of the airflow, its temperature is relatively lower, its internal resistance is higher, and its voltage drop is higher. This design ensures that the auxiliary power supply module's cross-stage power draw can meet the power requirements for data transmission between the signal connector 813 and the chip 821.

[0096] The voltage regulator module 85 can be a low-dropout regulator (LDO), which has a lower input-output voltage difference, meaning it can still operate stably when the input voltage is close to the output voltage.

[0097] The boost module 84 is closer to the first conductive element 811 and the second conductive element 812 than the voltage regulator module 85. The capacitor 841 of the boost module 84 is closer to the power input and output to achieve better filtering and energy storage performance.

[0098] The boost module 84 may include a BOOST boost circuit, a voltage control chip, an input voltage switching element, an output voltage switching element, an inductor, a capacitor 841, etc. The voltage control chip is used to control the on / off state of the input voltage switching element and the output voltage switching element according to a preset voltage range. The voltage control chip can monitor the output voltage of the boost module 84 in real time to determine whether the actual output voltage is within the preset voltage range. If the output voltage does not fall within the preset voltage range, the voltage control chip will adjust the on / off time of the input and output voltage switching elements to stabilize the output voltage and bring it within the preset voltage range, thus meeting the power requirements of the chip 821.

[0099] The input voltage switching element and the output voltage switching element can be metal-oxide-semiconductor field-effect transistors, that is, the input voltage switching element is a high-side MOS (Metal-Oxide-Semiconductor) field-effect transistor and the output voltage switching element is a low-side MOS field-effect transistor, so as to reduce the on-resistance and improve the efficiency of the boost module 84.

[0100] The processing module 86 is located between the signal connector 813 and the voltage regulator module 85. The processing module 86 may include a processor and an analog-to-digital converter. The analog-to-digital converter is connected to the voltage monitoring point 81a and is used to acquire the voltage of the voltage monitoring point 81a. The processor is connected to the analog-to-digital converter and is used to acquire the voltage of the voltage monitoring point 81a.

[0101] The processor can be an MCU (Microcontroller Unit), i.e., a single-chip microcomputer. The processor can be an embedded controller, a system-on-a-chip (SoC), etc. The processor can communicate with an external controller via the 813 signal connector to achieve data transmission.

[0102] The processor can be connected to multiple voltage monitoring points 81a via multiple analog-to-digital converters to monitor the voltage at multiple locations on the circuit board 81, thereby improving fault identification efficiency.

[0103] Electrical connection group 831 may include at least one conductive sheet 8311 connected in sequence, and the number of conductive sheets 8311 in each electrical connection group 831 may be different. Specifically, there may be three electrical connection groups 831, and the three electrical connection groups 831 are spaced apart to define two clearance channels 83a. That is, when designing the circuit board 81 package corresponding to the three electrical connection groups 831, they are not designed as a continuous conductive area, but are divided into three independent pads. Each electrical connection group 831 corresponds to a dedicated pad. The three pads are completely physically separated on the circuit board 81 and are electrically connected through conductive lines inside the circuit board 81.

[0104] like Figure 1 As shown, the number and size of the conductive pieces 8311 in the three electrical connection groups 831 can be different. The rightmost electrical connection group 831 includes four conductive pieces 8311 of different sizes, the middle electrical connection group 831 includes two conductive pieces 8311 of approximately the same size, and the leftmost electrical connection group 831 includes two conductive pieces 8311 of different sizes. The number of electrical connection groups 831 and the number and size of the conductive pieces 8311 in each electrical connection group 831 can be appropriately adjusted according to the area of ​​the substrate between the second conductive member 812 and the end power extraction unit 82. This application embodiment does not specifically limit this.

[0105] To achieve a neat and orderly circuit layout and avoid interference with other components, the clearance channel 83a on the substrate can be designed as a dedicated space for the circuits to pass through. Each clearance channel 83a can accommodate at least one voltage monitoring line and one temperature acquisition line 81c. In an example where two temperature sensors 814 and multiple voltage monitoring points 81a are provided on the substrate, two clearance channels 83a can be set accordingly. The arrangement of the temperature acquisition line 81c (connected to the temperature sensor 814) and the voltage monitoring line (connected to the voltage monitoring point 81a) follows the principle of proximity. One clearance channel 83a allows one temperature acquisition line 81c connected to a nearby temperature sensor 814 (such as the line connected to the upstream temperature sensor 814 of the airflow) and multiple voltage monitoring lines connected to multiple nearby voltage monitoring points 81a to pass through. The other clearance channel 83a allows another temperature acquisition line 81c connected to another nearby temperature sensor 814 (such as the line connected to the downstream temperature sensor 814 of the airflow) and multiple other voltage monitoring lines connected to multiple nearby voltage monitoring points 81a to pass through. This arrangement ensures short-path connections for the circuits, reduces signal loss, and further improves the regularity of the circuit layout on the substrate through classification and grouping, reducing the difficulty of circuit identification during maintenance.

[0106] Figure 2 This diagram shows a schematic representation of the structure of a circuit board 81 according to a second example of an embodiment of this application. Figure 3 This diagram shows a schematic representation of the structure of a circuit board 81 according to a third example of an embodiment of this application. Figure 4 This diagram shows a schematic representation of the structure of a circuit board 81 according to a fourth example of an embodiment of this application. Figure 5 A schematic diagram of the structure of a circuit board 81 according to a fifth example of an embodiment of this application is shown.

[0107] For example, the chip array may include a first power supply group 87, a second power supply group 88, and at least one third power supply group 89. The first power supply group 87, the second power supply group 88, and the third power supply group 89 include a plurality of power supply units 82 that are connected in series along a third direction L3. The first power supply group 87 may be adjacent to a first side edge of the substrate along the third direction, the second power supply group 88 may be adjacent to a second side edge of the substrate along the third direction, and at least one third power supply group 89 is located between the first power supply group 87 and the second power supply group 88 in a first direction L1.

[0108] Along the direction of airflow through the circuit board 81, the second power take-up group 88 is adjacent to the air inlet side of the substrate, and the first power take-up group 87 is adjacent to the air outlet side of the substrate. That is, the first power take-up group 87, at least one third power take-up group 89, and the second power take-up group 88 are distributed along the airflow direction.

[0109] The uppermost power-taking unit 82 in the first power-taking group 87 is the first power-taking unit 82, and the uppermost power-taking unit 82 in the second power-taking group 88 is the last power-taking unit 82. In any one of the first power-taking groups 87, the second power-taking group 88, and the third power-taking group 89, the lowermost power-taking unit 82 is connected in series with the lowermost power-taking unit 82 of the adjacent power-taking group through a corresponding second electrical connector 832. In at least one third power-taking group 89, the uppermost power-taking unit 82 in the same power-taking group is connected in series with the uppermost power-taking unit 82 of the adjacent power-taking group through a corresponding second electrical connector 832.

[0110] Specifically, such as Figures 1 to 5 As shown, the chip array may include a first power supply group 87, two third power supply groups 89 and a second power supply group 88 arranged sequentially at intervals along the first direction L1. The heat dissipation airflow flows from the left side to the right side of the substrate. The second power supply group 88 is located adjacent to the left side of the substrate, the first power supply group 87 is located adjacent to the right side of the substrate, and the two third power supply groups 89 are located in the area between the second power supply group 88 and the first power supply group 87.

[0111] The uppermost power-taking unit 82 of the first power-taking group 87 is electrically connected to the first conductive element 811 as the first power-taking unit 82. The uppermost power-taking unit 82 of the second power-taking group 88 is electrically connected to the second conductive element 812 as the last power-taking unit 82. The first power-taking unit 82 in the first power-taking group 87 is connected in series with each other in the group from top to bottom. The lowermost power-taking unit 82 in the first power-taking group 87 is electrically connected to the lowermost power-taking unit 82 of the adjacent third power-taking group 89. The lowermost power-taking unit 82 in the third power-taking group 89 is connected in series with each other in the group from top to bottom. The uppermost power-taking unit 82 in the third power-taking group 89 is connected to the uppermost power-taking unit 82 in another adjacent third power-taking group 89. The uppermost power-taking unit 82 in the other third power-taking group 89 is connected in series with each power-taking unit 82 in this group downwards. The lowermost power-taking unit 82 in the other third power-taking group 89 is electrically connected to the lowermost power-taking unit 82 in the second power-taking group 88. The lowermost power-taking unit 82 in the second power-taking group 88 is connected in series with each power-taking unit 82 in this group upwards until it reaches the uppermost end power-taking unit 82, thus completing the series connection of each power-taking unit 82 in the chip array.

[0112] The uppermost power-taking unit 82 in the first power-taking group 87 is positioned higher than the uppermost power-taking unit 82 in the second power-taking group 88 in a third-dimensional direction. The space between the two can be used to arrange the first electrical connector 83, thereby making full use of the substrate space and achieving a reasonable layout of each power-taking group and the first electrical connector 83.

[0113] The uppermost power-taking unit 82 in the first power-taking group 87 and the uppermost power-taking unit 82 in the second power-taking group 88 are positioned higher than the uppermost power-taking unit 82 in the third power-taking group 89 in the third direction, thus reserving a certain arrangement space above the third power-taking group 89; the second electrical connector 832 can extend along the first direction L1 and be located in the reserved space, exactly below the first electrical connector 83, which can make full use of the substrate space and realize a reasonable layout of each power-taking group, the first electrical connector 83 and the second electrical connector 832.

[0114] Each power-gathering unit 82 may include a plurality of chips 821 arranged at intervals along a first direction L1, the plurality of chips 821 being electrically connected in parallel. For example... Figures 1 to 4 As shown, each power-gathering unit 82 includes two chips 821 arranged side by side. In other examples, the power-gathering unit 82 may also include three, four, or any other number of chips 821 arranged side by side; this is merely an example and does not constitute a limitation of this application.

[0115] The signal connector 813 is located on the upper end of the substrate near the second side (on the left side of the upper end of the substrate). The signal line 81d can pass through the clearance channel 83a adjacent to the signal connector 813 and connect to the end power-taking unit 82. Figure 1 As shown, signal line 81d travels along the leftmost bypass channel 83a to connect with the rightmost chip 821 in the leftmost end power supply unit 82.

[0116] The stability of data transmission between signal connector 813 and chip 821 depends on whether the cross-stage power supply can support the voltage required for data transmission. The voltage obtained from the cross-stage power supply depends on the voltage division of chip 821, which is related to the internal resistance of chip 821. The internal resistance of chip 821 is affected by temperature. Within a certain temperature range, the internal resistance of chip 821 fluctuates with temperature changes, deviating from a fixed value and showing a trend of decreasing with increasing temperature and increasing with decreasing temperature. Therefore, temperature changes in chip 821 affect the operational state of data transmission between signal connector 813 and chip 821.

[0117] In this embodiment, the second power supply group 88 is located on the air intake side of the substrate. The chip 821 in the second power supply group 88 has a relatively lower temperature, higher internal resistance, and higher voltage division. The signal line 81d passes through the clearance channel 83a adjacent to the signal connector 813, and establishes a connection starting from the chip 821 adjacent to the clearance channel 83a at the end of the power supply unit 82 of the second power supply group 88. This ensures that the cross-stage power supply of the auxiliary power supply module can meet the power requirements for data transmission between the signal connector 813 and the chip 821.

[0118] Signal line 81d passes through the clearance channel 83a of the adjacent signal connector 813, starting from the chip 821 of the last power-taking unit 82 of the second power-taking group 88 near the clearance channel 83a, and sequentially connects all the chips 821 of the last power-taking unit 82 in a direction away from the clearance channel 83a. Based on the principle of proximity, it sequentially connects to the chips 821 of the adjacent power-taking unit 82, until it connects to the chip 821 of the lowest power-taking unit 82 of the second power-taking group 88. Signal line 81d starts from the chip 821 of the lowest power-taking unit 82 of the second power-taking group 88, connects to the chip 821 of the lowest power-taking unit 82 of the adjacent third power-taking group 89, and sequentially connects to each chip 821 of the third power-taking group 89 and each chip 821 of the first power-taking group 87 based on the principle of proximity.

[0119] by Figure 1 As shown in the example, signal line 81d travels along the leftmost bypass channel 83a and establishes a connection starting from the rightmost chip 821 of the uppermost end power supply unit 82 in the second power supply group 88. It then connects to the other chips 821 of the end power supply unit 82 in sequence to the left. The leftmost chip 821 of the end power supply unit 82 connects downwards to the leftmost chip 821 of the adjacent power supply unit 82. The leftmost chip 821 connects to the other chips 821 of the power supply unit 82 in sequence to the right. The rightmost chip 821 of the power supply unit 82 connects downwards to the rightmost chip 821 of the adjacent power supply unit 82. The rightmost chip 821 connects to the other chips 821 of the power supply unit 82 in sequence to the left. Following the principle of proximity, it continues until it connects to the rightmost chip 821 of the lowermost power supply unit 82 in the second power supply group 88.

[0120] The number of power-taking units 82 in the second power-taking group 88 can be even, so that the signal line 81d can be established starting from the rightmost chip 821 of the uppermost power-taking unit 82 (the last power-taking unit 82) in the second power-taking group 88, and continue to be connected from the rightmost chip 821 of the lowermost power-taking unit 82 in the second power-taking group 88 to the leftmost chip 821 of the lowermost power-taking unit 82 in the adjacent third power-taking group 89, thereby simplifying and shortening the path of the signal line 81d and improving the stability of signal transmission.

[0121] The signal line 81d continues to connect from the rightmost chip 821 of the bottommost power supply unit 82 in the second power supply group 88 to the leftmost chip 821 of the bottommost power supply unit 82 in the third power supply group 89, and then connects to the other chips 821 of the power supply unit 82 in sequence to the right. Then, the rightmost chip 821 of the power supply unit 82 connects upwards to the rightmost chip 821 of the adjacent power supply unit 82, and the rightmost chip 821 connects to the other chips 821 of the power supply unit 82 in sequence to the left. Following the principle of proximity, the connection of each chip 821 in each of the third power supply groups 89 is completed, and then the connection of the chips 821 in the first power supply group 87 continues.

[0122] The number of power-taking units 82 in the third power-taking group 89 can be odd, so that the signal line 81d enters from the leftmost chip 821 of the bottommost power-taking unit 82 of the third power-taking group 89 and exits from the rightmost chip 821 of the topmost power-taking unit 82 of the same power-taking group to continue to connect with the leftmost chip 821 of the topmost power-taking unit 82 of the adjacent third power-taking group 89, thereby simplifying and shortening the path of the signal line 81d.

[0123] The number of third power supply groups 89 can be even to ensure that the signal line 81d enters from the leftmost chip 821 of the bottommost power supply unit 82 of the third power supply group 89 adjacent to the second power supply group 88, and finally outputs from the rightmost chip 821 of the bottommost power supply unit 82 of the third power supply group 89 adjacent to the first power supply group 87 to continue to connect with the leftmost chip 821 of the bottommost power supply unit 82 of the first power supply group 87, thus simplifying and shortening the path of the signal line 81d.

[0124] The signal line 81d continues to connect from the rightmost chip 821 of the bottommost power-taking unit 82 of the third power-taking group 89 adjacent to the first power-taking group 87 to the leftmost chip 821 of the bottommost power-taking unit 82 of the first power-taking group 87. Then, it connects to the other chips 821 of the power-taking unit 82 in sequence to the right. Then, it connects upward from the rightmost chip 821 of the power-taking unit 82 to the rightmost chip 821 of the adjacent power-taking unit 82. From the rightmost chip 821, it connects to the other chips 821 of the power-taking unit 82 in sequence to the left. Following the principle of proximity, it continues until it connects to the leftmost chip 821 of the topmost power-taking unit 82 (the first power-taking unit 82) in the first power-taking group 87. At this point, the signal line 81d completes the connection between the chips 821.

[0125] The number of power-taking units 82 in the first power-taking group 87 can be even, so as to ensure that the signal line 81d enters from the leftmost chip 821 of the bottommost power-taking unit 82 of the first power-taking group 87 and outputs from the leftmost chip 821 of the topmost power-taking unit 82 of the first power-taking group 87, thus simplifying and shortening the path of the signal line 81d.

[0126] For example, the first power supply group 87 and the second power supply group 88 include a plurality of power supply areas 871 arranged at intervals along a third direction. There are gaps 872 between adjacent power supply areas 871 in the same power supply group. The number of gaps 872 in the first power supply group 87 is greater than the number of gaps 872 in the second power supply group 88. The number of gaps 872 in the second power supply group 88 can be 0, or equal to or greater than 1.

[0127] The empty space 872 here can be understood as an area where chip 821 is not placed, but a conductive sheet 8311 can be installed to reduce voltage drop. For example... Figure 1 As shown, the second power supply group 88 on the far left has four empty slots 872. These empty slots 872 are not soldered with chips 821, but are fitted with copper sheets to reduce voltage drop.

[0128] Since no chip 821 is placed in the vacant space 872, a wider heat dissipation channel can be formed, increasing the airflow volume and speed, reducing wind resistance, and improving the heat dissipation effect. For the second power extraction group 88 adjacent to the air intake side, since it is located at the upstream end of the airflow direction, the airflow temperature it passes through is relatively the lowest. Therefore, the second power extraction group 88 can be without the vacant space 872, allowing for the placement of more chips 821. While meeting the heat dissipation needs of its own chips 821, the number of chips 821 in the downstream power extraction group can be appropriately reduced, lowering the chip density of the downstream power extraction group, optimizing the downstream heat dissipation effect, and ultimately improving the temperature uniformity of the entire circuit board 81 (e.g., ...). Figure 4 As shown, the second power supply group 88 on the far left can be without a vacancy 872.

[0129] In examples where the number of vacant positions 872 in the second power supply group 88 is equal to or greater than 1, the number of power supply units 82 in at least one power supply area 871 in the second power supply group 88 can be greater than the number of power supply units 82 in at least one power supply area 871 in the first power supply group 87. That is, the second power supply group 88, which is located upstream and has a lower heat dissipation temperature, has more power supply units 82; while the first power supply group 87, which is located downstream and has a higher heat dissipation temperature, has fewer power supply units 82, thereby balancing the overall heat dissipation temperature of the circuit board 81.

[0130] The third power-taking group 89 can be without any empty spaces 872. That is, the third power-taking group 89, located in the roughly middle area of ​​the heat dissipation airflow direction, has a relatively large number of power-taking units 82. Although the airflow temperature in the middle area is higher than that of the upstream second power-taking group 88, it is lower than that of the downstream first power-taking group 87. By increasing the number of power-taking units 82 without empty spaces 872, the heat dissipation conditions in the middle area can be fully utilized to improve computing power, while avoiding local heat accumulation caused by excessively dense power-taking units 82. This balances the heat dissipation load of the middle area and the upstream and downstream areas, ensuring the synergy between computing power and heat dissipation of the circuit board 81.

[0131] like Figures 1 to 4As shown, the chip array includes four power supply groups, namely the second power supply group 88 on the left, the first power supply group 87 on the right, and two third power supply groups 89 located between the second power supply group 88 and the first power supply group 87. Each power supply group includes multiple power supply units 82 arranged in the third direction. Each power supply unit 82 includes two parallel electrically connected chips 821 arranged in the left-right direction.

[0132] Rows are defined in the left and right directions, and columns are defined in the third direction. Figure 1 In the example shown, the chip array comprises 78 rows and 2 columns, totaling 156 chips (821). Figure 2 In the example shown, the chip array comprises 80 rows and 2 columns, totaling 160 chips (821). Figure 3 In the example shown, the chip array consists of 82 rows and 2 columns, totaling 164 chips (821). Figure 4 In the example shown, the chip array comprises 84 rows and 2 columns, totaling 168 chips (821). Figure 5 As shown, each power supply group includes multiple power supply units 82 arranged in three directions. Each power supply unit 82 includes four parallel-connected chips 821 arranged in the left and right directions. The chip array includes 80 rows and 4 columns, totaling 320 chips 821.

[0133] Figures 1 to 5 The examples shown are only partial examples of the embodiments of this application. The number of chips 821, the number of chip rows and columns, and the number and distribution of power-taking units 82 in each power-taking group can be adaptively adjusted according to computing power requirements, heat dissipation requirements, and the arrangement requirements of each component on the circuit board 81. This application does not make specific limitations in this regard.

[0134] Along the first direction L1 (i.e., the direction of heat dissipation airflow), the spacing between adjacent power taps of the second power tap 88, the third power tap 89, and the first power tap 87 can be increased sequentially. As the airflow flows along the heat dissipation direction, the temperature will gradually increase. The sequentially increasing spacing between adjacent power taps can reserve more heat dissipation space for downstream areas with higher temperatures, reduce airflow obstruction in downstream areas, improve heat dissipation efficiency in high-temperature areas, and prevent downstream power taps from overheating due to heat accumulation. Ultimately, this achieves a gentler overall temperature gradient on the circuit board 81, reduces temperature differences between areas, and ensures stable operation of each chip 821.

[0135] The first conductive element 811 and the second conductive element 812 are disposed adjacent to each other, near the first side edge of the substrate along the extending direction. For example... Figures 1 to 4 As shown, for each power-drawing unit of the chip array, which is a circuit board composed of two chips connected in parallel, the first conductive element 811 and the second conductive element 812 can be located adjacent to the first side edge of the substrate along the extending direction. Figure 5As shown, for each power-drawing unit of the chip array, which is a circuit board composed of four or more chips connected in parallel, the first conductive element 811 and the second conductive element 812 are closer to the first side edge of the substrate along the extension direction relative to the second side edge of the substrate along the extension direction, so as to leave room for other components on the circuit board, such as signal connectors, boost modules, voltage regulator modules, etc.

[0136] Other configurations of the circuit board 81 in the above embodiments can be adopted from various technical solutions now and in the future known to those skilled in the art, and will not be described in detail here.

[0137] In the description of this specification, it should be understood that the terms "length", "upper", "lower", "front", "rear", "left", "right", "vertical", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0138] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0139] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" can refer to electrical connection or communication; they can be direct connection or indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0140] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0141] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0142] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit board, characterized in that, include: substrate; A chip array is disposed on the substrate, the chip array comprising a plurality of power-collecting units connected in sequence, each power-collecting unit comprising at least one chip; A power supply module, the power supply module including a first conductive element for connecting to the positive terminal of a power supply and a second conductive element for connecting to the negative terminal of a power supply, the first conductive element being electrically connected to the first power-taking unit of the chip array, and the second conductive element being electrically connected to the last power-taking unit of the chip array; The first conductive element and the second conductive element are arranged adjacent to each other and are disposed at the first end of the substrate along the extension direction.

2. The circuit board according to claim 1, characterized in that, The second conductive element is further away from the first side edge of the substrate along the extension direction relative to the first conductive element; The first power-taking unit is disposed adjacent to the first side edge of the substrate along the extension direction, and the last power-taking unit is disposed adjacent to the second side edge of the substrate along the extension direction.

3. The circuit board according to claim 1, characterized in that, The edge of the first end of the substrate along the extension direction has a notch in the region corresponding to the first conductive element.

4. The circuit board according to claim 1, characterized in that, The upper edges of the first conductive element and the second conductive element do not extend beyond the upper edge of the substrate.

5. The circuit board according to claim 2, characterized in that, The power supply module further includes a first electrical connector, which is connected between the second conductive element and the end power extraction unit.

6. The circuit board according to claim 5, characterized in that, The first electrical connector extends along a first direction perpendicular to the extension direction.

7. The circuit board according to claim 6, characterized in that, The first electrical connector includes at least two electrical connection groups that are connected in sequence, with adjacent electrical connection groups spaced apart to define a clearance channel for arranging the wiring.

8. The circuit board according to claim 7, characterized in that, The electrical connection group includes at least one conductive sheet connected in sequence, and the number of conductive sheets in each electrical connection group is different.

9. The circuit board according to claim 1, characterized in that, The power supply module further includes a boost module and a voltage regulator module, which are disposed at the first end of the substrate along the extension direction.

10. The circuit board according to claim 9, characterized in that, The boosting module and the stabilizing module are arranged along a first direction perpendicular to the extension direction, with the boosting module being closer to the first conductive element and the second conductive element than the stabilizing module.

11. The circuit board according to claim 1, characterized in that, It also includes a signal connector, which is disposed at a first end of the substrate along the extension direction, adjacent to a second side edge of the substrate along the extension direction; the signal connector is sequentially connected to each chip of the chip array via signal lines.

12. The circuit board according to claim 11, characterized in that, It also includes a processing module, which is disposed at the first end of the substrate in the extension direction and is configured between the signal connector and the voltage regulator module.

13. The circuit board according to claim 12, characterized in that, The power supply module has multiple voltage monitoring points, and the processing module is connected to the multiple voltage monitoring points through multiple voltage monitoring lines to collect the voltage of the voltage monitoring points.

14. The circuit board according to claim 12, characterized in that, A temperature sensor is provided on the substrate, and the processing module is connected to the temperature sensor through a temperature acquisition line to acquire the temperature detected by the temperature sensor.

15. The circuit board according to claim 14, characterized in that, The number of temperature sensors is at least two, and along the direction of airflow through the circuit board, at least one of the temperature sensors is adjacent to the air inlet side of the substrate, and at least one of the temperature sensors is adjacent to the air outlet side of the substrate.

16. The circuit board according to claim 7, characterized in that, A voltage monitoring line extends through the clearance channel to connect with the corresponding voltage monitoring point, and / or a temperature acquisition line extends through the clearance channel to connect with a temperature sensor.

17. The circuit board according to claim 7, characterized in that, The number of electrical connection groups is three, and the three electrical connection groups are spaced apart to define two avoidance channels; Each of the aforementioned avoidance channels is traversed by at least one voltage monitoring line and at least one temperature acquisition line.

18. The circuit board according to claim 7, characterized in that, The signal line passes through a clearance channel adjacent to the signal connector and is connected to the signal of the end power supply unit.

19. The circuit board according to claim 1, characterized in that, The chip array includes a first power supply group, a second power supply group, and at least one third power supply group. The first power supply group, the second power supply group, and the third power supply group include multiple power supply units that are connected in series along the extension direction. The first power-taking group is adjacent to a first side edge of the substrate along the extension direction, the second power-taking group is adjacent to a second side edge of the substrate along the extension direction, and the at least one third power-taking group is located between the first power-taking group and the second power-taking group in a first direction.

20. The circuit board according to claim 19, characterized in that, The uppermost power-taking unit in the first power-taking group is the first power-taking unit, and the uppermost power-taking unit in the second power-taking group is the last power-taking unit; The circuit board also includes a plurality of second electrical connectors; In any one of the first power supply group, the second power supply group, and the third power supply group, the power supply unit at the bottom is connected in series with the power supply unit at the bottom of the adjacent power supply group through the corresponding second electrical connector. In the at least one third power supply group, the uppermost power supply unit in the same power supply group is connected in series with the uppermost power supply unit in the adjacent power supply group through the corresponding second electrical connector.

21. The circuit board according to claim 20, characterized in that, Along the direction of airflow through the circuit board, the second power take-up group is adjacent to the air inlet side of the substrate, and the first power take-up group is adjacent to the air outlet side of the substrate.

22. The circuit board according to claim 21, characterized in that, The signal line passes through the clearance channel of the adjacent signal connector, starting from the chip of the last power-taking unit of the second power-taking group near the clearance channel, and sequentially connects all the chips in the last power-taking unit in a direction away from the clearance channel. Based on the principle of proximity, it sequentially connects the chips of the adjacent power-taking units downwards until it connects to the chip of the lowest power-taking unit of the second power-taking group. The signal line starts from the chip of the power-taking unit at the bottom of the second power-taking group, connects to the chip of the power-taking unit at the bottom of the adjacent third power-taking group, and connects to each chip of the third power-taking group and each chip of the first power-taking group in sequence based on the principle of proximity.

23. The circuit board according to claim 19, characterized in that, Each of the power-collecting units includes a plurality of chips arranged at intervals along a first direction, the plurality of chips being electrically connected in parallel.

24. The circuit board according to claim 19, characterized in that, The uppermost power-taking unit in the first power-taking group is the first power-taking unit, and the uppermost power-taking unit in the second power-taking group is the last power-taking unit; The position of the uppermost power-taking unit in the first power-taking group is higher than the height of the uppermost power-taking unit in the second power-taking group in the extension direction.

25. The circuit board according to claim 19, characterized in that, The uppermost power-taking unit in the first power-taking group is the first power-taking unit, and the uppermost power-taking unit in the second power-taking group is the last power-taking unit; The uppermost power-taking unit in the first power-taking group and the uppermost power-taking unit in the second power-taking group are positioned higher than the uppermost power-taking unit in the third power-taking group in the extension direction.

26. The circuit board according to claim 19, characterized in that, The first power-taking group and the second power-taking group include multiple power-taking areas arranged at intervals along the extending direction; There are vacant positions between adjacent power supply areas in the same power supply group. The number of vacant positions in the first power supply group is greater than the number of vacant positions in the second power supply group. The number of vacant positions in the second power supply group is 0, or equal to or greater than 1.

27. The circuit board according to claim 26, characterized in that, The number of vacant positions in the second power supply group is equal to or greater than 1, and the number of power supply units in at least one power supply area in the second power supply group is greater than the number of power supply units in at least one power supply area in the first power supply group.

28. The circuit board according to claim 26, characterized in that, Along the first direction, the spacing between adjacent power supply groups in the second power supply group, the third power supply group, and the first power supply group increases sequentially.

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