Semiconductor structure

Abstract

This invention provides a semiconductor device including a capacitor structure. The capacitor structure (e.g., a trench capacitor structure) is formed in the interconnect layer of the semiconductor device. Instead of etching the dielectric layer of the interconnect layer to form the capacitor structure trench (e.g., a deep trench), a wide main trench (e.g., having a relatively low aspect ratio) is formed in the dielectric layer of the interconnect layer. The main trench is filled with dielectric plugs, which are patterned and used to form multiple pillars of the bottom electrode structure of the capacitor structure. The pillars of the bottom electrode structure define multiple secondary trenches (e.g., having a relatively high aspect ratio) in the main trench, and then the insulating layer of the capacitor structure is lined within the secondary trenches and filled with multiple pillars of the top electrode structure of the capacitor structure. This invention can increase the capacitance of the capacitor structure.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure. Background Technology

[0002] Semiconductor devices may include one or more capacitor structures in an interconnect layer above the device layer (e.g., a back end of line (BEOL) region or a back-end region). The capacitor structures may perform and / or support one or more functions in the semiconductor device, such as memory (e.g., dynamic random access memory (DRAM)), charge decoupling, analog-to-digital (A / D) converters, and / or other functions. In some cases, capacitor structures may be included in the pixel sensor circuitry of an image sensor device to provide overflow photocurrent storage, thereby enabling increased full-well capacity of the pixel sensor circuitry. Utility Model Content

[0003] This utility model provides a semiconductor structure, including: a bottom electrode structure including a first plurality of pillars extending vertically from a first base layer of the bottom electrode structure; an insulating layer located on the sidewalls of the first plurality of pillars and on the first base layer; a top electrode structure including a second plurality of pillars extending vertically from a second base layer of the top electrode structure; and an interconnect structure having a trench region, wherein the first base layer extends along a horizontal plane from one end of the trench region to the opposite end of the trench region and overlaps with the second plurality of pillars.

[0004] This utility model provides a semiconductor structure, including: a bottom electrode structure including a plurality of electrode walls extending vertically from a first base layer of the bottom electrode structure, wherein a first segment of the first base layer has a first thickness, and a second segment of the first base layer has a second thickness, the second thickness being greater than the first thickness; an insulating layer located on the sidewalls of the plurality of electrode walls and on the first base layer; and a top electrode structure including a plurality of electrode plugs extending vertically from a second base layer of the top electrode structure. Attached Figure Description

[0005] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the sizes of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 This is a schematic diagram of an exemplary implementation of the semiconductor device described in this article.

[0007] Figure 2A and Figure 2B This is a schematic diagram of an exemplary implementation of the capacitor structure described in this article.

[0008] Figures 3A-3F This is a schematic diagram illustrating an exemplary implementation of the semiconductor device described herein.

[0009] Figures 4A-4L This is a schematic diagram illustrating an exemplary implementation of the capacitor structure described in this article.

[0010] Figure 5 This is a flowchart of an exemplary process related to forming the capacitor structure in the semiconductor device described in this article. Detailed Implementation

[0011] The following utility model description provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the utility model description. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the utility model description. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of components during use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0013] Capacitor structures can include metal-insulator-metal (MIM) structures, where an insulating layer is sandwiched between two conductive electrode layers. The capacitance of a capacitor structure (e.g., the amount of charge it can store) depends directly on the geometry of the conductive electrode layers. The larger the surface area of ​​the conductive electrode layers, the larger the capacitance. Therefore, increasing the size of the metal electrode layers increases the capacitance of the capacitor structure.

[0014] Increasing the lateral dimensions of capacitor structures directly conflicts with semiconductor design principles in the semiconductor industry, which aim to reduce the size of semiconductor devices to achieve lower power consumption, higher operational performance and efficiency, and / or enable semiconductor devices for increasingly smaller form factor applications. Therefore, in some cases, the size of capacitor structures can be increased vertically within semiconductor devices, allowing the capacitor structure to extend through multiple layers. Deep trench capacitors (DTCs) are a type of capacitor structure formed in deep trenches within a semiconductor device, with their electrode and insulating layers extending along and conforming to the contour of the trench. This allows for an increase in the area of ​​the conductive electrode layers (thus increasing capacitance) while minimizing the increase in the lateral dimensions of the capacitor structure.

[0015] However, forming deep trenches for DTCs through etching can be challenging because achieving a high aspect ratio (e.g., a high ratio of trench depth to width) can be difficult due to lateral etching. Furthermore, the deeper the trench, the higher the likelihood of sidewall collapse. These challenges can lead to DTC failures and reduced yields in semiconductor devices.

[0016] In some embodiments described herein, the capacitor structure (e.g., a trench capacitor structure or a DTC structure) is formed in the interconnect layer of the semiconductor device. Instead of forming the trenches of the capacitor structure (e.g., deep trenches) by etching the dielectric layer of the interconnect layer, a wide main trench (e.g., with a relatively low aspect ratio) is formed in the dielectric layer of the interconnect layer. The main trench is filled with dielectric plugs, which are patterned and used to form multiple pillars (or “fingers”) of the bottom electrode structure of the capacitor structure. The pillars of the bottom electrode structure define multiple secondary trenches in the main trench, and then the multiple pillars (or “fingers”) of the top electrode structure of the capacitor structure are padded and filled with the insulating layer of the capacitor structure.

[0017] Therefore, secondary trenches formed of metal (e.g., the material corresponding to the pillars of the bottom electrode structure) are less prone to collapse compared to secondary trenches formed of the dielectric material of the interconnect layer. This reduces the likelihood of capacitor structure failure and increases the yield of capacitor structures formed in semiconductor devices.

[0018] Furthermore, using the pillars of the bottom electrode structure to define the secondary trenches forming the insulating layer and the pillars of the top electrode structure increases the utilization of the volume within the main trench within the metal-insulator-metal (MIM) stack of the capacitor structure (e.g., compared to using the dielectric material of the dielectric layer of the interconnect layer to define the secondary trenches, which would take away area from the MIM stack of the capacitor structure). This increases the capacitance of the capacitor structure.

[0019] Furthermore, the primary trench may be lined with pads (e.g., barrier pads, adhesive pads) that may also serve as etch stop pads during the patterning of the dielectric plug. This reduces the likelihood of lateral etching into the dielectric layer of the interconnect layer (e.g., compared to using the dielectric layer of the interconnect layer to define the secondary trench), thereby enabling the secondary trench to achieve a high aspect ratio.

[0020] In this manner, a capacitor structure (e.g., a trench capacitor structure or a DTC structure) is formed in the interconnect layer of a semiconductor device. Instead of forming the trenches of the capacitor structure (e.g., deep trenches) by etching the dielectric layer of the interconnect layer, a wide main trench (e.g., with a relatively low aspect ratio) is formed in the dielectric layer of the interconnect layer. The main trench is filled with dielectric plugs, which are patterned and used to form multiple pillars of the bottom electrode structure of the capacitor structure. The pillars of the bottom electrode structure define multiple secondary trenches in the main trench, and then the insulating layer of the capacitor structure is used as a pad to fill the multiple pillars of the top electrode structure of the capacitor structure.

[0021] Figure 1 This is an icon representing an exemplary implementation 100 of the semiconductor device 102 described herein. The semiconductor device 102 may include a system-on-chip (SoC) die, such as a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a digital signal processing (DSP) die, an application-specific integrated circuit (ASIC) die, and / or other types of SoC dies. Additionally and / or alternatively, the semiconductor device 102 may include memory dies, input / output (I / O) dies, pixel sensor dies, and / or other types of semiconductor dies. Memory dies may include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, NAND dies, high bandwidth memory (HBM) dies, and / or other types of memory dies. Generally, the semiconductor device 102 is a semiconductor device that includes one or more capacitor structures in its interconnect layers.

[0022] like Figure 1As shown, the semiconductor device 102 includes a device layer 104, an interconnect layer 106 that is vertically aligned with the device layer 104 in the semiconductor device 102 (e.g., in the z-direction), and a bonding layer 108 that is vertically aligned with the interconnect layer 106 in the semiconductor device 102 (e.g., in the z-direction).

[0023] Device layer 104 may also be referred to as the front end of line (FEOL) region of semiconductor device 102. Device layer 104 includes substrate layer 110. Substrate layer 110 may correspond to a portion of the semiconductor chip forming semiconductor device 102. Substrate layer 110 may include a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates. Substrate layer 110 may extend in semiconductor device 102 along the x-direction and / or y-direction.

[0024] Integrated circuit device 112 may be contained within and / or on substrate layer 110 in device layer 104 of semiconductor device 102. Integrated circuit device 112 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (finFET) structures, front-end gate all-around (GAA) transistor structures), pixel sensors, front-end capacitors, front-end resistors, front-end inductors, photodetectors, transceivers, transmitters, receivers, optical circuitry, and / or other types of front-end semiconductor devices. "Front-end semiconductor device" refers to a semiconductor device formed in device layer 104 of semiconductor device 102 (e.g., within and / or on substrate layer 110), and not in interconnect layer 106 of semiconductor device 102.

[0025] A dielectric layer 114 is contained above a substrate layer 110. The dielectric layer 114 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 114 includes a dielectric material that enables selective etching of portions of the substrate layer 110 and / or protects the integrated circuit device 112 from etching, and / or electrically isolates the integrated circuit device 112 within the device layer 104. The dielectric layer 114 includes silicon nitride (Si). x N y ), oxides (e.g., silicon dioxide (SiO2) x(and / or other oxide materials), and / or other types of dielectric materials. The dielectric layer 114 may extend in the semiconductor device 102 along the x-direction and / or y-direction.

[0026] Interconnect layer 106 of semiconductor device 102 is contained above substrate layer 110 and integrated circuit device 112, along the z-direction in semiconductor device 102. Integrated circuit device 112 is electrically coupled to interconnect layer 106. Interconnect layer 106 includes a plurality of dielectric layers (e.g., back-end dielectric layers) arranged in a direction approximately perpendicular to substrate layer 110 (e.g., the z-direction). The dielectric layers may include ILD layer 116 and ESL 118, which are alternately arranged in the z-direction. ILD layer 116 and ESL 118 may extend in semiconductor device 102 along the x-direction and / or y-direction.

[0027] ILD layers 116 may each comprise oxides (e.g., silicon oxide (SiO2)). x The dielectric material can be an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), a hydrosilsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, the ILD layer 116 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO2). x ), amorphous fluorinated carbon (aC) x F y ), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon-oxygen carbon (SiOC) polymers, porous hydrosilsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous polyarylene ether (PAE), and / or porous silica (SiO2) x ), and other examples.

[0028] ESL 118 may each include silicon nitride (Si) x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, ILD layers 116 and ESL 118 comprise different dielectric materials to provide etch selectivity, enabling various structures to be formed in interconnect layer 106.

[0029] Interconnect layer 106 includes multiple conductive structures. One or more conductive structures 120 are electrically coupled and / or substantially coupled to one or more integrated circuit devices 112 in device layer 104. Conductive structures 120 provide electrical wiring to enable signals and / or power to be supplied to and / or received from integrated circuit devices 112. Conductive structures 120 may include combinations of metallization structures and interconnect structures. Metallization structures may include trenches, metallization layers, conductive traces, and / or other types of metallization structures. Interconnect structures may include vias, plugs, interconnects, and / or other types of interconnect structures. Conductive structures 120 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials. In some embodiments, conductive structures 120 include one or more pad layers. The one or more pad layers may include barrier pads, adhesive pads, and / or other types of pads. Examples of materials for one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN), among others.

[0030] In some embodiments, conductive structures 120 may be arranged in multiple layers arranged vertically (e.g., in the z-direction) within interconnect layer 106. In other words, multiple conductive structure layers 120 may extend within interconnect layer 106 over device layer 104 to facilitate the routing of electrical signals and / or power between device layer 104 and interconnect layer 106. Metallization structures may be arranged in a metallization layer referred to as the M layer. For example, a metal-0 (M0) layer comprising multiple conductive structures 120 (e.g., metallization structures) may be located at the bottom of interconnect layer 106 and may be directly coupled to device layer 104 (e.g., to integrated circuit device 112 in device layer 104). A via-1 (V1) layer comprising multiple conductive structures (e.g., interconnect structures) may be included above the M0 layer. A metal-1 layer (M1) comprising multiple conductive structures 120 (e.g., metallized structures) may be located above the V1 layer in the interconnect layer 106, a via-2 layer (V2) comprising multiple conductive structures (e.g., interconnect structures) may be contained above the M1 layer, a metal-2 layer (M2) comprising multiple conductive structures 120 (e.g., metallized structures) may be located above the V2 layer, and so on.

[0031] One or more top metal layers may be included above the conductive structures 120 (e.g., M and V layers) in interconnect layer 106. For example, interconnect layer 106 may include ESL 122, ILD layer 124, ESL 126, ILD layer 128, ESL 130, ILD layer 132, ESL 134, and ILD layer 136, and may include top via 138 (e.g., extending through ESL 122 and ILD layer 124), top metal layer 140 (e.g., extending through ESL 126 and ILD layer 128), top via 142 (e.g., extending through ESL 130 and ILD layer 132), and / or top metal layer 144 (e.g., extending through ESL 134 and / or ILD layer 136), and other examples.

[0032] The top vias 138 and 142 may be substantially larger than the interconnect structure of conductive structure 120 (e.g., potentially taller in the z-direction). Similarly, the top metal layers 140 and 144 may be substantially larger than the metallization structure of conductive structure 120 (e.g., potentially taller in the z-direction). For example, the metallization structure of conductive structure 120 may have a sub-micrometer z-direction height, while the top metal layers 140 and 144 may have a z-direction height of about 1 micrometer or greater. However, other z-direction heights of the metallization structure of conductive structure 120 and the top metal layers 140 and 144 are also within the scope of this invention.

[0033] The physically large size of the top vias 138 and 142, as well as the top metal layers 140 and 144, provides lower chip resistance and enables the top of interconnect layer 106 to handle higher current signals. The physically small size of conductive structure 120 allows for a higher density of conductive structure 120 to be placed closer to the integrated circuit devices 112 in device layer 104, enabling the integrated circuit devices 112 to be arranged more closely, thereby achieving a higher integrated circuit device density in device layer 104.

[0034] In some embodiments, ESL 122, 126, 130, and 134 may comprise alternating arrangements of materials. For example, ESL 122 and 130 may comprise silicon carbide (SiC), while ESL 126 and 134 may comprise silicon nitride (SixNy, such as Si3N4). However, other combinations of materials for ESL 122, 126, 130, and 134 are also within the scope of this invention.

[0035] In some embodiments, ESL 122 may have a z-direction thickness ranging from about 300 angstroms to about 800 angstroms. However, other values ​​within this range are also within the scope of this invention. In some embodiments, ILD layer 124 may have a z-direction thickness ranging from about 4000 angstroms to about 8000 angstroms. However, other values ​​within this range are also within the scope of this invention. In some embodiments, ESL 126 may have a z-direction thickness ranging from about 300 angstroms to about 700 angstroms. However, other values ​​within this range are also within the scope of this invention. In some embodiments, ILD layer 128 may have a z-direction thickness ranging from about 6000 angstroms to about 12000 angstroms. However, other values ​​within this range are also within the scope of this invention. In some embodiments, ESL 130 may have a z-direction thickness ranging from about 300 angstroms to about 800 angstroms. However, other values ​​within this range are also within the scope of this invention. In some embodiments, ILD layer 132 may have a z-direction thickness ranging from about 4,000 angstroms to about 8,000 angstroms. However, other values ​​within this range are also within the scope of this invention. In some embodiments, ESL 134 may have a z-direction thickness ranging from about 300 angstroms to about 700 angstroms. However, other values ​​within this range are also within the scope of this invention. In some embodiments, ILD layer 136 may have a z-direction thickness ranging from about 7,000 angstroms to about 10,000 angstroms. However, other values ​​within this range are also within the scope of this invention.

[0036] Bonding layer 108 may be connected to the top metal layer 144 of interconnect layer 106. Bonding layer 108 may include additional ESL and dielectric layers, such as ESL 146, dielectric layer 148, ESL 150, and / or dielectric layer 152. Furthermore, bonding layer 108 may include bonding via 154 (e.g., extending through ESL 146 and / or dielectric layer 148) and bonding pad 156 (e.g., extending through ESL 150 and / or dielectric layer 152). Bonding via 154 may be electrically connected to and / or substantially connected to the top metal layer 144, while bonding pad 156 may be electrically connected to and / or substantially connected to the bonding via 154.

[0037] ESL 146 and 150 may each contain silicon nitride (Si). x N y The dielectric layers 148 and 152 may each comprise oxides (e.g., silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. x(and / or other oxide materials), undoped silicate glass (USG), borosilicate glass (BSG), fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrosilsesquioxane (HSQ) and / or other suitable dielectric materials.

[0038] In some embodiments, the thickness of ESL 146 in the z-direction may be in the range of about 500 angstroms to about 1000 angstroms. However, other ranges are also within the scope of this invention. In some embodiments, the thickness of dielectric layer 148 in the z-direction may be in the range of about 4000 angstroms to about 9000 angstroms. However, other ranges are also within the scope of this invention. In some embodiments, the thickness of ESL 150 in the z-direction may be in the range of about 800 angstroms to about 1600 angstroms. However, other ranges are also within the scope of this invention. In some embodiments, the thickness of dielectric layer 152 in the z-direction may be in the range of about 6000 angstroms to about 12000 angstroms. However, other ranges are also within the scope of this invention.

[0039] The bonding via 154 includes a conductive structure extending primarily in the z-direction. The bonding via 154 electrically couples the top metal layer 144 to the bonding pad 156. The bonding pad 156 includes a conductive pad for bonding the semiconductor device 102 to another semiconductor device to form a vertically stacked semiconductor package. The bonding via 154 and the bonding pad 156 include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other conductive materials.

[0040] The bonding layer 108 also includes a bonding dielectric layer 158 surrounding the bonding pad 156. The bonding dielectric layer 158 can also be used to bond the semiconductor device 102 to another semiconductor device to form a vertically stacked semiconductor package. Therefore, the combination of the bonding pad 156 and the bonding dielectric layer 158 enables the semiconductor device 102 to be bonded to another semiconductor device via metal-to-metal bonding and dielectric-to-dielectric bonding. The bonding dielectric layer 158 may include one or more dielectric materials, such as silicon nitride (Si). x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, the thickness of the bonding dielectric layer 158 in the z-direction may be in the range of about 500 angstroms to about 1000 angstroms. However, other range values ​​are also within the scope of this invention.

[0041] like Figure 1As further shown, the semiconductor device 102 may include one or more capacitor structures 160. The capacitor structure 160 may include a trench capacitor structure contained in and extending through at least a portion of the interconnect layer 106. In some embodiments, the capacitor structure 160 may be contained in and extending through at least a portion of the bonding layer 108, or alternatively, extending through a portion of the interconnect layer 106.

[0042] The capacitor structure 160 may be electrically connected to multiple conductive structures in the interconnect layer 106. For example, the bottom of the capacitor structure 160 may be electrically connected to the conductive structure 120, while the top of the capacitor structure 160 may be electrically connected to the top via 142. As another example, the capacitor structure 160 may be electrically connected to multiple conductive structures 120 and / or multiple top vias 142 on the top of the capacitor structure 160.

[0043] In some embodiments, integrated circuit device 112 is electrically coupled to capacitor structure 160 to form memory cells (e.g., dynamic random access memory (DRAM) cells or another type of capacitor-based memory cell) in semiconductor device 102. In some embodiments, capacitor structure 160 is configured to provide charge decoupling for one or more integrated circuit devices 112. In some embodiments, capacitor structure 160 is configured to store charge (e.g., photocurrent) for integrated circuit devices 112 (e.g., pixel sensors) in semiconductor device 102 to increase the full-well capacity (FWC) of the pixel sensors in semiconductor device 102. In some embodiments, capacitor structure 160 is configured to support a global shutter function of semiconductor device 102. In some embodiments, capacitor structure 160 is configured to provide charge smoothing for organic light-emitting diode (OLED) display pixels of semiconductor device 102, enabling high brightness uniformity in the OLED display pixels. In some embodiments, capacitor structure 160 is configured to perform another function in semiconductor device 102.

[0044] As mentioned above, Figure 1 Provided as an example. Other examples may be related to... Figure 1 The descriptions are different.

[0045] Figure 2A and Figure 2B This is the icon for example implementation 200 of the capacitor structure 160 described in this article. Figure 2A This describes a cross-sectional view of the capacitor structure 160 in the semiconductor device 102 along the x-direction (line AA). Figure 2B Describe the top view of the capacitor structure 160 in the xy plane.

[0046] like Figure 2AAs shown, the capacitor structure 160 includes a main trench structure 202a extending through one or more dielectric layers in the interconnect layer 106, and an upper extension region 202b above the main trench structure 202a. The main trench structure 202a corresponds to the body of the capacitor structure 160 formed in the trench, while the upper extension region 202b corresponds to a portion of the capacitor structure 160 extending along the top surface of a portion of the ILD layer 132 before being encapsulated in the ILD layer 132.

[0047] Pad 204 may be included on the sidewalls, and the bottom surface of the main trench structure 202a may define the perimeter of the main trench structure 202a. Pad 204 may extend outward from the main trench structure 202a in the upper extension region 202b. Pad 204 may include tantalum nitride (TaN) barrier pads, tantalum (Ta) pads, and / or other types of pads. Pad 204 may include adhesive pads and / or barrier pads. For example, pad 204 may include a copper (Cu) diffusion barrier to prevent, minimize, and / or otherwise reduce the likelihood of copper atoms from the underlying conductive structure 120 migrating upward to the capacitor structure 160.

[0048] Bottom electrode structure 206 may be included in main trench structure 202a on pad 204. Bottom electrode structure 206 may be electrically connected to underlying conductive structure 120. Underlying conductive structure 120 may include capacitor bottom metal (CBM) vias, CBM pads, CBM contacts, and / or other types of interconnect structures. A portion of underlying conductive structure 120 located directly beneath main trench structure 202a of capacitor structure 160 (e.g., a portion of the interconnect structure) may be referred to as trench region of underlying conductive structure 120.

[0049] The bottom electrode structure 206 includes a plurality of electrode walls 206a-206j that extend vertically (e.g., in the z-direction) from the base layer 206k of the bottom electrode structure 206. The base layer 206k extends along a horizontal plane (e.g., in the xy-plane) from one end of the main trench structure 202a (and from one end of the trench region of the underlying conductive structure 120) to the opposite end of the main trench structure 202a (and to the opposite end of the trench region of the underlying conductive structure 120), and overlaps with the electrode walls 206a-206j. The electrode walls 206a-206j may be implemented as pillars, columns, hollow cylinders, hollow rectangular prisms, hollow square prisms, and / or other types of structures that extend primarily vertically (e.g., in the z-direction) from the base layer 206k of the bottom electrode structure 206. Electrode walls 206a and 206j may correspond to the outer electrode walls of the bottom electrode structure 206, since electrode walls 206a and 206j extend along the sidewalls of the main trench structure 202a. Electrode walls 206b-206i may correspond to the inner electrode walls, since electrode walls 206b-206i are located in the main trench structure 202a, with the sidewalls of the main trench structure 202a pointing inwards.

[0050] The region between electrode walls 206a-206j defines trenches (e.g., secondary trenches) that are filled by the insulating layer 208 of capacitor structure 160 and the top electrode structure 210 of capacitor structure 160. Insulating layer 208 may include a plurality of connected approximately U-shaped cross-sectional segments 208a-208i conforming to the trenches defined by the electrode walls 206a-206j of bottom electrode structure 206. The approximately U-shaped cross-sectional segments 208a-208i may be joined together at their tops (e.g., near the upper extension region 202b) such that the approximately U-shaped cross-sectional segments 208a-208i are joined together to form a continuous layer extending through the main trench structure 202a. A portion of insulating layer 208 may also extend outward from the main trench structure 202a in the upper extension region 202b.

[0051] The top electrode structure 210 may include a plurality of electrode plugs 210a-210i (or pillars, walls, columns, and / or other types of conductive structures) extending into a trench defined by the electrode walls 206a-206j of the bottom electrode structure 206. The electrode plugs 210a-210i extend vertically (e.g., in the z-direction) from the base layer 210j of the top electrode structure 210. Thus, the electrode plugs 210a-210i extend downward from the base layer 210j of the top electrode structure 210, while the electrode walls 206a-206j of the bottom electrode structure 206 extend upward from the base layer 206k of the bottom electrode structure 206. A portion of the top electrode structure 210 may also extend outward from the main trench structure 202a in the upper extension region 202b. The main trench structure 202a (and the trench region of the underlying conductive structure 120) may overlap with the electrode plugs 210a-210i.

[0052] like Figure 2A As further shown, the electrode walls 206a-206j and electrode plugs 210a-210i can be arranged alternately in a horizontal or lateral manner. For example, in the x-direction, the electrode walls 206a-206j and electrode plugs 210a-210i can be arranged such that electrode wall 206a is horizontally or laterally adjacent to electrode plug 210a, electrode wall 206b is horizontally or laterally adjacent to electrode plug 210b, electrode wall 206c is horizontally or laterally adjacent to electrode plug 210c, and so on. Figure 2A The number of electrode walls 206a-206j and electrode plugs 210a-210i shown is one example; other numbers are also within the scope of this invention.

[0053] Thus, the capacitor structure 160 includes, in the x-direction within the main trench structure 202a, a portion comprising the bottom electrode structure 206, the insulating layer 208, and the top electrode structure 210. For example, along the x-direction, the capacitor structure 160 may include the electrode wall 206a of the bottom electrode structure 206, the approximately U-shaped cross-sectional segment 208a of the insulating layer 208 (where the electrode plug 210a of the top electrode structure 210 extends), the electrode wall 206b of the bottom electrode structure 206, the approximately U-shaped cross-sectional segment 208b of the insulating layer 208 (where the electrode plug 210b of the top electrode structure 210 extends), the electrode wall 206c of the bottom electrode structure 206, the approximately U-shaped cross-sectional segment 208c of the insulating layer 208 (where the electrode plug 210c of the top electrode structure 210 extends), and so on.

[0054] The bottom electrode structure 206 (also referred to as capacitor bottom metal (CBM)) and the top electrode structure 210 (also referred to as capacitor top metal (CTM)) may each comprise one or more conductive metals, one or more conductive metal-containing materials, one or more conductive ceramic materials, and / or other types of conductive materials. Examples include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN), among others. In some embodiments, the bottom electrode structure 206 and the top electrode structure 210 comprise the same material or the same material composition. In some embodiments, the bottom electrode structure 206 and the top electrode structure 210 comprise different materials or different material compositions.

[0055] The insulating layer 208 may include one or more electrically insulating materials. In some embodiments, the insulating layer 208 includes one or more low dielectric constant materials, such as silicon oxide (SiO2). x (e.g., SiO2). Additionally and / or alternatively, the insulating layer 208 may comprise one or more high dielectric constant materials, such as zirconium oxide (ZrO2). x For example, ZrO2), aluminum oxide (Al) x O y For example, Al2O3), silicon nitride (Si) x N y For example, Si3N4), yttrium oxide (Y) x O y For example, Y2O3), lanthanum oxide (La x O y (e.g., La2O3) and / or hafnium oxide (HfO) x (e.g., HfO2), and other examples. In some embodiments, the insulating layer 208 is a multilayer stack comprising multiple dielectric layers. For example, the insulating layer 208 may comprise a ZrO2 / Al2O3 / ZrO2 (ZAZ) layer stack.

[0056] like Figure 2A As further shown, the base layer 206k of the bottom electrode structure 206 may be electrically connected to the underlying conductive structure 120 in the interconnect layer 106. The base layer 210j of the top electrode structure 210 may be electrically connected to the top via 142 in the interconnect layer 106. The top via 142 may extend through one or more capping layers contained above the base layer 210j of the top electrode structure 210. The capping layers may electrically insulate the top electrode structure 210 and / or may serve as a hard mask layer defining the upper extension region 202b of the capacitor structure 160.

[0057] The capping layer may include capping layer 212, capping layer 214, and / or another capping layer. Capping layers 212 and 214 may include an oxide-containing dielectric material such as silicon oxide (SiO2). x For example, SiO2), nitrogen oxide dielectric materials such as silicon oxynitride (SiON), and nitride dielectric materials such as silicon nitride (SiO2). x N y (e.g., Si3N4) and / or another suitable dielectric material. In some embodiments, capping layers 212 and 214 comprise the same material and / or have the same material composition. In some embodiments, capping layers 212 and 214 comprise different materials and / or have different material compositions.

[0058] like Figure 2A As further shown, the capacitor structure 160 may include one or more sidewall spacers 216 and / or 218 on the sidewalls of the capping layers 212 and / or 214, and / or on the sidewalls of the base layer 210j of the top electrode structure 210. The combination of the capping layers 212, 214 and the sidewall spacers 216, 218 can be used as a self-aligned mask when etching layers to define the bottom electrode structure 206. The sidewall spacers 216 may include an oxide-containing dielectric material such as silicon oxide (SiO2). x (e.g., SiO2), and other examples. The sidewall spacers 218 may include nitride-containing dielectric materials such as silicon nitride (SiO2). x N y (e.g., Si3N4), and other examples.

[0059] like Figure 2B As shown, the bottom electrode structure 206 can define multiple holes, plugs, or cylindrical trenches, in which the insulating layer 208 and the top electrode structure 210 extend. These holes can be arranged in a grid, a staggered grid (e.g., rows of the grid are staggered), and / or another top-view layout.

[0060] As mentioned above, Figure 2A and Figure 2B Provided as an example. Other examples may be related to... Figure 2A and Figure 2B The descriptions are different.

[0061] Figures 3A-3F This is an illustration of an exemplary implementation 300 forming the semiconductor device 102 described herein. In some embodiments, with Figures 3A-3F One or more semiconductor process operations described herein may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, die / die transfer tools, and / or other types of semiconductor process tools.

[0062] Turning Figure 3AA substrate 110 may be provided. The substrate 110 may be provided in the form of a semiconductor chip, such as a silicon (Si) chip, an SOI chip, and / or another type of semiconductor wafer. The semiconductor device 102 may be formed on the semiconductor chip together with other semiconductor devices.

[0063] like Figure 3B As shown, integrated circuit device 112 may be formed within and / or on substrate layer 110 in device layer 104 of semiconductor device 102. One or more semiconductor process tools may be used to form one or more portions of integrated circuit device 112. For example, an ion implantation tool may be used to dope one or more regions in substrate layer 110 with one or more types of dopant to form well regions, implantation regions, and / or other types of doped regions in substrate layer 110 of integrated circuit device 112. Alternatively, a deposition tool may be used to perform various deposition operations to deposit layers and / or structures of integrated circuit device 112, and / or deposit photoresist layers for etching substrate layer 110 and / or portions of deposited layers. Alternatively, an exposure tool may be used to expose the photoresist layer to form a pattern in the photoresist layer. Alternatively, a developing tool may be used to develop the pattern in the photoresist layer. Alternatively, an etching tool may be used to etch substrate layer 110 and / or portions of deposited layers to form integrated circuit device 112. Alternatively, a planarization tool may be used to planarize portions of integrated circuit device 112. For example, an electroplating tool can be used to deposit the metal structure and / or layers of the integrated circuit device 112.

[0064] like Figure 3B As further shown, a dielectric layer 114 is deposited over and / or on the substrate 110 and over and / or on the integrated circuit device 112 using a deposition tool. The dielectric layer 114 can be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or another suitable deposition technique. In some embodiments, a planarization operation, such as chemical mechanical planarization (CMP), can be performed using a planarization tool to planarize the dielectric layer 114 after deposition.

[0065] like Figure 3CAs shown, a first portion of the interconnect layer 106 of the semiconductor device 102 is formed over the dielectric layer 114. Alternating ILD layers 116 and ESL layers 118 are deposited in the first portion of the interconnect layer 106 of the semiconductor device 102 using one or more deposition tools. Thus, the ILD layers 116 and ESL layers 118 can be aligned along the z-direction in the semiconductor device 102. Each ILD layer 116 and each ESL layer 118 can be deposited using one or more deposition tools via PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, a planarization tool can be used to planarize the ILD layers 116 and / or ESL layers 118 after deposition.

[0066] Before forming the interconnect layer 106, contacts for the integrated circuit device 112 can be formed through the dielectric layer 114. Contacts can be formed in recesses within the dielectric layer 114. In some embodiments, a pattern in a photoresist layer is used to etch the dielectric layer 114 to form recesses. In these embodiments, a photoresist layer can be formed on the dielectric layer 114 using a deposition tool. The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A portion of the photoresist layer can be developed and removed using a developing tool to expose the pattern. The dielectric layer can be etched based on the pattern using an etching tool to form recesses. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, remaining portions of the photoresist layer can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to form grooves by pattern etching the dielectric layer 114.

[0067] Contacts may be formed in recesses. In some embodiments, contacts (e.g., gate contacts) are formed on the gate structure of integrated circuit device 112. In some embodiments, contacts (e.g., source / drain contacts) are formed on the source / drain regions of integrated circuit device 112. Material for the contacts can be deposited in the recesses using deposition tools via CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The material for the contacts may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and then the material for the contacts is deposited on the seed layer. In some embodiments, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the contacts after deposition, such that the top of the contacts is substantially coplanar with the top of dielectric layer 114.

[0068] like Figure 3CAs further shown, various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools to form a conductive structure 120 in a first portion of the interconnect layer 106 of the semiconductor device 102. In some embodiments, the first portion of the interconnect layer 106 may be formed in multiple layers. For example, ILD layers 116 and ESL 118 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), grooves may be formed in and / or through ILD layers 116 and ESL 118 (e.g., using exposure tools, developing tools, and / or etching tools), and a first layer (e.g., MO layer) of the conductive structure 120 (e.g., a metallized structure) may be formed in ILD layers 116 and ESL 118 (e.g., using one or more deposition tools and / or one or more planarization tools). Another ILD layer 116 and another ESL 118 may be formed, and a second layer (e.g., a V0 layer) of conductive structure 120 (e.g., an interconnect structure) may be formed in ILD layer 116 and ESL 118. An additional layer of conductive structure 120 may be formed in interconnect layer 106 in a similar manner.

[0069] The conductive structure 120 can be deposited using one or more deposition tools via PVD, ALD, CVD, electroplating (e.g., electrochemical plating) and / or other suitable deposition techniques. In some embodiments, a planarization tool can be used to planarize the conductive structure 120 after deposition.

[0070] like Figure 3C As further shown, ESLs 122, 126, and 130 may be formed in interconnect layer 106, and ILD layers 124, 128, and 132 may be formed in interconnect layer 106. ESLs 122, 126, and 130, as well as ILD layers 124, 128, and 132, are deposited using one or more deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, ESLs 122, 126, and 130, and ILD layers 124, 128, and 132 may be planarized using planarization tools.

[0071] like Figure 3CAs further shown, various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools to form a top via 138 and a top metal layer 140 in a first portion of the interconnect layer 106 of the semiconductor device 102. In some embodiments, an ESL 122 and an ILD layer 124 may be formed, and grooves may be formed in and / or through the ESL 122 and ILD layers 124 (e.g., using exposure tools, developing tools, and / or etching tools), and the top via 138 may be formed in the grooves (e.g., using one or more deposition tools and / or one or more planarization tools). In some embodiments, ESL 126 and ILD layer 128 may be formed, and grooves may be formed in and / or through ESL 126 and ILD layer 128 (e.g., using an exposure tool, development tool and / or etching tool), and a top metal layer 140 may be formed in the grooves (e.g., using one or more deposition tools and / or one or more planarization tools).

[0072] The top via 138 and the top metal layer 140 can be deposited using one or more deposition tools via PVD, ALD, CVD, electroplating (e.g., electrochemical plating) and / or other suitable deposition techniques. In some embodiments, the top via 138 and the top metal layer 140 can be planarized using a planarization tool after deposition.

[0073] like Figure 3D As shown, a capacitor structure 160 can be formed in the interconnect layer 106 of the semiconductor device 102. The capacitor structure 160 can be formed in a through-groove of one or more dielectric layers in the interconnect layer 106. These dielectric layers may be, for example, one or more ILD layers 116, one or more ESL layers 118, ESL layer 122, ILD layer 124, ESL layer 126, ILD layer 128, ESL layer 130, and / or ILD layer 132, and other examples. The groove can extend through the dielectric layer to an underlying conductive structure 120 in the interconnect layer 106, such that the capacitor structure 160 is formed on and electrically connected to the conductive structure 120. An example implementation of forming the capacitor structure 160 is shown in... Figures 4A-4L The explanation and description are as follows.

[0074] like Figure 3EAs shown, additional material can be formed in the ILD layer 132, such that the top of the capacitor structure 160 is encapsulated within the ILD layer 132. The additional material in the ILD layer 132 can be deposited using deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, the ILD layer 132 can be planarized using a planarization tool after the additional material in the ILD layer 132 has been deposited.

[0075] like Figure 3E As further shown, ESL 134 and ILD layer 136 may be formed, and grooves may be formed in and / or through ESL 134 and ILD layer 136 (e.g., using an exposure tool, development tool and / or etching tool), and a top metal layer 144 may be formed in the grooves (e.g., using one or more deposition tools and / or one or more planarization tools).

[0076] The top via 142 and the top metal layer 144 can be deposited using one or more deposition tools via PVD, ALD, CVD, electroplating (e.g., electrochemical plating) and / or other suitable deposition techniques. In some embodiments, the top via 142 and the top metal layer 144 can be planarized using a planarization tool after deposition.

[0077] like Figure 3E As further shown, a top via 142 may be formed, allowing the top via 142 to land on and be electrically connected to the capacitor structure 160. The top via 142 electrically connects the capacitor structure 160 to the top metal layer 144 and other structures in the semiconductor device 102.

[0078] like Figure 3F As shown, ESLs 146 and 150 of bonding layers 108, dielectric layers 148 and 152 of bonding layers 108, and bonding dielectric layer 158 of bonding layers 108 can be formed above interconnect layer 106. Bond via 154 can be formed in and / or through ESL 146 and dielectric layer 148, and can be formed on top metal layer 144. Bond pad 156 can be formed in and / or through ESL 150, dielectric layer 152, and / or bonding dielectric layer 158, and can be formed on bonding via 154.

[0079] ESL 146, dielectric layer 148, ESL 150, dielectric layer 152, and / or bonding dielectric layer 158 can be deposited using one or more deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, planarization operations (e.g., CMP operations) can be performed using planarization tools to planarize ESL 146, dielectric layer 148, ESL 150, dielectric layer 152, and / or bonding dielectric layer 158.

[0080] In some embodiments, the engagement via 154 and the engagement pad 156 may be formed in a dual damascene groove. For example, a first etching operation may be performed to form a trench portion of the dual damascene groove, and a second etching operation may be performed to form a via portion of the dual damascene groove. Another example is that a first etching operation may be performed to form a via portion of the dual damascene groove, and a second etching operation may be performed to form a trench portion of the dual damascene groove. The engagement via 154 may be formed in the via portion of the dual damascene groove, and the engagement pad 156 may be formed in the trench portion of the dual damascene groove.

[0081] The bonding vias 154 and bonding pads 156 can be deposited using deposition tools via CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The bonding vias 154 and bonding pads 156 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited in a dual damascene groove, and then the bonding vias 154 and bonding pads 156 are deposited on the seed layer. In some embodiments, a liner layer (e.g., an adhesive liner, a barrier liner) is first deposited in a dual damascene groove, and then the bonding vias 154 and bonding pads 156 are deposited on the liner layer. The liner layer may include suitable liner materials, such as tantalum nitride (TaN) and / or titanium nitride (TiN). In some embodiments, after depositing the bonding vias 154 and bonding pads 156, a planarization operation (e.g., a CMP operation) is performed using a planarization tool to planarize the bonding pads 156.

[0082] As mentioned above, Figures 3A-3F This is provided as an example only. Other examples may be provided. Figures 3A-3F The descriptions are different.

[0083] Figures 4A-4L This is an illustration of an exemplary implementation 400 that forms the capacitor structure 160 described herein. In some embodiments, with Figures 4A-4L One or more operations described in the relevant description may be related to Figures 3A-3F The processes associated with forming the semiconductor device 102 shown and described are executed. In some embodiments, with Figures 4A-4LOne or more semiconductor process operations described herein may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, die / die transfer tools, and / or other types of semiconductor process tools.

[0084] like Figure 4A As shown, the groove 402 is formed in one or more dielectric layers in the interconnect layer 106, such as one or more ILD layers 116, one or more ESL layers 118, ESL layer 122, ILD layer 124, ESL layer 126, ILD layer 128, ESL layer 130 and / or ILD layer 132, etc. The groove 402 may extend through the dielectric layer to the underlying conductive structure 120 in the interconnect layer 106, so that the capacitor structure 160 is formed on the conductive structure 120 and electrically connected thereto.

[0085] The groove 402 can be formed to have a relatively low aspect ratio, i.e., the ratio of the depth (dimension D1) in the z-direction of the groove 402 to the width (e.g., the width in the x-direction and the width in the y-direction) (dimension D2) of the groove 402. For example, the aspect ratio of the groove 402 can be contained in the range of about 2:1 to about 10:1. However, other values ​​and ranges are also within the scope of this invention. In some embodiments, the groove 402 is formed to have an aspect ratio greater than about 10:1 and up to about 25:1.

[0086] In some embodiments, the z-direction depth (dimension D1) of the groove 402 may be contained in the range of about 160 nanometers to about 1650 nanometers. However, other values ​​and ranges are also within the scope of this invention. In some embodiments, the width of the groove 402 (e.g., x-direction width, y-direction width) (dimension D2) may be contained in the range of about 65 nanometers to about 80 nanometers. However, other values ​​and ranges are also within the scope of this invention.

[0087] In some embodiments, the groove 402 may have a sidewall angle (dimension D3 is the angle between the bottom surface of the groove 402 and the sidewall of the groove 402), which is contained in the range of about 95 degrees to about 110 degrees. However, other values ​​and ranges are also within the scope of this invention.

[0088] like Figure 4B As shown, a gasket 204 is formed in a groove 402. The gasket 204 may be conformally deposited on the sidewalls and bottom surface of the groove 402. A portion of the gasket 204 may also be deposited on the top surface of the ILD layer 132. In some embodiments, conformal CVD and / or ALD techniques are used to deposit the gasket 204. In some embodiments, other deposition techniques are used to deposit the gasket 204.

[0089] The pad 204 can be deposited to a thickness (dimension D4) ranging from about 100 angstroms to about 1000 angstroms. However, other values ​​and ranges are also within the scope of this invention. If the thickness of the pad 204 is less than about 100 angstroms, voids and / or other discontinuities may occur in the pad 204, and the pad 204 may not provide sufficient copper migration protection. If the thickness of the pad 204 is greater than about 1000 angstroms, the area within the recess 402 may be reduced, providing less area for the capacitor structure 160 in the recess 402. However, other values ​​and ranges besides about 100 angstroms to about 1000 angstroms are also within the scope of this invention.

[0090] like Figure 4B As further shown, a first portion of the bottom electrode structure 206 is formed on the pad 204 in the groove 402. In particular, electrode walls 206a and 206j (e.g., outer electrode walls) of the bottom electrode structure 206 may be formed on the sidewalls of the groove 402, and a base layer 206k of the bottom electrode structure 206 may be formed on the bottom of the groove 402. The first portion of the bottom electrode structure 206 may also be formed on the top surface of the ILD layer 132.

[0091] The first portion of the bottom electrode structure 206 can be conformally deposited using conformal CVD and / or ALD techniques. In some embodiments, other deposition techniques are used to deposit the first portion of the bottom electrode structure 206. The first portion of the bottom electrode structure 206 can be formed to a thickness (dimension D5) ranging from about 200 angstroms to about 500 angstroms. However, other values ​​and ranges are also within the scope of this invention.

[0092] like Figure 4C As shown, the remaining area in the groove 402 is filled with a dielectric plug 404, such as a silicon dioxide (SiO2) plug. Alternatively, the remaining area in the groove 402 may be filled with a semiconductor plug (e.g., a silicon (Si) plug, a polysilicon plug). The dielectric plug 404 can be deposited using deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. The dielectric plug 404 may be deposited in one or more deposition operations.

[0093] like Figure 4C As further shown, a planarization operation (e.g., CMP operation) can be performed using a planarization tool to planarize the dielectric plug 404 after deposition. The planarization operation can stop once the portion of the bottom electrode structure 206 extending along the top of the ILD layer 132 is reached. Thus, the top surface of the dielectric plug 404 can be substantially coplanar with the top surface of the portion of the bottom electrode structure 206 extending along the top of the ILD layer 132. Additionally and / or alternatively, an etching operation can be performed using an etching tool to remove excess material from the dielectric plug 404.

[0094] like Figure 4D As shown, dielectric plug 404 can be etched to form grooves 406a-406d within it. Grooves 406a-406d extend through dielectric plug 404 to the base layer 206k of the underlying bottom electrode structure 206. The remaining portion of dielectric plug 404 may correspond to dielectric plugs 408a-408e defining grooves 406a-406d. Figure 4D The number of grooves 406a-406d and dielectric plugs 408a-408e shown is one example; other numbers are also within the scope of this invention.

[0095] In some embodiments, a pattern in the photoresist layer is used to etch the dielectric plug 404 to form grooves 406a-406d. In these embodiments, a photoresist layer can be formed on the dielectric plug 404 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric plug 404 based on the pattern to form grooves 406a-406d. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative to pattern-based etching of the dielectric plug 404.

[0096] In some implementations, deep reactive ion etching (sometimes referred to as "BOSCH" etching) can be used to achieve a high aspect ratio (e.g., about 25:1 to about 50:1 or greater) for the recesses 406a-406d. Deep reactive ion etching is a cyclic etching technique in which multiple deposition and etching cycles are performed, using a protective pad to minimize lateral etching. For example, a deep reactive ion etching cycle may include etching the recesses 406a-406d to a first depth, forming a protective pad on the sidewalls and bottom surface of the recesses 406a-406d, etching the protective pad to remove the protective pad on the bottom surface of the recesses 406a-406d, and etching the bottom of the recesses 406a-406d to increase the depth of the recesses 406a-406d to a second depth, while the protective pad protects the sidewalls of the recesses 406a-406d from lateral etching. Additional cycles may be performed to achieve a specific depth for the recesses 406a-406d.

[0097] like Figure 4DAs shown, grooves 406a-406d may be formed having a lateral (e.g., x-direction, y-direction) width (dimension D6), a vertical (e.g., z-direction) depth (dimension D7), a sidewall angle (dimension D8), and / or a lateral spacing (dimension D9). In some embodiments, the lateral width (dimension D6) of grooves 406a-406d ranges from about 500 angstroms to about 1200 angstroms. In some embodiments, the vertical depth (dimension D7) of grooves 406a-406d ranges from about 200 nanometers to about 1650 nanometers. In some embodiments, the sidewall angle (dimension D8) of grooves 406a-406d ranges from about 90 degrees to about 92 degrees. In some embodiments, the lateral spacing between adjacent pairs of grooves 406a-406d (possibly corresponding to the lateral thickness of dielectric plugs 408a-408e) ranges from about 800 angstroms to about 1600 angstroms. However, other values ​​and ranges of these dimensions are within the scope of this invention.

[0098] like Figure 4E As shown, a second portion of the bottom electrode structure 206 is formed in the grooves 406a-406d and on top of the dielectric plugs 408a-408e. The second portion of the bottom electrode structure 206 can be conformally deposited using conformal chemical vapor deposition (CVD) and / or atomic layer deposition (ALD). In some embodiments, an alternative deposition technique is used to deposit the second portion of the bottom electrode structure 206.

[0099] The second portion of the bottom electrode structure 206 may include additional material for electrode walls 206b-206i (e.g., inner electrode walls) and base layer 206k. The first and second portions of the bottom electrode structure 206 merge or connect on top of electrode walls 206a-206j, such that adjacent pairs of electrode walls 206a-206j are connected together. For example, the tops of electrode walls 206a and 206b may be connected together (e.g., across dielectric plug 408a), the tops of electrode walls 206c and 206d may be connected together (e.g., across dielectric plug 408b), the tops of electrode walls 206e and 206f may be connected together (e.g., across dielectric plug 408c), the tops of electrode walls 206g and 206h may be connected together (e.g., across dielectric plug 408d), and / or the tops of electrode walls 206i and 206j may be connected together (e.g., across dielectric plug 408e).

[0100] Electrode walls 206b-206i may be formed on the sidewalls of recesses 406a-406d, which may correspond to the sidewalls of dielectric plugs 408a-408e. In some embodiments, the thickness (dimension D10) of the electrode walls 206b-206i is in the range of about 200 angstroms to about 300 angstroms. However, other values ​​and ranges are within the scope of this invention.

[0101] Additional material of the base layer 206k may be deposited at the bottom of the grooves 406a-406d. Dielectric plugs 408a-408e prevent the additional material of the base layer 206k from being deposited on the unexposed portions of the base layer 206k. Therefore, the base layer 206k includes a first segment with a first thickness (size D11) below the dielectric plugs 408a-408e and a second segment with a second thickness (size D12) exposed through the grooves 406a-406d, wherein the second thickness is greater than the first thickness (size D12 > size D11), the difference corresponding to size D13. In some embodiments, the difference between size D12 and size D11 (corresponding to size D13) may be contained in the range of about 200 angstroms to about 300 angstroms. However, other values ​​and ranges are within the scope of this invention.

[0102] like Figure 4F As shown, a mask layer 410 and a photoresist layer 412 can be formed. The mask layer 410 can be formed in the recesses 406a-406d and can extend across the surface of the ILD layer 132. The photoresist layer 412 can be formed on the mask layer 410.

[0103] Mask layer 410 may include an advanced patterning film (APF) layer, a bottom anti-reflective coating (BARC), and / or other suitable shielding materials. Mask layer 410 may include amorphous carbon materials, silicon dioxide materials (e.g., SiOx, such as SiO2), silicon oxynitride (SiON), polymers, and / or other suitable materials. Mask layer 410 may be deposited using deposition tools via physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, and / or other suitable deposition techniques.

[0104] The photoresist layer 412 may include organic photoresist materials, inorganic photoresist materials, and / or other suitable photoresist materials. The photoresist layer 412 may be deposited using a deposition tool via spin coating and / or other suitable deposition techniques.

[0105] like Figure 4GAs shown, the mask layer 410 can be etched to form patterned plugs 414a-414d in the grooves 406a-406d, respectively. The patterned plugs 414a-414d can be used in conjunction with dielectric plugs 408a-408e to etch portions of the bottom electrode structure 206 that connects to the top of the electrode walls 206a-206j.

[0106] In some embodiments, the mask layer 410 is consumed when a portion of the bottom electrode structure 206 on top of the connecting electrode walls 206a-206j is etched. For example, a pattern can be formed in the photoresist layer 412 (e.g., using photolithography and development techniques), and the mask layer 410 can be etched using an etching tool until a portion of the bottom electrode structure 206 on top of the connecting electrode walls 206a-206j is exposed through the mask layer 410 (this results in the formation of patterned plugs 414a-414d). The etching operation can continue until the portion of the bottom electrode structure 206 on top of the connecting electrode walls 206a-206j is removed, such that the electrode walls 206a-206j are disconnected from each other on top. This may result in further material removal from the patterned plugs 414a-414d. Therefore, the top surface of the patterned plugs 414a-414d may be lower than the top surface of the dielectric plugs 408a-408e.

[0107] like Figure 4H As shown, dielectric plugs 408a-408e and patterned plugs 414a-414d are removed from the recess 402. Removal of the dielectric plugs 408a-408e and patterned plugs 414a-414d leaves recesses 416a-416i (e.g., secondary recesses or trenches) defined by the electrode walls 206a-206j and the base layer 206k of the bottom electrode structure 206. Using the electrode walls 206a-206j and the base layer 206k of the bottom electrode structure 206 to define the recesses 416a-416i reduces the likelihood of recesses 416a-416i collapsing compared to the case where the recesses 416a-416i are formed by the dielectric layer in the interconnect layer 106. The distance or spacing between adjacent electrode walls 206a-206j (the dimension D14 may also correspond to the lateral width of the grooves 416a-416i) may range from about 500 angstroms to about 1000 angstroms. However, other values ​​and ranges are also within the scope of this invention.

[0108] In some embodiments, dielectric plugs 408a-408e and patterned plugs 414a-414d are removed in the same operation, such as by etching (e.g., wet etching, plasma-based etching, gas-based etching). In some embodiments, dielectric plugs 408a-408e and patterned plugs 414a-414d are removed in separate operations. For example, dielectric plugs 408a-408e may be removed by etching, while patterned plugs 414a-414d may be removed by plasma ashing, chemical stripping, and / or other photoresist removal techniques. In some embodiments, dielectric plugs 408a-408e are removed first, followed by patterned plugs 414a-414d. In some embodiments, patterned plugs 414a-414d are removed first, followed by dielectric plugs 408a-408e.

[0109] Etching agents such as vaporized hydrofluoric acid (VHF) or liquid hydrofluoric acid (HF) can be used to etch dielectric plugs 408a-408e and / or patterned plugs 414a-414d, while leaving the electrode walls 206a-206j and the substrate 206k of the bottom electrode structure 206 almost unetched or completely unetched. Hydrofluoric acid-based etchants can be used to selectively etch oxide-based materials (e.g., the materials of dielectric plugs 408a-408e and / or patterned plugs 414a-414d), while leaving the materials of the bottom electrode structure 206 (e.g., titanium nitride (TiN), and other examples) almost unetched or completely unetched.

[0110] like Figure 4I As shown, an insulating layer 208 can be deposited on the bottom electrode structure 206 in the groove 402. Specifically, the insulating layer 208 is deposited on the sidewalls of the grooves 416a-416i (corresponding to electrode walls 206a-206j) and the bottom surface of the grooves 416a-416i (corresponding to the base layer 206k). This results in the formation of approximately U-shaped cross-sectional segments 208a-208i of the insulating layer 208, which are joined at the top of the approximately U-shaped cross-sectional segments 208a-208i.

[0111] In some embodiments, the insulating layer 208 is conformally deposited using a deposition tool via conformal CVD and / or ALD techniques. In some embodiments, the insulating layer 208 is deposited using another deposition technique. The insulating layer 208 can be deposited to a thickness (dimension D15) ranging from about 40 angstroms to about 80 angstroms. However, other values ​​and ranges are also within the scope of this invention.

[0112] like Figure 4I As further shown, due to the different thicknesses of different segments of the base layer 206k of the bottom electrode structure 206 (e.g. Figure 4EAs described above, the bottom surfaces of the approximate U-shaped cross-section segments 208a-208i of different subsets may be located at different vertical (z-direction) positions (e.g., different depths, different heights) within the groove 402. For example, the approximate U-shaped cross-section segments 208a-208i of the first subset (e.g., approximate U-shaped cross-section segments 208a, 208c, 208e, 208g, and 208i) may be located above the thinner base layer segment 206k (e.g., Figure 4E The second subset, consisting of approximately U-shaped cross-section segments 208a-208i (e.g., approximately U-shaped cross-section segments 208b, 208e, 208f, and 208h), is located above the thicker base layer segment 206k (e.g., ...). Figure 4E (Dimension D12 in the text). Therefore, the bottom surface of the approximate U-shaped cross-section segments 208a-208i of the first subset (e.g., approximate U-shaped cross-section segments 208a, 208c, 208e, 208g, and 208i) may be located at a lower vertical (z-direction) position in the groove 402, lower than the bottom surface of the approximate U-shaped cross-section segments 208a-208i of the second subset (e.g., approximate U-shaped cross-section segments 208b, 208e, 208f, and 208h).

[0113] like Figure 4J As shown, the top electrode structure 210 can be deposited on the insulating layer 208. Therefore, electrode plugs 210a-210i are formed on the insulating layer 208 in the grooves 416a-416i, respectively. A base layer 210j of the top electrode structure 210 is formed above the grooves 416a-416i and connects the electrode plugs 210a-210i together. A portion of the base layer 210j of the top electrode structure 210 may also extend along the top surface of the ILD layer 132. In some embodiments, the top electrode structure 210 is deposited using deposition tools via CVD, ALD, and / or other suitable deposition techniques.

[0114] The top electrode structure 210 can be deposited to a thickness (dimension D16) ranging from about 200 angstroms to about 400 angstroms. However, other values ​​and ranges are also within the scope of this invention. The top electrode structure 210 can be deposited to a sufficient thickness to fill the grooves 416a-416i and form a base layer 210j above the grooves 416a-416i.

[0115] like Figure 4J As further shown, due to the different thicknesses of different segments of the base layer 206k of the bottom electrode structure 206 (e.g. Figure 4EAs described above, the bottom surfaces of different subsets of electrode plugs 210a-210i may be located at different vertical (z-direction) positions (e.g., different depths, different heights) within the main trench structure 202a of capacitor structure 160. For example, a first subset of electrode plugs 210a-210i (e.g., electrode plugs 210a, 210c, 210e, 210g, and 210i) may be located above the thinner base layer segment 206k (e.g., Figure 4E The second subset of electrode plugs 210a-210i (e.g., electrode plugs 210b, 210d, 210f, and 210h) can be located above the thicker base layer segment 206k (e.g., ...). Figure 4E (Dimension D12 in the text). Therefore, the bottom surface of the first subset of electrode plugs 210a-210i (e.g., electrode plugs 210a, 210c, 210e, 210g, and 210i) may be located at a lower vertical (z-direction) position in the main trench structure 202a, lower than the bottom surface of the second subset of electrode plugs 210a-210i (e.g., electrode plugs 210b, 210d, 210f, and 210h).

[0116] like Figure 4K As shown, capping layers 212 and 214 may be formed over the main trench structure 202a of capacitor structure 160. For example, capping layers 212 and 214 may be formed over the base layer 210j of top electrode structure 210 and may extend along the top surface of ILD layer 132. Capping layers 212 and 214 may be deposited using deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, planarization operations (e.g., CMP operations) may be performed using planarization tools to planarize capping layers 212 and / or 214 after deposition.

[0117] An etching operation can be performed to define the upper extension region 202b of the capacitor structure 160. The capping layers 212 and 214 can be etched using etching tools, and the capping layers 212 and 214 can be used as masks for etching the base layer 210j of the top electrode structure 210. In some embodiments, the etching operation may include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0118] like Figure 4KAs further shown, sidewall spacers 216 and 218 are formed at the ends of cap layers 212 and 214, on the ends of the base layer 210j of the top electrode structure 210. The sidewall spacers 216 and 218 can be deposited using deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. The sidewall spacers 216 and 218 can be deposited in one or more deposition operations.

[0119] Another etching operation can be performed to trim portions of the pad 204, the bottom electrode structure 206, and / or the insulating layer 208 in the upper extension region 202b of the capacitor structure 160. Cap layers 212, 214 and sidewall spacers 216, 218 can be used as self-aligning masks to etch portions of the pad 204, the bottom electrode structure 206, and / or the insulating layer 208 in the upper extension region 202b of the capacitor structure 160. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0120] like Figure 4L As shown, additional material can be formed for the ILD layer 132 and the top via 142. To form the top via 142, a groove can be formed through the ILD layer 132 and capping layers 212 and 214 to the base layer 210j of the top electrode structure 210. In some embodiments, the ILD layer 132 is etched using a pattern in a photoresist layer and through the capping layers 212 and 214 to form the groove. In these embodiments, a photoresist layer can be formed on the ILD layer 132 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). The photoresist layer can be exposed to a radiation source using an exposure tool to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The ILD layer 132 can be etched based on the pattern using an etching tool and through the capping layers 212 and 214 to form the groove. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some implementations, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative to pattern-based groove formation.

[0121] Top vias 142 can be deposited using deposition tools employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The top vias 142 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited in a trench, and then the top vias 142 are deposited on the seed layer. In some embodiments, one or more pads are deposited in a trench, and then the top vias 142 are deposited on the pads. Pads may include barrier pads, adhesive pads, and / or other types of pads. Examples of pad materials include tantalum nitride (TaN) and / or titanium nitride (TiN). In some embodiments, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the top vias 142 after deposition.

[0122] As mentioned above, Figures 4A-4L This is provided as an example. Other examples may be related to... Figures 4A-4L The descriptions are different.

[0123] Figure 5 This is a flowchart of an exemplary process 500 related to forming the capacitor structure in the semiconductor device described herein. In some embodiments, it is performed using one or more semiconductor processing tools. Figure 5 One or more process blocks, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, die / die transfer tools and / or other types of semiconductor processing tools.

[0124] like Figure 5 As shown, process 500 may include forming a first dielectric layer (block 510) of an interconnect layer of a semiconductor device over a device layer of the semiconductor device. For example, one or more semiconductor processing tools may be used to form a first dielectric layer (e.g., ILD layer 116, ESL 118, ESL 122, ILD layer 124, ESL 126, ILD layer 128, ESL 130, ILD layer 132) of an interconnect layer (e.g., interconnect layer 106) of a semiconductor device (e.g., semiconductor device 102) over a device layer (e.g., device layer 104, substrate layer 110 of device layer 104), as described herein.

[0125] like Figure 5 As further shown, process 500 may include forming a first groove (box 520) through the first dielectric layer. For example, one or more semiconductor processing tools may be used to form the first groove (e.g., groove 402) through the first dielectric layer, as described herein. In some embodiments, conductive structures in the interconnect layer (e.g., conductive structure 120) are exposed through the first groove.

[0126] like Figure 5As further shown, process 500 may include a first portion (block 530) of a bottom electrode structure in which a capacitor structure is formed on the sidewalls and bottom surface of the first recess. For example, a first portion (e.g., electrode walls 206a and 206j, substrate 206k) of a bottom electrode structure (e.g., bottom electrode structure 206) in which a capacitor structure (e.g., capacitor structure 160) is formed on the sidewalls and bottom surface of the first recess using one or more semiconductor processing tools, as described herein.

[0127] like Figure 5 As further shown, process 500 may include filling a first groove (box 540) with a second dielectric layer on a first portion of the bottom electrode structure. For example, one or more semiconductor processing tools may be used to fill the first groove with a second dielectric layer (e.g., dielectric plug 404) on the first portion of the bottom electrode structure, as described herein.

[0128] like Figure 5 As further shown, process 500 may include forming a plurality of second grooves in the second dielectric layer (box 550). For example, one or more semiconductor processing tools may be used to form a plurality of second grooves (e.g., grooves 406a-404d) in the second dielectric layer, as described herein.

[0129] like Figure 5 As further shown, process 500 may include forming a second portion of a bottom electrode structure on the sidewalls and bottom surfaces of the plurality of second recesses (block 560). For example, the second portion of the bottom electrode structure (e.g., additional portions of electrode walls 206b-206i, base layer 206k) may be formed on the sidewalls and bottom surfaces of the plurality of second recesses using one or more semiconductor processing tools, as described herein.

[0130] like Figure 5 As further shown, process 500 may include an insulating layer (block 570) forming a capacitor structure along a first portion and a second portion of the bottom electrode structure. For example, one or more semiconductor processing tools may be used to form the insulating layer (e.g., insulating layer 208) of the capacitor structure along the first and second portions of the bottom electrode structure, as described herein.

[0131] like Figure 5 As further shown, process 500 may include a top electrode structure (block 580) in which a capacitor structure is formed on an insulating layer. For example, a top electrode structure (e.g., top electrode structure 210) in which a capacitor structure is formed on an insulating layer may be used using one or more semiconductor processing tools, as described herein.

[0132] Process 500 may include additional implementations, such as any single or combined implementations described below and / or one or more other process-related implementations described elsewhere in this document.

[0133] In a first embodiment, the first part forming the bottom electrode structure includes forming a base layer (e.g., base layer 206k) of the bottom electrode structure on the bottom surface of the first groove, and forming an outer vertical wall (e.g., electrode wall 206a and 206j) of the bottom electrode structure on the sidewall of the first groove.

[0134] In the second embodiment, the second part forming the bottom electrode structure, alone or in combination with the first embodiment, includes forming an internal vertical wall (e.g., electrode wall 206b-206i) of the bottom electrode structure on the sidewalls of the plurality of second grooves.

[0135] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 500 includes removing the remaining portion of the second dielectric layer after forming the second portion of the bottom electrode structure, wherein forming the top electrode structure includes forming an elongated plug (e.g., electrode plugs 210a-210i) of the top electrode structure between the outer vertical wall and the inner vertical wall of the bottom electrode structure.

[0136] In the fourth embodiment, the second portion of the bottom electrode structure is formed alone or in combination with one or more of the first to third embodiments, including forming the second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer and etching the second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer, such that the second portion of the bottom electrode structure remains on the sidewalls and bottom surface of the plurality of second grooves.

[0137] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 500 includes filling a plurality of second recesses with patterned plugs (e.g., patterned plugs 414a-414d), wherein a second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer includes a second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer after filling the plurality of second recesses with patterned plugs.

[0138] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 500 includes removing the remaining portion of the second dielectric layer and the patterned plug after etching a second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer.

[0139] In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, removing the patterned plug includes performing a photoresist ashing operation to remove the patterned plug, while removing the remainder of the second dielectric layer includes performing an etching operation to remove the remainder of the second dielectric layer.

[0140] Although Figure 5The example block of process 500 is shown, but in some implementations, process 500 includes more than Figure 5 The diagram depicts more blocks, fewer blocks, different blocks, or blocks with different arrangements. Furthermore, or alternatively, two or more blocks of process 500 can be executed in parallel.

[0141] In this manner, a capacitor structure (e.g., a trench capacitor structure) is formed in the interconnect layer of a semiconductor device. Instead of etching the dielectric layer of the interconnect layer to form trenches for the capacitor structure (e.g., deep trenches), a wide main trench (e.g., with a relatively low aspect ratio) is formed in the dielectric layer of the interconnect layer. The main trench is filled with dielectric plugs, and the dielectric plugs are patterned and used to form multiple pillars of the bottom electrode structure of the capacitor structure. The pillars of the bottom electrode structure define multiple secondary trenches (e.g., with a relatively high aspect ratio) in the main trench, and then filled with insulating layer pads of the capacitor structure and multiple pillars of the top electrode structure of the capacitor structure.

[0142] As described in more detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes: a bottom electrode structure including a first plurality of pillars extending vertically from a first base layer of the bottom electrode structure; an insulating layer located on the sidewalls of the first plurality of pillars and on the first base layer; a top electrode structure including a second plurality of pillars extending vertically from a second base layer of the top electrode structure; and an interconnect structure having a trench region, wherein the first base layer extends along a horizontal plane from one end of the trench region to an opposite end of the trench region and overlaps with the second plurality of pillars.

[0143] In some embodiments, the first plurality of pillars extend vertically above the first substrate; and the second plurality of pillars extend vertically below the second substrate. In some embodiments, the first plurality of pillars and the second plurality of pillars are arranged in a horizontally alternating manner in the semiconductor structure. In some embodiments, the insulating layer comprises a plurality of approximately U-shaped cross-sectional segments; and adjacent approximately U-shaped cross-sectional segments are interconnected at the top of adjacent approximately U-shaped cross-sectional segments. In some embodiments, the plurality of approximately U-shaped cross-sectional segments and the first plurality of pillars are arranged in a horizontally alternating manner in the semiconductor structure. In some embodiments, the second plurality of pillars extend into the plurality of approximately U-shaped cross-sectional segments. In some embodiments, a pad is further included, located between the bottom electrode structure and the underlying conductive structure, wherein the pad extends below the plurality of approximately U-shaped cross-sectional segments, and wherein the plurality of approximately U-shaped cross-sectional segments, the first plurality of pillars, and the second plurality of pillars are arranged in a horizontally alternating manner in the semiconductor structure, without the pad inserted between the approximately U-shaped cross-sectional segments, the first plurality of pillars, and the second plurality of pillars.

[0144] As described in more detail above, some embodiments described herein provide a method. The method includes: forming a first dielectric layer of an interconnect layer of a semiconductor device over a device layer of the semiconductor device; forming a first groove through the first dielectric layer; forming a first portion of a bottom electrode structure of a capacitor structure on the sidewalls and bottom surface of the first groove; filling the first groove with a second dielectric layer on the first portion of the bottom electrode structure; forming a plurality of second grooves in the second dielectric layer; forming a second portion of the bottom electrode structure on the sidewalls and bottom surface of the plurality of second grooves; forming an insulating layer of the capacitor structure along the first and second portions of the bottom electrode structure; and forming a top electrode structure of the capacitor structure on the insulating layer.

[0145] In some embodiments, forming a first portion of the bottom electrode structure includes: forming a base layer of the bottom electrode structure on the bottom surface of the first groove; and forming an outer vertical wall of the bottom electrode structure on the sidewall of the first groove. In some embodiments, forming a second portion of the bottom electrode structure includes: forming an inner vertical wall of the bottom electrode structure on the sidewall of the plurality of second grooves. In some embodiments, it further includes: after forming the second portion of the bottom electrode structure, removing the remaining portion of the second dielectric layer, wherein forming the top electrode structure includes: forming an elongated plug of the top electrode structure between the outer vertical wall and the inner vertical wall of the bottom electrode structure. In some embodiments, forming the second portion of the bottom electrode structure includes: forming the second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer; and etching the second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer such that the second portion of the bottom electrode structure remains on the sidewall and bottom surface of the plurality of second grooves. In some embodiments, the method further includes: filling the plurality of second recesses with patterned plugs, wherein etching a second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer comprises: after filling the plurality of second recesses with the patterned plugs, etching a second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer. In some embodiments, the method further comprises: after etching a second portion of the bottom electrode structure on top of the remaining portion of the second dielectric layer, removing the remaining portion of the second dielectric layer and the patterned plugs. In some embodiments, removing the patterned plugs comprises: performing a photoresist ashing operation to remove the patterned plugs; and removing the remaining portion of the second dielectric layer comprises: performing an etching operation to remove the remaining portion of the second dielectric layer.

[0146] As described in more detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes: a bottom electrode structure including a plurality of electrode walls extending vertically from a first base layer of the bottom electrode structure, wherein a first segment of the first base layer has a first thickness, and a second segment of the first base layer has a second thickness greater than the first thickness; an insulating layer located on the sidewalls of the plurality of electrode walls and on the first base layer; and a top electrode structure including a plurality of electrode plugs extending vertically from a second base layer of the top electrode structure.

[0147] In some embodiments, the first bottom of a first subset of the plurality of electrode plugs located above the first segment of the first base layer is positioned at a lower vertical position than the second bottom of a second subset of the plurality of electrode plugs located above the second segment of the first base layer. In some embodiments, the insulating layer comprises a plurality of approximately U-shaped cross-sectional segments; and adjacent approximately U-shaped cross-sectional segments of the plurality of approximately U-shaped cross-sectional segments are interconnected at the top of adjacent approximately U-shaped cross-sectional segments. In some embodiments, the first bottom of the first subset of the plurality of approximately U-shaped cross-sectional segments located above the first segment of the first base layer is positioned at a lower vertical position than the second bottom of a second subset of the plurality of approximately U-shaped cross-sectional segments located above the second segment of the first base layer. In some embodiments, the plurality of electrode plugs extend into the plurality of approximately U-shaped cross-sectional segments.

[0148] The terms “approximately” and “roughly” can indicate that a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this invention, the terms “approximately” and “roughly” can refer to a percentage of a given quantity value.

[0149] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this invention. Those skilled in the art should understand that this invention can be used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this invention.

Claims

1. A semiconductor structure, characterized in that, include: The bottom electrode structure includes a first plurality of pillars extending vertically from a first base layer of the bottom electrode structure; An insulating layer is located on the sidewalls of the first plurality of pillars and on the first base layer; The top electrode structure includes a second plurality of pillars extending vertically from the second base layer of the top electrode structure; as well as Interconnect structure with trench regions The first base layer extends along a horizontal plane from one end of the trench area to the opposite end of the trench area and overlaps with the second plurality of columns.

2. The semiconductor structure according to claim 1, characterized in that, The first plurality of columns extend vertically above the first base layer; and The second plurality of columns extend vertically below the second base layer.

3. The semiconductor structure according to claim 1, characterized in that, The first plurality of pillars and the second plurality of pillars are arranged in a horizontally alternating manner in the semiconductor structure.

4. The semiconductor structure according to claim 1, characterized in that, The insulating layer comprises multiple approximately U-shaped cross-sectional segments; and Among the plurality of approximate U-shaped cross-sectional segments, adjacent approximate U-shaped cross-sectional segments are connected to each other at the top of the adjacent approximate U-shaped cross-sectional segments.

5. The semiconductor structure according to claim 4, characterized in that, The plurality of approximately U-shaped cross-sectional segments and the first plurality of pillars are arranged in a horizontally alternating manner in the semiconductor structure.

6. The semiconductor structure according to claim 4, characterized in that, The second plurality of columns extend into the plurality of approximately U-shaped cross-sectional segments.

7. The semiconductor structure according to claim 4, characterized in that, Also includes: A pad is located between the bottom electrode structure and the underlying conductive structure. The gasket extends below the plurality of approximately U-shaped cross-sectional segments, and The plurality of approximately U-shaped cross-sectional segments, the first plurality of pillars, and the second plurality of pillars are arranged in a horizontally alternating manner in the semiconductor structure, and no pads are inserted between the approximately U-shaped cross-sectional segments, the first plurality of pillars, and the second plurality of pillars.

8. A semiconductor structure, characterized in that, include: The bottom electrode structure includes multiple electrode walls that extend vertically from a first base layer of the bottom electrode structure. The first segment of the first base layer each has a first thickness, and Each of the second segments of the first base layer has a second thickness, which is greater than the first thickness. An insulating layer is located on the sidewalls of the plurality of electrode walls and on the first base layer; as well as The top electrode structure includes a plurality of electrode plugs that extend vertically from a second base layer of the top electrode structure.

9. The semiconductor structure according to claim 8, characterized in that, The first bottom of the first subset of the plurality of electrode plugs located above the first segment of the first base layer is located at a lower vertical position than the second bottom of the second subset of the plurality of electrode plugs located above the second segment of the first base layer.

10. The semiconductor structure according to claim 8, characterized in that, The insulating layer comprises multiple approximately U-shaped cross-sectional segments; and The adjacent approximate U-shaped cross-sectional segments of the plurality of approximate U-shaped cross-sectional segments are connected to each other at the top of the adjacent approximate U-shaped cross-sectional segments.

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